mirror of
https://github.com/dingusdev/dingusppc.git
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d91e14abc6
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first. The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging. The result is that this command in Open Firmware: `12345678 16800 config-l!` will log this: `VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
406 lines
15 KiB
C++
406 lines
15 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Bandit ARBus-to-PCI Bridge emulation. */
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#include <devices/common/pci/bandit.h>
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <memaccess.h>
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#include <cinttypes>
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const int MultiplyDeBruijnBitPosition2[] =
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{
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0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
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31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
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};
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/** finds the position of the bit that is set */
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#define WHAT_BIT_SET(val) (MultiplyDeBruijnBitPosition2[(uint32_t)(val * 0x077CB531U) >> 27])
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Bandit::Bandit(int bridge_num, std::string name) : PCIHost(), PCIDevice(name)
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{
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supports_types(HWCompType::PCI_HOST | HWCompType::PCI_DEV);
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this->base_addr = 0xF0000000 + ((bridge_num & 3) << 25);
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MemCtrlBase *mem_ctrl = dynamic_cast<MemCtrlBase *>
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(gMachineObj->get_comp_by_type(HWCompType::MEM_CTRL));
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// add memory mapped I/O region for Bandit control registers
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// This region has the following layout:
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// base_addr + 0x000000 --> I/O space
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// base_addr + 0x800000 --> CONFIG_ADDR
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// base_addr + 0xC00000 --> CONFIG_DATA
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// base_addr + 0x1000000 --> pass-through memory space (not included below)
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mem_ctrl->add_mmio_region(base_addr, 0x01000000, this);
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// prepare the PCI config header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 0x0001;
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this->class_rev = 0x06000003;
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this->cache_ln_sz = 8;
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this->command = 0x16;
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// make several PCI config space registers read-only
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this->pci_wr_cmd = [](uint16_t cmd) {}; // command register
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this->pci_wr_cache_lnsz = [](uint8_t val) {}; // cache line size register
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// set the bits in the fine address space field of the address mask register
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// that correspond to the 32MB assigned PCI address space of this Bandit.
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// This initialization is implied by the device functionality.
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this->addr_mask = 3 << ((bridge_num & 3) * 2);
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this->name = name;
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}
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uint32_t Bandit::pci_cfg_read(uint32_t reg_offs, uint32_t size)
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{
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if (reg_offs < 64) {
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return PCIDevice::pci_cfg_read(reg_offs, size);
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}
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switch (reg_offs) {
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case BANDIT_ADDR_MASK:
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return BYTESWAP_32(this->addr_mask);
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default:
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LOG_F(WARNING, "%s: reading from unimplemented config register at 0x%X",
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this->pci_name.c_str(), reg_offs);
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}
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return 0;
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}
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void Bandit::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size)
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{
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, size);
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return;
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}
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switch (reg_offs) {
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case BANDIT_ADDR_MASK:
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this->addr_mask = BYTESWAP_32(value);
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this->verbose_address_space();
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break;
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default:
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LOG_F(WARNING, "%s: writing to unimplemented config register at 0x%X",
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this->pci_name.c_str(), reg_offs);
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}
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}
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uint32_t Bandit::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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int bus_num, dev_num, fun_num;
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uint8_t reg_offs;
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uint32_t result, idsel;
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if (offset & BANDIT_CONFIG_SPACE) {
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if (offset & 0x00400000) {
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fun_num = (this->config_addr >> 8) & 7;
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reg_offs = this->config_addr & 0xFCU;
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// access to the CONFIG_DATA pseudo-register causes a Config Cycle
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if (this->config_addr & BANDIT_CAR_TYPE) {
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bus_num = (this->config_addr >> 16) & 255;
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dev_num = (this->config_addr >> 11) & 31;
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LOG_F(
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WARNING, "%s: read config cycle type 1 not supported yet %02x:%02x.%x @%02x.%c",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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idsel = (this->config_addr >> 11) & 0x1FFFFFU;
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if (!SINGLE_BIT_SET(idsel)) {
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LOG_F(
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ERROR, "%s: read invalid IDSEL=0x%X config:0x%X ??:??.%x? @%02x?.%c",
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this->name.c_str(), idsel, this->config_addr,
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fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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if (idsel == BANDIT_ID_SEL) { // access to myself
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result = this->pci_cfg_read(reg_offs, size);
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} else {
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if (this->dev_map.count(idsel)) {
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result = this->dev_map[idsel]->pci_cfg_read(reg_offs, size);
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} else {
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dev_num = WHAT_BIT_SET(idsel) + 11;
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LOG_F(
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ERROR, "%s err: read attempt from non-existing PCI device ??:%02x.%x @%02x.%c",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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}
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} else {
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result = this->config_addr;
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}
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} else { // I/O space access
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_read(offset, size, &result)) {
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return result;
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}
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}
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LOG_F(ERROR, "%s: attempt to read from unmapped PCI I/O space, offset=0x%X",
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this->name.c_str(), offset);
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}
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return result;
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}
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void Bandit::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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int bus_num, dev_num, fun_num;
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uint8_t reg_offs;
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uint32_t idsel;
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if (offset & BANDIT_CONFIG_SPACE) {
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if (offset & 0x00400000) {
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fun_num = (this->config_addr >> 8) & 7;
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reg_offs = this->config_addr & 0xFCU;
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// access to the CONFIG_DATA pseudo-register causes a Config Cycle
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if (this->config_addr & BANDIT_CAR_TYPE) {
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bus_num = (this->config_addr >> 16) & 255;
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dev_num = (this->config_addr >> 11) & 31;
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LOG_F(
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WARNING, "%s: write config cycle type 1 not supported yet %02x:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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return;
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}
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idsel = (this->config_addr >> 11) & 0x1FFFFFU;
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if (!SINGLE_BIT_SET(idsel)) {
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LOG_F(
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ERROR, "%s: write invalid IDSEL=0x%X config:0x%X ??:??.%x? @%02x?.%c = %0*x",
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this->name.c_str(), idsel, this->config_addr,
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fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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return;
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}
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if (idsel == BANDIT_ID_SEL) { // access to myself
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this->pci_cfg_write(reg_offs, value, size);
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return;
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}
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if (this->dev_map.count(idsel)) {
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this->dev_map[idsel]->pci_cfg_write(reg_offs, value, size);
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} else {
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dev_num = WHAT_BIT_SET(idsel) + 11;
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LOG_F(
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ERROR, "%s err: write attempt to non-existing PCI device ??:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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}
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} else {
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this->config_addr = BYTESWAP_32(value);
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}
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} else { // I/O space access
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// broadcast I/O request to devices that support I/O space
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// until a device returns true that means "request accepted"
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for (auto& dev : this->io_space_devs) {
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if (dev->pci_io_write(offset, value, size)) {
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return;
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}
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}
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LOG_F(ERROR, "%s: attempt to write to unmapped PCI I/O space, offset=0x%X",
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this->name.c_str(), offset);
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}
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}
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void Bandit::verbose_address_space()
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{
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uint32_t mask;
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int bit_pos;
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LOG_F(INFO, "%s address spaces:", this->pci_name.c_str());
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// verbose coarse aka 256MB memory regions
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for (mask = 0x10000, bit_pos = 0; mask != 0x80000000UL; mask <<= 1, bit_pos++) {
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if (this->addr_mask & mask) {
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uint32_t start_addr = bit_pos << 28;
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LOG_F(INFO, "- 0x%X ... 0x%X", start_addr, start_addr + 0x0FFFFFFFU);
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}
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}
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// verbose fine aka 16MB memory regions
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for (mask = 0x1, bit_pos = 0; mask != 0x10000UL; mask <<= 1, bit_pos++) {
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if (this->addr_mask & mask) {
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uint32_t start_addr = (bit_pos << 24) + 0xF0000000UL;
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LOG_F(INFO, "- 0x%X ... 0x%X", start_addr, start_addr + 0x00FFFFFFU);
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}
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}
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}
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Chaos::Chaos(std::string name) : PCIHost()
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{
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supports_types(HWCompType::PCI_HOST);
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MemCtrlBase *mem_ctrl = dynamic_cast<MemCtrlBase *>
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(gMachineObj->get_comp_by_type(HWCompType::MEM_CTRL));
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// add memory mapped I/O region for Chaos control registers
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// This region has the following layout:
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// base_addr + 0x800000 --> CONFIG_ADDR
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// base_addr + 0xC00000 --> CONFIG_DATA
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mem_ctrl->add_mmio_region(0xF0000000UL, 0x01000000, this);
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this->name = name;
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}
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uint32_t Chaos::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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int bus_num, dev_num, fun_num;
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uint8_t reg_offs;
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uint32_t result, idsel;
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if (offset & BANDIT_CONFIG_SPACE) {
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if (offset & 0x00400000) {
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fun_num = (this->config_addr >> 8) & 7;
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reg_offs = this->config_addr & 0xFCU;
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// access to the CONFIG_DATA pseudo-register causes a Config Cycle
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if (this->config_addr & BANDIT_CAR_TYPE) {
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bus_num = (this->config_addr >> 16) & 255;
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dev_num = (this->config_addr >> 11) & 31;
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LOG_F(
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WARNING, "%s: read config cycle type 1 not supported yet %02x:%02x.%x @%02x.%c",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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idsel = (this->config_addr >> 11) & 0x1FFFFFU;
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if (!SINGLE_BIT_SET(idsel)) {
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LOG_F(
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ERROR, "%s: read invalid IDSEL=0x%X config:0x%X ??:??.%x? @%02x?.%c",
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this->name.c_str(), idsel, this->config_addr,
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fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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if (this->dev_map.count(idsel)) {
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result = this->dev_map[idsel]->pci_cfg_read(reg_offs, size);
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} else {
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dev_num = WHAT_BIT_SET(idsel) + 11;
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LOG_F(
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ERROR, "%s err: read attempt from non-existing VCI device ??:%02x.%x @%02x.%c",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size
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);
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return 0xFFFFFFFFUL; // PCI spec §6.1
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}
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} else {
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result = this->config_addr;
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}
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} else { // I/O space access
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LOG_F(ERROR, "%s: I/O space not supported", this->name.c_str());
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return 0;
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}
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return result;
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}
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void Chaos::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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int bus_num, dev_num, fun_num;
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uint8_t reg_offs;
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uint32_t idsel;
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if (offset & BANDIT_CONFIG_SPACE) {
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if (offset & 0x00400000) {
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fun_num = (this->config_addr >> 8) & 7;
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reg_offs = this->config_addr & 0xFCU;
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// access to the CONFIG_DATA pseudo-register causes a Config Cycle
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if (this->config_addr & BANDIT_CAR_TYPE) {
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bus_num = (this->config_addr >> 16) & 255;
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dev_num = (this->config_addr >> 11) & 31;
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LOG_F(
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WARNING, "%s: write config cycle type 1 not supported yet %02x:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), bus_num, dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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return;
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}
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idsel = (this->config_addr >> 11) & 0x1FFFFFU;
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if (!SINGLE_BIT_SET(idsel)) {
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LOG_F(
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ERROR, "%s: write invalid IDSEL=0x%X config:0x%X ??:??.%x? @%02x?.%c = %0*x",
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this->name.c_str(), idsel, this->config_addr,
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fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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return;
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}
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if (this->dev_map.count(idsel)) {
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this->dev_map[idsel]->pci_cfg_write(reg_offs, value, size);
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} else {
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dev_num = WHAT_BIT_SET(idsel) + 11;
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LOG_F(
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ERROR, "%s err: write attempt to non-existing VCI device ??:%02x.%x @%02x.%c = %0*x",
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this->name.c_str(), dev_num, fun_num, reg_offs + (offset & 3),
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size == 4 ? 'l' : size == 2 ? 'w' : size == 1 ? 'b' : '0' + size, size * 2, flip_sized(value, size)
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);
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}
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} else {
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this->config_addr = BYTESWAP_32(value);
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}
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} else { // I/O space access
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LOG_F(ERROR, "%s: I/O space not supported", this->name.c_str());
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}
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}
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static const DeviceDescription Bandit1_Descriptor = {
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Bandit::create_first, {}, {}
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};
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static const DeviceDescription Chaos_Descriptor = {
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Chaos::create, {}, {}
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};
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REGISTER_DEVICE(Bandit1, Bandit1_Descriptor);
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REGISTER_DEVICE(Chaos, Chaos_Descriptor);
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