mirror of
https://github.com/dingusdev/dingusppc.git
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170 lines
5.2 KiB
C++
170 lines
5.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Hammerhead Memory Controller emulation. */
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/hammerhead.h>
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#include <loguru.hpp>
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#include <cinttypes>
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#include <memory>
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using namespace Hammerhead;
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HammerheadCtrl::HammerheadCtrl() : MemCtrlBase()
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{
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this->name = "Hammerhead Memory Controller";
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV);
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// add MMIO region for the configuration and status registers
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add_mmio_region(0xF8000000, 0x500, this);
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}
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uint32_t HammerheadCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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uint32_t result;
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if (offset >= HammerheadReg::BANK_0_BASE_MSB &&
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offset <= HammerheadReg::BANK_25_BASE_LSB) {
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offset = (offset - HammerheadReg::BANK_0_BASE_MSB) >> 4;
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if (offset & 1) { // return the LSB part
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result = bank_base[offset >> 1] & 0xFFU;
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} else { // return the MSB part
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result = bank_base[offset >> 1] >> 8;
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}
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goto finish;
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}
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switch (offset) {
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case HammerheadReg::CPU_ID:
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result = HH_CPU_ID_TNT;
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break;
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case HammerheadReg::MOTHERBOARD_ID:
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result = (this->mb_id << 5) | (this->rom_type << 4);
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break;
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case HammerheadReg::CPU_SPEED:
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result = this->bus_speed << 5;
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break;
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case HammerheadReg::ARBITER_CONFIG:
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result = this->arb_config;
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break;
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case HammerheadReg::WHO_AM_I:
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result = BM_PRIMARY_CPU << 3;
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break;
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case HammerheadReg::L2_CACHE_CONFIG:
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result = 0; // say there is no L2 cache
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break;
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default:
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LOG_F(WARNING, "Hammerhead: unknown register read at offset 0x%X", offset);
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return 0;
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}
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// Hammerhead registers are one byte wide so always place
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// the result in the MSB of a multibyte read
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finish:
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return result << ((size - 1) << 3);
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}
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void HammerheadCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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// extract byte value from the MSB of a multibyte value
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value = value >> ((size - 1) << 3);
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if (offset >= HammerheadReg::BANK_0_BASE_MSB &&
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offset <= HammerheadReg::BANK_25_BASE_LSB) {
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offset = (offset - HammerheadReg::BANK_0_BASE_MSB) >> 4;
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if (offset & 1) { // update the LSB part
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bank_base[offset >> 1] = (bank_base[offset >> 1] & 0xFF00U) | value;
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} else { // update the MSB part
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bank_base[offset >> 1] = (bank_base[offset >> 1] & 0x00FFU) | (value << 8);
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}
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LOG_F(INFO, "Hammerhead: bank base #%d set to 0x%X", offset >> 1, bank_base[offset >> 1]);
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return;
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}
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switch (offset) {
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case HammerheadReg::MEM_TIMING_0:
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LOG_F(9, "Hammerhead: MEM_TIMING_0 set to 0x%X", value);
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break;
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case HammerheadReg::MEM_TIMING_1:
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LOG_F(9, "Hammerhead: MEM_TIMING_1 set to 0x%X", value);
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break;
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case HammerheadReg::REFRESH_TIMING:
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LOG_F(9, "Hammerhead: REFRESH_TIMING set to 0x%X", value);
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break;
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case HammerheadReg::ROM_TIMING:
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LOG_F(9, "Hammerhead: ROM_TIMING set to 0x%X", value);
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break;
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case HammerheadReg::ARBITER_CONFIG:
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this->arb_config = value;
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break;
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default:
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LOG_F(WARNING, "Hammerhead: unknown register write at offset 0x%X", offset);
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}
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}
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void HammerheadCtrl::insert_ram_dimm(int slot_num, uint32_t capacity)
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{
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if (slot_num < 0 || slot_num >= 26) {
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ABORT_F("Hammerhead: invalid DIMM slot number %d", slot_num);
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}
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switch (capacity) {
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case DRAM_CAP_2MB:
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case DRAM_CAP_4MB:
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case DRAM_CAP_8MB:
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case DRAM_CAP_16MB:
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case DRAM_CAP_32MB:
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case DRAM_CAP_64MB:
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this->bank_size[slot_num * 2 + 0] = capacity;
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break;
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case DRAM_CAP_128MB:
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this->bank_size[slot_num * 2 + 0] = DRAM_CAP_64MB;
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this->bank_size[slot_num * 2 + 1] = DRAM_CAP_64MB;
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break;
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default:
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ABORT_F("Hammerhead: unsupported DRAM capacity %d", capacity);
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}
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}
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void HammerheadCtrl::map_phys_ram()
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{
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uint32_t total_ram = 0;
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for (int i = 0; i < 26; i++) {
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total_ram += this->bank_size[i];
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}
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LOG_F(INFO, "Hammerhead: total RAM size = %d bytes", total_ram);
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if (!add_ram_region(0x00000000, total_ram)) {
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ABORT_F("Hammerhead: could not allocate physical RAM storage");
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}
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}
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static const DeviceDescription Hammerhead_Descriptor = {
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HammerheadCtrl::create, {}, {}
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};
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REGISTER_DEVICE(Hammerhead, Hammerhead_Descriptor);
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