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add instruction timings

This commit is contained in:
Matthew Laux 2022-06-20 19:09:29 -05:00
parent 571b92bb99
commit 3d6d3a0171
10 changed files with 557 additions and 310 deletions
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3
.gitignore vendored
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@ -12,4 +12,5 @@ cmake_install.cmake
include
lib
imgui.ini
.DS_Store
roms

2
cli/emulator.c
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@ -32,7 +32,7 @@ int main(int argc, char *argv[])
cpu.pc = 0;
for (executed = 0; executed < 1000000; executed++) {
for (executed = 0; executed < 100000; executed++) {
dmg_step(&dmg);
}

32
get_opcodes.js
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@ -1,13 +1,25 @@
let total = 0;
let rows = document.getElementsByTagName('tr');
let val = "";
for (let row = 1; row < rows.length; row++) {
let cols = rows[row].getElementsByTagName("td");
for (let col = 1; col < cols.length; col++) {
let html = cols[col].innerHTML;
if (html.indexOf("<br>") != -1) {
html = html.substring(0, html.indexOf("<br>"));
}
console.log("{ 0x" + total.toString(16) + ", \"" + html + "\" },");
total++;
}
}
let cols = rows[row].getElementsByTagName("td");
for (let col = 0; col < cols.length; col++) {
let html = cols[col].innerText.split('\n');
if (html.length >= 2) {
let insnName = html[0];
let cycleCounts = html[1].split(' ')[1];
let branchParts = cycleCounts.split('-');
let cycleCount = branchParts[0].substring(0, branchParts[0].length - 1);
let cycleCountBranch = cycleCount;
if (branchParts.length > 1) {
cycleCountBranch = branchParts[1].substring(0, branchParts[1].length - 1);
}
val += "{ 0x" + total.toString(16) + ", \"" + insnName + "\", " + cycleCount + ", " + cycleCountBranch + " },";
} else {
val += "{ 0x" + total.toString(16) + ", \"<invalid>\", 0, 0 },";
}
total++;
}
}
console.log(val);

49
src/cpu.c
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@ -31,57 +31,26 @@ static inline void clear_flag(struct cpu *cpu, int flag)
cpu->f &= ~flag;
}
static inline u16 read_af(struct cpu *cpu)
{
return cpu->a << 8 | cpu->f;
}
static inline u16 read_bc(struct cpu *cpu)
{
return cpu->b << 8 | cpu->c;
}
static inline u16 read_de(struct cpu *cpu)
{
return cpu->d << 8 | cpu->e;
}
static inline u16 read_hl(struct cpu *cpu)
{
return cpu->h << 8 | cpu->l;
}
static inline u16 read_double_reg(struct cpu *cpu, u8 *rh, u8 *rl)
{
return *rh << 8 | *rl;
}
static inline void write_af(struct cpu *cpu, int value)
{
cpu->a = value >> 8;
cpu->f = value & 0xff;
}
#define read_af(cpu) read_double_reg((cpu), &(cpu)->a, &(cpu)->f)
#define read_bc(cpu) read_double_reg((cpu), &(cpu)->b, &(cpu)->c)
#define read_de(cpu) read_double_reg((cpu), &(cpu)->d, &(cpu)->e)
#define read_hl(cpu) read_double_reg((cpu), &(cpu)->h, &(cpu)->l)
static inline void write_bc(struct cpu *cpu, int value)
{
cpu->b = value >> 8;
cpu->c = value & 0xff;
}
static inline void write_de(struct cpu *cpu, int value)
{
cpu->d = value >> 8;
cpu->e = value & 0xff;
}
// TODO figure out if I like this style better and convert write_af, etc to this
static inline void write_double_reg(struct cpu *cpu, u8 *rh, u8 *rl, int value)
{
*rh = value >> 8;
*rl = value & 0xff;
}
#define write_hl(cpu, value) write_double_reg((cpu), &cpu->h, &cpu->l, value)
#define write_af(cpu, value) write_double_reg((cpu), &(cpu)->a, &(cpu)->f, value)
#define write_bc(cpu, value) write_double_reg((cpu), &(cpu)->b, &(cpu)->c, value)
#define write_de(cpu, value) write_double_reg((cpu), &(cpu)->d, &(cpu)->e, value)
#define write_hl(cpu, value) write_double_reg((cpu), &(cpu)->h, &(cpu)->l, value)
void cpu_panic(struct cpu *cpu)
{
@ -361,7 +330,6 @@ void cpu_step(struct cpu *cpu)
u8 opc = cpu->mem_read(cpu->mem_model, cpu->pc);
printf("0x%04x %s\n", cpu->pc, instructions[opc].format);
cpu->pc++;
if (cpu->pc == 0x100) exit(0);
switch (opc) {
case 0: // NOP
break;
@ -696,7 +664,6 @@ void cpu_step(struct cpu *cpu)
case 0xf0: // LDH A,(a8)
cpu->a = read16(cpu, 0xff00 + read8(cpu, cpu->pc));
cpu->pc++;
printf("scanline was %d\n", cpu->a);
break;
case 0xf2: // LD A,(C)
cpu->a = read8(cpu, 0xff00 + cpu->c);

1
src/cpu.h
View File

@ -15,6 +15,7 @@ struct cpu
u8 l;
u16 sp;
u16 pc;
u32 cycle_count;
u8 (*mem_read)(void *, u16);
void (*mem_write)(void *, u16, u8);

5
src/dmg.c
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@ -75,5 +75,8 @@ void dmg_step(void *_dmg)
// all other hw
cpu_step(dmg->cpu);
lcd_step(dmg->lcd);
if (dmg->cpu->pc % 456 == 0) {
// each line takes 456 cycles
lcd_step(dmg->lcd);
}
}

1
src/dmg.h
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@ -3,6 +3,7 @@
#include "cpu.h"
#include "rom.h"
#include "lcd.h"
struct dmg {
struct cpu *cpu;

770
src/instructions.c
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@ -1,260 +1,518 @@
#include "instructions.h"
const struct instruction instructions[] = {
{ 0x0, "NOP" },
{ 0x1, "LD BC,d16" },
{ 0x2, "LD (BC),A" },
{ 0x3, "INC BC" },
{ 0x4, "INC B" },
{ 0x5, "DEC B" },
{ 0x6, "LD B,d8" },
{ 0x7, "RLCA" },
{ 0x8, "LD (a16),SP" },
{ 0x9, "ADD HL,BC" },
{ 0xa, "LD A,(BC)" },
{ 0xb, "DEC BC" },
{ 0xc, "INC C" },
{ 0xd, "DEC C" },
{ 0xe, "LD C,d8" },
{ 0xf, "RRCA" },
{ 0x10, "STOP 0" },
{ 0x11, "LD DE,d16" },
{ 0x12, "LD (DE),A" },
{ 0x13, "INC DE" },
{ 0x14, "INC D" },
{ 0x15, "DEC D" },
{ 0x16, "LD D,d8" },
{ 0x17, "RLA" },
{ 0x18, "JR r8" },
{ 0x19, "ADD HL,DE" },
{ 0x1a, "LD A,(DE)" },
{ 0x1b, "DEC DE" },
{ 0x1c, "INC E" },
{ 0x1d, "DEC E" },
{ 0x1e, "LD E,d8" },
{ 0x1f, "RRA" },
{ 0x20, "JR NZ,r8" },
{ 0x21, "LD HL,d16" },
{ 0x22, "LD (HL+),A" },
{ 0x23, "INC HL" },
{ 0x24, "INC H" },
{ 0x25, "DEC H" },
{ 0x26, "LD H,d8" },
{ 0x27, "DAA" },
{ 0x28, "JR Z,r8" },
{ 0x29, "ADD HL,HL" },
{ 0x2a, "LD A,(HL+)" },
{ 0x2b, "DEC HL" },
{ 0x2c, "INC L" },
{ 0x2d, "DEC L" },
{ 0x2e, "LD L,d8" },
{ 0x2f, "CPL" },
{ 0x30, "JR NC,r8" },
{ 0x31, "LD SP,d16" },
{ 0x32, "LD (HL-),A" },
{ 0x33, "INC SP" },
{ 0x34, "INC (HL)" },
{ 0x35, "DEC (HL)" },
{ 0x36, "LD (HL),d8" },
{ 0x37, "SCF" },
{ 0x38, "JR C,r8" },
{ 0x39, "ADD HL,SP" },
{ 0x3a, "LD A,(HL-)" },
{ 0x3b, "DEC SP" },
{ 0x3c, "INC A" },
{ 0x3d, "DEC A" },
{ 0x3e, "LD A,d8" },
{ 0x3f, "CCF" },
{ 0x40, "LD B,B" },
{ 0x41, "LD B,C" },
{ 0x42, "LD B,D" },
{ 0x43, "LD B,E" },
{ 0x44, "LD B,H" },
{ 0x45, "LD B,L" },
{ 0x46, "LD B,(HL)" },
{ 0x47, "LD B,A" },
{ 0x48, "LD C,B" },
{ 0x49, "LD C,C" },
{ 0x4a, "LD C,D" },
{ 0x4b, "LD C,E" },
{ 0x4c, "LD C,H" },
{ 0x4d, "LD C,L" },
{ 0x4e, "LD C,(HL)" },
{ 0x4f, "LD C,A" },
{ 0x50, "LD D,B" },
{ 0x51, "LD D,C" },
{ 0x52, "LD D,D" },
{ 0x53, "LD D,E" },
{ 0x54, "LD D,H" },
{ 0x55, "LD D,L" },
{ 0x56, "LD D,(HL)" },
{ 0x57, "LD D,A" },
{ 0x58, "LD E,B" },
{ 0x59, "LD E,C" },
{ 0x5a, "LD E,D" },
{ 0x5b, "LD E,E" },
{ 0x5c, "LD E,H" },
{ 0x5d, "LD E,L" },
{ 0x5e, "LD E,(HL)" },
{ 0x5f, "LD E,A" },
{ 0x60, "LD H,B" },
{ 0x61, "LD H,C" },
{ 0x62, "LD H,D" },
{ 0x63, "LD H,E" },
{ 0x64, "LD H,H" },
{ 0x65, "LD H,L" },
{ 0x66, "LD H,(HL)" },
{ 0x67, "LD H,A" },
{ 0x68, "LD L,B" },
{ 0x69, "LD L,C" },
{ 0x6a, "LD L,D" },
{ 0x6b, "LD L,E" },
{ 0x6c, "LD L,H" },
{ 0x6d, "LD L,L" },
{ 0x6e, "LD L,(HL)" },
{ 0x6f, "LD L,A" },
{ 0x70, "LD (HL),B" },
{ 0x71, "LD (HL),C" },
{ 0x72, "LD (HL),D" },
{ 0x73, "LD (HL),E" },
{ 0x74, "LD (HL),H" },
{ 0x75, "LD (HL),L" },
{ 0x76, "HALT" },
{ 0x77, "LD (HL),A" },
{ 0x78, "LD A,B" },
{ 0x79, "LD A,C" },
{ 0x7a, "LD A,D" },
{ 0x7b, "LD A,E" },
{ 0x7c, "LD A,H" },
{ 0x7d, "LD A,L" },
{ 0x7e, "LD A,(HL)" },
{ 0x7f, "LD A,A" },
{ 0x80, "ADD A,B" },
{ 0x81, "ADD A,C" },
{ 0x82, "ADD A,D" },
{ 0x83, "ADD A,E" },
{ 0x84, "ADD A,H" },
{ 0x85, "ADD A,L" },
{ 0x86, "ADD A,(HL)" },
{ 0x87, "ADD A,A" },
{ 0x88, "ADC A,B" },
{ 0x89, "ADC A,C" },
{ 0x8a, "ADC A,D" },
{ 0x8b, "ADC A,E" },
{ 0x8c, "ADC A,H" },
{ 0x8d, "ADC A,L" },
{ 0x8e, "ADC A,(HL)" },
{ 0x8f, "ADC A,A" },
{ 0x90, "SUB B" },
{ 0x91, "SUB C" },
{ 0x92, "SUB D" },
{ 0x93, "SUB E" },
{ 0x94, "SUB H" },
{ 0x95, "SUB L" },
{ 0x96, "SUB (HL)" },
{ 0x97, "SUB A" },
{ 0x98, "SBC A,B" },
{ 0x99, "SBC A,C" },
{ 0x9a, "SBC A,D" },
{ 0x9b, "SBC A,E" },
{ 0x9c, "SBC A,H" },
{ 0x9d, "SBC A,L" },
{ 0x9e, "SBC A,(HL)" },
{ 0x9f, "SBC A,A" },
{ 0xa0, "AND B" },
{ 0xa1, "AND C" },
{ 0xa2, "AND D" },
{ 0xa3, "AND E" },
{ 0xa4, "AND H" },
{ 0xa5, "AND L" },
{ 0xa6, "AND (HL)" },
{ 0xa7, "AND A" },
{ 0xa8, "XOR B" },
{ 0xa9, "XOR C" },
{ 0xaa, "XOR D" },
{ 0xab, "XOR E" },
{ 0xac, "XOR H" },
{ 0xad, "XOR L" },
{ 0xae, "XOR (HL)" },
{ 0xaf, "XOR A" },
{ 0xb0, "OR B" },
{ 0xb1, "OR C" },
{ 0xb2, "OR D" },
{ 0xb3, "OR E" },
{ 0xb4, "OR H" },
{ 0xb5, "OR L" },
{ 0xb6, "OR (HL)" },
{ 0xb7, "OR A" },
{ 0xb8, "CP B" },
{ 0xb9, "CP C" },
{ 0xba, "CP D" },
{ 0xbb, "CP E" },
{ 0xbc, "CP H" },
{ 0xbd, "CP L" },
{ 0xbe, "CP (HL)" },
{ 0xbf, "CP A" },
{ 0xc0, "RET NZ" },
{ 0xc1, "POP BC" },
{ 0xc2, "JP NZ,a16" },
{ 0xc3, "JP a16" },
{ 0xc4, "CALL NZ,a16" },
{ 0xc5, "PUSH BC" },
{ 0xc6, "ADD A,d8" },
{ 0xc7, "RST 00H" },
{ 0xc8, "RET Z" },
{ 0xc9, "RET" },
{ 0xca, "JP Z,a16" },
{ 0xcb, "PREFIX CB" },
{ 0xcc, "CALL Z,a16" },
{ 0xcd, "CALL a16" },
{ 0xce, "ADC A,d8" },
{ 0xcf, "RST 08H" },
{ 0xd0, "RET NC" },
{ 0xd1, "POP DE" },
{ 0xd2, "JP NC,a16" },
{ 0xd3, "<invalid>" },
{ 0xd4, "CALL NC,a16" },
{ 0xd5, "PUSH DE" },
{ 0xd6, "SUB d8" },
{ 0xd7, "RST 10H" },
{ 0xd8, "RET C" },
{ 0xd9, "RETI" },
{ 0xda, "JP C,a16" },
{ 0xdb, "<invalid>" },
{ 0xdc, "CALL C,a16" },
{ 0xdd, "<invalid>" },
{ 0xde, "SBC A,d8" },
{ 0xdf, "RST 18H" },
{ 0xe0, "LDH (a8),A" },
{ 0xe1, "POP HL" },
{ 0xe2, "LD (C),A" },
{ 0xe3, "<invalid>" },
{ 0xe4, "<invalid>" },
{ 0xe5, "PUSH HL" },
{ 0xe6, "AND d8" },
{ 0xe7, "RST 20H" },
{ 0xe8, "ADD SP,r8" },
{ 0xe9, "JP (HL)" },
{ 0xea, "LD (a16),A" },
{ 0xeb, "<invalid>" },
{ 0xec, "<invalid>" },
{ 0xed, "<invalid>" },
{ 0xee, "XOR d8" },
{ 0xef, "RST 28H" },
{ 0xf0, "LDH A,(a8)" },
{ 0xf1, "POP AF" },
{ 0xf2, "LD A,(C)" },
{ 0xf3, "DI" },
{ 0xf4, "<invalid>" },
{ 0xf5, "PUSH AF" },
{ 0xf6, "OR d8" },
{ 0xf7, "RST 30H" },
{ 0xf8, "LD HL,SP+r8" },
{ 0xf9, "LD SP,HL" },
{ 0xfa, "LD A,(a16)" },
{ 0xfb, "EI" },
{ 0xfc, "<invalid>" },
{ 0xfd, "<invalid>" },
{ 0xfe, "CP d8" },
{ 0xff, "RST 38H" },
{0x0, "NOP", 4, 4},
{0x1, "LD BC,u16", 12, 12},
{0x2, "LD (BC),A", 8, 8},
{0x3, "INC BC", 8, 8},
{0x4, "INC B", 4, 4},
{0x5, "DEC B", 4, 4},
{0x6, "LD B,u8", 8, 8},
{0x7, "RLCA", 4, 4},
{0x8, "LD (u16),SP", 20, 20},
{0x9, "ADD HL,BC", 8, 8},
{0xa, "LD A,(BC)", 8, 8},
{0xb, "DEC BC", 8, 8},
{0xc, "INC C", 4, 4},
{0xd, "DEC C", 4, 4},
{0xe, "LD C,u8", 8, 8},
{0xf, "RRCA", 4, 4},
{0x10, "STOP", 4, 4},
{0x11, "LD DE,u16", 12, 12},
{0x12, "LD (DE),A", 8, 8},
{0x13, "INC DE", 8, 8},
{0x14, "INC D", 4, 4},
{0x15, "DEC D", 4, 4},
{0x16, "LD D,u8", 8, 8},
{0x17, "RLA", 4, 4},
{0x18, "JR i8", 12, 12},
{0x19, "ADD HL,DE", 8, 8},
{0x1a, "LD A,(DE)", 8, 8},
{0x1b, "DEC DE", 8, 8},
{0x1c, "INC E", 4, 4},
{0x1d, "DEC E", 4, 4},
{0x1e, "LD E,u8", 8, 8},
{0x1f, "RRA", 4, 4},
{0x20, "JR NZ,i8", 8, 12},
{0x21, "LD HL,u16", 12, 12},
{0x22, "LD (HL+),A", 8, 8},
{0x23, "INC HL", 8, 8},
{0x24, "INC H", 4, 4},
{0x25, "DEC H", 4, 4},
{0x26, "LD H,u8", 8, 8},
{0x27, "DAA", 4, 4},
{0x28, "JR Z,i8", 8, 12},
{0x29, "ADD HL,HL", 8, 8},
{0x2a, "LD A,(HL+)", 8, 8},
{0x2b, "DEC HL", 8, 8},
{0x2c, "INC L", 4, 4},
{0x2d, "DEC L", 4, 4},
{0x2e, "LD L,u8", 8, 8},
{0x2f, "CPL", 4, 4},
{0x30, "JR NC,i8", 8, 12},
{0x31, "LD SP,u16", 12, 12},
{0x32, "LD (HL-),A", 8, 8},
{0x33, "INC SP", 8, 8},
{0x34, "INC (HL)", 12, 12},
{0x35, "DEC (HL)", 12, 12},
{0x36, "LD (HL),u8", 12, 12},
{0x37, "SCF", 4, 4},
{0x38, "JR C,i8", 8, 12},
{0x39, "ADD HL,SP", 8, 8},
{0x3a, "LD A,(HL-)", 8, 8},
{0x3b, "DEC SP", 8, 8},
{0x3c, "INC A", 4, 4},
{0x3d, "DEC A", 4, 4},
{0x3e, "LD A,u8", 8, 8},
{0x3f, "CCF", 4, 4},
{0x40, "LD B,B", 4, 4},
{0x41, "LD B,C", 4, 4},
{0x42, "LD B,D", 4, 4},
{0x43, "LD B,E", 4, 4},
{0x44, "LD B,H", 4, 4},
{0x45, "LD B,L", 4, 4},
{0x46, "LD B,(HL)", 8, 8},
{0x47, "LD B,A", 4, 4},
{0x48, "LD C,B", 4, 4},
{0x49, "LD C,C", 4, 4},
{0x4a, "LD C,D", 4, 4},
{0x4b, "LD C,E", 4, 4},
{0x4c, "LD C,H", 4, 4},
{0x4d, "LD C,L", 4, 4},
{0x4e, "LD C,(HL)", 8, 8},
{0x4f, "LD C,A", 4, 4},
{0x50, "LD D,B", 4, 4},
{0x51, "LD D,C", 4, 4},
{0x52, "LD D,D", 4, 4},
{0x53, "LD D,E", 4, 4},
{0x54, "LD D,H", 4, 4},
{0x55, "LD D,L", 4, 4},
{0x56, "LD D,(HL)", 8, 8},
{0x57, "LD D,A", 4, 4},
{0x58, "LD E,B", 4, 4},
{0x59, "LD E,C", 4, 4},
{0x5a, "LD E,D", 4, 4},
{0x5b, "LD E,E", 4, 4},
{0x5c, "LD E,H", 4, 4},
{0x5d, "LD E,L", 4, 4},
{0x5e, "LD E,(HL)", 8, 8},
{0x5f, "LD E,A", 4, 4},
{0x60, "LD H,B", 4, 4},
{0x61, "LD H,C", 4, 4},
{0x62, "LD H,D", 4, 4},
{0x63, "LD H,E", 4, 4},
{0x64, "LD H,H", 4, 4},
{0x65, "LD H,L", 4, 4},
{0x66, "LD H,(HL)", 8, 8},
{0x67, "LD H,A", 4, 4},
{0x68, "LD L,B", 4, 4},
{0x69, "LD L,C", 4, 4},
{0x6a, "LD L,D", 4, 4},
{0x6b, "LD L,E", 4, 4},
{0x6c, "LD L,H", 4, 4},
{0x6d, "LD L,L", 4, 4},
{0x6e, "LD L,(HL)", 8, 8},
{0x6f, "LD L,A", 4, 4},
{0x70, "LD (HL),B", 8, 8},
{0x71, "LD (HL),C", 8, 8},
{0x72, "LD (HL),D", 8, 8},
{0x73, "LD (HL),E", 8, 8},
{0x74, "LD (HL),H", 8, 8},
{0x75, "LD (HL),L", 8, 8},
{0x76, "HALT", 4, 4},
{0x77, "LD (HL),A", 8, 8},
{0x78, "LD A,B", 4, 4},
{0x79, "LD A,C", 4, 4},
{0x7a, "LD A,D", 4, 4},
{0x7b, "LD A,E", 4, 4},
{0x7c, "LD A,H", 4, 4},
{0x7d, "LD A,L", 4, 4},
{0x7e, "LD A,(HL)", 8, 8},
{0x7f, "LD A,A", 4, 4},
{0x80, "ADD A,B", 4, 4},
{0x81, "ADD A,C", 4, 4},
{0x82, "ADD A,D", 4, 4},
{0x83, "ADD A,E", 4, 4},
{0x84, "ADD A,H", 4, 4},
{0x85, "ADD A,L", 4, 4},
{0x86, "ADD A,(HL)", 8, 8},
{0x87, "ADD A,A", 4, 4},
{0x88, "ADC A,B", 4, 4},
{0x89, "ADC A,C", 4, 4},
{0x8a, "ADC A,D", 4, 4},
{0x8b, "ADC A,E", 4, 4},
{0x8c, "ADC A,H", 4, 4},
{0x8d, "ADC A,L", 4, 4},
{0x8e, "ADC A,(HL)", 8, 8},
{0x8f, "ADC A,A", 4, 4},
{0x90, "SUB A,B", 4, 4},
{0x91, "SUB A,C", 4, 4},
{0x92, "SUB A,D", 4, 4},
{0x93, "SUB A,E", 4, 4},
{0x94, "SUB A,H", 4, 4},
{0x95, "SUB A,L", 4, 4},
{0x96, "SUB A,(HL)", 8, 8},
{0x97, "SUB A,A", 4, 4},
{0x98, "SBC A,B", 4, 4},
{0x99, "SBC A,C", 4, 4},
{0x9a, "SBC A,D", 4, 4},
{0x9b, "SBC A,E", 4, 4},
{0x9c, "SBC A,H", 4, 4},
{0x9d, "SBC A,L", 4, 4},
{0x9e, "SBC A,(HL)", 8, 8},
{0x9f, "SBC A,A", 4, 4},
{0xa0, "AND A,B", 4, 4},
{0xa1, "AND A,C", 4, 4},
{0xa2, "AND A,D", 4, 4},
{0xa3, "AND A,E", 4, 4},
{0xa4, "AND A,H", 4, 4},
{0xa5, "AND A,L", 4, 4},
{0xa6, "AND A,(HL)", 8, 8},
{0xa7, "AND A,A", 4, 4},
{0xa8, "XOR A,B", 4, 4},
{0xa9, "XOR A,C", 4, 4},
{0xaa, "XOR A,D", 4, 4},
{0xab, "XOR A,E", 4, 4},
{0xac, "XOR A,H", 4, 4},
{0xad, "XOR A,L", 4, 4},
{0xae, "XOR A,(HL)", 8, 8},
{0xaf, "XOR A,A", 4, 4},
{0xb0, "OR A,B", 4, 4},
{0xb1, "OR A,C", 4, 4},
{0xb2, "OR A,D", 4, 4},
{0xb3, "OR A,E", 4, 4},
{0xb4, "OR A,H", 4, 4},
{0xb5, "OR A,L", 4, 4},
{0xb6, "OR A,(HL)", 8, 8},
{0xb7, "OR A,A", 4, 4},
{0xb8, "CP A,B", 4, 4},
{0xb9, "CP A,C", 4, 4},
{0xba, "CP A,D", 4, 4},
{0xbb, "CP A,E", 4, 4},
{0xbc, "CP A,H", 4, 4},
{0xbd, "CP A,L", 4, 4},
{0xbe, "CP A,(HL)", 8, 8},
{0xbf, "CP A,A", 4, 4},
{0xc0, "RET NZ", 8, 20},
{0xc1, "POP BC", 12, 12},
{0xc2, "JP NZ,u16", 12, 16},
{0xc3, "JP u16", 16, 16},
{0xc4, "CALL NZ,u16", 12, 24},
{0xc5, "PUSH BC", 16, 16},
{0xc6, "ADD A,u8", 8, 8},
{0xc7, "RST 00h", 16, 16},
{0xc8, "RET Z", 8, 20},
{0xc9, "RET", 16, 16},
{0xca, "JP Z,u16", 12, 16},
{0xcb, "PREFIX CB", 4, 4},
{0xcc, "CALL Z,u16", 12, 24},
{0xcd, "CALL u16", 24, 24},
{0xce, "ADC A,u8", 8, 8},
{0xcf, "RST 08h", 16, 16},
{0xd0, "RET NC", 8, 20},
{0xd1, "POP DE", 12, 12},
{0xd2, "JP NC,u16", 12, 16},
{0xd3, "<invalid>", 0, 0},
{0xd4, "CALL NC,u16", 12, 24},
{0xd5, "PUSH DE", 16, 16},
{0xd6, "SUB A,u8", 8, 8},
{0xd7, "RST 10h", 16, 16},
{0xd8, "RET C", 8, 20},
{0xd9, "RETI", 16, 16},
{0xda, "JP C,u16", 12, 16},
{0xdb, "<invalid>", 0, 0},
{0xdc, "CALL C,u16", 12, 24},
{0xdd, "<invalid>", 0, 0},
{0xde, "SBC A,u8", 8, 8},
{0xdf, "RST 18h", 16, 16},
{0xe0, "LD (FF00+u8),A", 12, 12},
{0xe1, "POP HL", 12, 12},
{0xe2, "LD (FF00+C),A", 8, 8},
{0xe3, "<invalid>", 0, 0},
{0xe4, "<invalid>", 0, 0},
{0xe5, "PUSH HL", 16, 16},
{0xe6, "AND A,u8", 8, 8},
{0xe7, "RST 20h", 16, 16},
{0xe8, "ADD SP,i8", 16, 16},
{0xe9, "JP HL", 4, 4},
{0xea, "LD (u16),A", 16, 16},
{0xeb, "<invalid>", 0, 0},
{0xec, "<invalid>", 0, 0},
{0xed, "<invalid>", 0, 0},
{0xee, "XOR A,u8", 8, 8},
{0xef, "RST 28h", 16, 16},
{0xf0, "LD A,(FF00+u8)", 12, 12},
{0xf1, "POP AF", 12, 12},
{0xf2, "LD A,(FF00+C)", 8, 8},
{0xf3, "DI", 4, 4},
{0xf4, "<invalid>", 0, 0},
{0xf5, "PUSH AF", 16, 16},
{0xf6, "OR A,u8", 8, 8},
{0xf7, "RST 30h", 16, 16},
{0xf8, "LD HL,SP+i8", 12, 12},
{0xf9, "LD SP,HL", 8, 8},
{0xfa, "LD A,(u16)", 16, 16},
{0xfb, "EI", 4, 4},
{0xfc, "<invalid>", 0, 0},
{0xfd, "<invalid>", 0, 0},
{0xfe, "CP A,u8", 8, 8},
{0xff, "RST 38h", 16, 16},
// 0xcb instructions
{0x100, "RLC B", 8, 8},
{0x101, "RLC C", 8, 8},
{0x102, "RLC D", 8, 8},
{0x103, "RLC E", 8, 8},
{0x104, "RLC H", 8, 8},
{0x105, "RLC L", 8, 8},
{0x106, "RLC (HL)", 16, 16},
{0x107, "RLC A", 8, 8},
{0x108, "RRC B", 8, 8},
{0x109, "RRC C", 8, 8},
{0x10a, "RRC D", 8, 8},
{0x10b, "RRC E", 8, 8},
{0x10c, "RRC H", 8, 8},
{0x10d, "RRC L", 8, 8},
{0x10e, "RRC (HL)", 16, 16},
{0x10f, "RRC A", 8, 8},
{0x110, "RL B", 8, 8},
{0x111, "RL C", 8, 8},
{0x112, "RL D", 8, 8},
{0x113, "RL E", 8, 8},
{0x114, "RL H", 8, 8},
{0x115, "RL L", 8, 8},
{0x116, "RL (HL)", 16, 16},
{0x117, "RL A", 8, 8},
{0x118, "RR B", 8, 8},
{0x119, "RR C", 8, 8},
{0x11a, "RR D", 8, 8},
{0x11b, "RR E", 8, 8},
{0x11c, "RR H", 8, 8},
{0x11d, "RR L", 8, 8},
{0x11e, "RR (HL)", 16, 16},
{0x11f, "RR A", 8, 8},
{0x120, "SLA B", 8, 8},
{0x121, "SLA C", 8, 8},
{0x122, "SLA D", 8, 8},
{0x123, "SLA E", 8, 8},
{0x124, "SLA H", 8, 8},
{0x125, "SLA L", 8, 8},
{0x126, "SLA (HL)", 16, 16},
{0x127, "SLA A", 8, 8},
{0x128, "SRA B", 8, 8},
{0x129, "SRA C", 8, 8},
{0x12a, "SRA D", 8, 8},
{0x12b, "SRA E", 8, 8},
{0x12c, "SRA H", 8, 8},
{0x12d, "SRA L", 8, 8},
{0x12e, "SRA (HL)", 16, 16},
{0x12f, "SRA A", 8, 8},
{0x130, "SWAP B", 8, 8},
{0x131, "SWAP C", 8, 8},
{0x132, "SWAP D", 8, 8},
{0x133, "SWAP E", 8, 8},
{0x134, "SWAP H", 8, 8},
{0x135, "SWAP L", 8, 8},
{0x136, "SWAP (HL)", 16, 16},
{0x137, "SWAP A", 8, 8},
{0x138, "SRL B", 8, 8},
{0x139, "SRL C", 8, 8},
{0x13a, "SRL D", 8, 8},
{0x13b, "SRL E", 8, 8},
{0x13c, "SRL H", 8, 8},
{0x13d, "SRL L", 8, 8},
{0x13e, "SRL (HL)", 16, 16},
{0x13f, "SRL A", 8, 8},
{0x140, "BIT 0,B", 8, 8},
{0x141, "BIT 0,C", 8, 8},
{0x142, "BIT 0,D", 8, 8},
{0x143, "BIT 0,E", 8, 8},
{0x144, "BIT 0,H", 8, 8},
{0x145, "BIT 0,L", 8, 8},
{0x146, "BIT 0,(HL)", 12, 12},
{0x147, "BIT 0,A", 8, 8},
{0x148, "BIT 1,B", 8, 8},
{0x149, "BIT 1,C", 8, 8},
{0x14a, "BIT 1,D", 8, 8},
{0x14b, "BIT 1,E", 8, 8},
{0x14c, "BIT 1,H", 8, 8},
{0x14d, "BIT 1,L", 8, 8},
{0x14e, "BIT 1,(HL)", 12, 12},
{0x14f, "BIT 1,A", 8, 8},
{0x150, "BIT 2,B", 8, 8},
{0x151, "BIT 2,C", 8, 8},
{0x152, "BIT 2,D", 8, 8},
{0x153, "BIT 2,E", 8, 8},
{0x154, "BIT 2,H", 8, 8},
{0x155, "BIT 2,L", 8, 8},
{0x156, "BIT 2,(HL)", 12, 12},
{0x157, "BIT 2,A", 8, 8},
{0x158, "BIT 3,B", 8, 8},
{0x159, "BIT 3,C", 8, 8},
{0x15a, "BIT 3,D", 8, 8},
{0x15b, "BIT 3,E", 8, 8},
{0x15c, "BIT 3,H", 8, 8},
{0x15d, "BIT 3,L", 8, 8},
{0x15e, "BIT 3,(HL)", 12, 12},
{0x15f, "BIT 3,A", 8, 8},
{0x160, "BIT 4,B", 8, 8},
{0x161, "BIT 4,C", 8, 8},
{0x162, "BIT 4,D", 8, 8},
{0x163, "BIT 4,E", 8, 8},
{0x164, "BIT 4,H", 8, 8},
{0x165, "BIT 4,L", 8, 8},
{0x166, "BIT 4,(HL)", 12, 12},
{0x167, "BIT 4,A", 8, 8},
{0x168, "BIT 5,B", 8, 8},
{0x169, "BIT 5,C", 8, 8},
{0x16a, "BIT 5,D", 8, 8},
{0x16b, "BIT 5,E", 8, 8},
{0x16c, "BIT 5,H", 8, 8},
{0x16d, "BIT 5,L", 8, 8},
{0x16e, "BIT 5,(HL)", 12, 12},
{0x16f, "BIT 5,A", 8, 8},
{0x170, "BIT 6,B", 8, 8},
{0x171, "BIT 6,C", 8, 8},
{0x172, "BIT 6,D", 8, 8},
{0x173, "BIT 6,E", 8, 8},
{0x174, "BIT 6,H", 8, 8},
{0x175, "BIT 6,L", 8, 8},
{0x176, "BIT 6,(HL)", 12, 12},
{0x177, "BIT 6,A", 8, 8},
{0x178, "BIT 7,B", 8, 8},
{0x179, "BIT 7,C", 8, 8},
{0x17a, "BIT 7,D", 8, 8},
{0x17b, "BIT 7,E", 8, 8},
{0x17c, "BIT 7,H", 8, 8},
{0x17d, "BIT 7,L", 8, 8},
{0x17e, "BIT 7,(HL)", 12, 12},
{0x17f, "BIT 7,A", 8, 8},
{0x180, "RES 0,B", 8, 8},
{0x181, "RES 0,C", 8, 8},
{0x182, "RES 0,D", 8, 8},
{0x183, "RES 0,E", 8, 8},
{0x184, "RES 0,H", 8, 8},
{0x185, "RES 0,L", 8, 8},
{0x186, "RES 0,(HL)", 16, 16},
{0x187, "RES 0,A", 8, 8},
{0x188, "RES 1,B", 8, 8},
{0x189, "RES 1,C", 8, 8},
{0x18a, "RES 1,D", 8, 8},
{0x18b, "RES 1,E", 8, 8},
{0x18c, "RES 1,H", 8, 8},
{0x18d, "RES 1,L", 8, 8},
{0x18e, "RES 1,(HL)", 16, 16},
{0x18f, "RES 1,A", 8, 8},
{0x190, "RES 2,B", 8, 8},
{0x191, "RES 2,C", 8, 8},
{0x192, "RES 2,D", 8, 8},
{0x193, "RES 2,E", 8, 8},
{0x194, "RES 2,H", 8, 8},
{0x195, "RES 2,L", 8, 8},
{0x196, "RES 2,(HL)", 16, 16},
{0x197, "RES 2,A", 8, 8},
{0x198, "RES 3,B", 8, 8},
{0x199, "RES 3,C", 8, 8},
{0x19a, "RES 3,D", 8, 8},
{0x19b, "RES 3,E", 8, 8},
{0x19c, "RES 3,H", 8, 8},
{0x19d, "RES 3,L", 8, 8},
{0x19e, "RES 3,(HL)", 16, 16},
{0x19f, "RES 3,A", 8, 8},
{0x1a0, "RES 4,B", 8, 8},
{0x1a1, "RES 4,C", 8, 8},
{0x1a2, "RES 4,D", 8, 8},
{0x1a3, "RES 4,E", 8, 8},
{0x1a4, "RES 4,H", 8, 8},
{0x1a5, "RES 4,L", 8, 8},
{0x1a6, "RES 4,(HL)", 16, 16},
{0x1a7, "RES 4,A", 8, 8},
{0x1a8, "RES 5,B", 8, 8},
{0x1a9, "RES 5,C", 8, 8},
{0x1aa, "RES 5,D", 8, 8},
{0x1ab, "RES 5,E", 8, 8},
{0x1ac, "RES 5,H", 8, 8},
{0x1ad, "RES 5,L", 8, 8},
{0x1ae, "RES 5,(HL)", 16, 16},
{0x1af, "RES 5,A", 8, 8},
{0x1b0, "RES 6,B", 8, 8},
{0x1b1, "RES 6,C", 8, 8},
{0x1b2, "RES 6,D", 8, 8},
{0x1b3, "RES 6,E", 8, 8},
{0x1b4, "RES 6,H", 8, 8},
{0x1b5, "RES 6,L", 8, 8},
{0x1b6, "RES 6,(HL)", 16, 16},
{0x1b7, "RES 6,A", 8, 8},
{0x1b8, "RES 7,B", 8, 8},
{0x1b9, "RES 7,C", 8, 8},
{0x1ba, "RES 7,D", 8, 8},
{0x1bb, "RES 7,E", 8, 8},
{0x1bc, "RES 7,H", 8, 8},
{0x1bd, "RES 7,L", 8, 8},
{0x1be, "RES 7,(HL)", 16, 16},
{0x1bf, "RES 7,A", 8, 8},
{0x1c0, "SET 0,B", 8, 8},
{0x1c1, "SET 0,C", 8, 8},
{0x1c2, "SET 0,D", 8, 8},
{0x1c3, "SET 0,E", 8, 8},
{0x1c4, "SET 0,H", 8, 8},
{0x1c5, "SET 0,L", 8, 8},
{0x1c6, "SET 0,(HL)", 16, 16},
{0x1c7, "SET 0,A", 8, 8},
{0x1c8, "SET 1,B", 8, 8},
{0x1c9, "SET 1,C", 8, 8},
{0x1ca, "SET 1,D", 8, 8},
{0x1cb, "SET 1,E", 8, 8},
{0x1cc, "SET 1,H", 8, 8},
{0x1cd, "SET 1,L", 8, 8},
{0x1ce, "SET 1,(HL)", 16, 16},
{0x1cf, "SET 1,A", 8, 8},
{0x1d0, "SET 2,B", 8, 8},
{0x1d1, "SET 2,C", 8, 8},
{0x1d2, "SET 2,D", 8, 8},
{0x1d3, "SET 2,E", 8, 8},
{0x1d4, "SET 2,H", 8, 8},
{0x1d5, "SET 2,L", 8, 8},
{0x1d6, "SET 2,(HL)", 16, 16},
{0x1d7, "SET 2,A", 8, 8},
{0x1d8, "SET 3,B", 8, 8},
{0x1d9, "SET 3,C", 8, 8},
{0x1da, "SET 3,D", 8, 8},
{0x1db, "SET 3,E", 8, 8},
{0x1dc, "SET 3,H", 8, 8},
{0x1dd, "SET 3,L", 8, 8},
{0x1de, "SET 3,(HL)", 16, 16},
{0x1df, "SET 3,A", 8, 8},
{0x1e0, "SET 4,B", 8, 8},
{0x1e1, "SET 4,C", 8, 8},
{0x1e2, "SET 4,D", 8, 8},
{0x1e3, "SET 4,E", 8, 8},
{0x1e4, "SET 4,H", 8, 8},
{0x1e5, "SET 4,L", 8, 8},
{0x1e6, "SET 4,(HL)", 16, 16},
{0x1e7, "SET 4,A", 8, 8},
{0x1e8, "SET 5,B", 8, 8},
{0x1e9, "SET 5,C", 8, 8},
{0x1ea, "SET 5,D", 8, 8},
{0x1eb, "SET 5,E", 8, 8},
{0x1ec, "SET 5,H", 8, 8},
{0x1ed, "SET 5,L", 8, 8},
{0x1ee, "SET 5,(HL)", 16, 16},
{0x1ef, "SET 5,A", 8, 8},
{0x1f0, "SET 6,B", 8, 8},
{0x1f1, "SET 6,C", 8, 8},
{0x1f2, "SET 6,D", 8, 8},
{0x1f3, "SET 6,E", 8, 8},
{0x1f4, "SET 6,H", 8, 8},
{0x1f5, "SET 6,L", 8, 8},
{0x1f6, "SET 6,(HL)", 16, 16},
{0x1f7, "SET 6,A", 8, 8},
{0x1f8, "SET 7,B", 8, 8},
{0x1f9, "SET 7,C", 8, 8},
{0x1fa, "SET 7,D", 8, 8},
{0x1fb, "SET 7,E", 8, 8},
{0x1fc, "SET 7,H", 8, 8},
{0x1fd, "SET 7,L", 8, 8},
{0x1fe, "SET 7,(HL)", 16, 16},
{0x1ff, "SET 7,A", 8, 8},
};

2
src/instructions.h
View File

@ -4,6 +4,8 @@
struct instruction {
int opcode;
const char *format;
int cycles;
int cycles_branch;
};
extern const struct instruction instructions[];

2
src/types.h
View File

@ -3,5 +3,7 @@
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned long u32;
typedef unsigned long long u64;
#endif