1999-10-03 14:16:26 +00:00
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*
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* asm_support.asm - AmigaOS utility functions in assembly language
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*
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* Basilisk II (C) 1997-1999 Christian Bauer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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INCLUDE "exec/types.i"
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INCLUDE "exec/macros.i"
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INCLUDE "exec/memory.i"
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INCLUDE "exec/tasks.i"
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INCLUDE "dos/dos.i"
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INCLUDE "devices/timer.i"
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XDEF _AtomicAnd
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XDEF _AtomicOr
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XDEF _MoveVBR
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XDEF _Execute68k
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XDEF _Execute68kTrap
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XDEF _TrapHandlerAsm
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XDEF _ExceptionHandlerAsm
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XDEF _Scod060Patch1
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XDEF _Scod060Patch2
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XDEF _ThInitFPUPatch
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2000-08-20 14:08:44 +00:00
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XDEF _AsmTriggerNMI
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1999-10-03 14:16:26 +00:00
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XREF _OldTrapHandler
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XREF _OldExceptionHandler
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XREF _IllInstrHandler
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XREF _PrivViolHandler
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XREF _EmulatedSR
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XREF _IRQSigMask
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XREF _InterruptFlags
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XREF _MainTask
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XREF _SysBase
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1999-10-19 19:28:28 +00:00
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XREF _quit_emulator
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2000-08-20 14:08:44 +00:00
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XREF _kprintf
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1999-10-03 14:16:26 +00:00
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SECTION text,CODE
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*
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* Atomic bit operations (don't trust the compiler)
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*
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_AtomicAnd move.l 4(sp),a0
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move.l 8(sp),d0
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and.l d0,(a0)
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rts
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_AtomicOr move.l 4(sp),a0
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move.l 8(sp),d0
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or.l d0,(a0)
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rts
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*
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* Move VBR away from 0 if neccessary
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*
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_MoveVBR movem.l d0-d1/a0-a1/a5-a6,-(sp)
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move.l _SysBase,a6
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lea getvbr,a5 ;VBR at 0?
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JSRLIB Supervisor
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tst.l d0
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bne.s 1$
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move.l #$400,d0 ;Yes, allocate memory for new table
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move.l #MEMF_PUBLIC,d1
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JSRLIB AllocMem
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tst.l d0
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beq.s 1$
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JSRLIB Disable
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move.l d0,a5 ;Copy old table
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move.l d0,a1
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sub.l a0,a0
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move.l #$400,d0
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JSRLIB CopyMem
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JSRLIB CacheClearU
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move.l a5,d0 ;Set VBR
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lea setvbr,a5
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JSRLIB Supervisor
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JSRLIB Enable
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1$ movem.l (sp)+,d0-d1/a0-a1/a5-a6
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rts
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getvbr movec vbr,d0
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rte
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setvbr movec d0,vbr
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rte
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*
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* Execute 68k subroutine (must be ended with rts)
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* r->a[7] and r->sr are unused!
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*
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; void Execute68k(uint32 addr, M68kRegisters *r);
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_Execute68k
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move.l 4(sp),d0 ;Get arguments
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move.l 8(sp),a0
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movem.l d2-d7/a2-a6,-(sp) ;Save registers
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move.l a0,-(sp) ;Push pointer to M68kRegisters on stack
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pea 1$ ;Push return address on stack
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move.l d0,-(sp) ;Push pointer to 68k routine on stack
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movem.l (a0),d0-d7/a0-a6 ;Load registers from M68kRegisters
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rts ;Jump into 68k routine
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1$ move.l a6,-(sp) ;Save a6
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move.l 4(sp),a6 ;Get pointer to M68kRegisters
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movem.l d0-d7/a0-a5,(a6) ;Save d0-d7/a0-a5 to M68kRegisters
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move.l (sp)+,56(a6) ;Save a6 to M68kRegisters
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addq.l #4,sp ;Remove pointer from stack
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movem.l (sp)+,d2-d7/a2-a6 ;Restore registers
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rts
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*
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* Execute MacOS 68k trap
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* r->a[7] and r->sr are unused!
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*
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; void Execute68kTrap(uint16 trap, M68kRegisters *r);
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_Execute68kTrap
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move.l 4(sp),d0 ;Get arguments
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move.l 8(sp),a0
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movem.l d2-d7/a2-a6,-(sp) ;Save registers
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move.l a0,-(sp) ;Push pointer to M68kRegisters on stack
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move.w d0,-(sp) ;Push trap word on stack
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subq.l #8,sp ;Create fake A-Line exception frame
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movem.l (a0),d0-d7/a0-a6 ;Load registers from M68kRegisters
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move.l a2,-(sp) ;Save a2 and d2
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move.l d2,-(sp)
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lea 1$,a2 ;a2 points to return address
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move.w 16(sp),d2 ;Load trap word into d2
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jmp ([$28.w],10) ;Jump into MacOS A-Line handler
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1$ move.l a6,-(sp) ;Save a6
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move.l 6(sp),a6 ;Get pointer to M68kRegisters
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movem.l d0-d7/a0-a5,(a6) ;Save d0-d7/a0-a5 to M68kRegisters
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move.l (sp)+,56(a6) ;Save a6 to M68kRegisters
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addq.l #6,sp ;Remove pointer and trap word from stack
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movem.l (sp)+,d2-d7/a2-a6 ;Restore registers
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rts
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*
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* Exception handler of main task (for 60Hz interrupts)
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*
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_ExceptionHandlerAsm
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move.l d0,-(sp) ;Save d0
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and.l #SIGBREAKF_CTRL_C,d0 ;CTRL-C?
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bne.s 2$
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move.w _EmulatedSR,d0 ;Interrupts enabled in emulated SR?
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and.w #$0700,d0
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bne 1$
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move.w #$0064,-(sp) ;Yes, fake interrupt stack frame
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pea 1$
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move.w _EmulatedSR,d0
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move.w d0,-(sp)
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2000-08-20 14:08:44 +00:00
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or.w #$0100,d0 ;Set interrupt level in SR
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1999-10-03 14:16:26 +00:00
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move.w d0,_EmulatedSR
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2000-08-20 14:08:44 +00:00
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move.l $64.w,-(sp) ;Jump to MacOS interrupt handler
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rts
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1999-10-03 14:16:26 +00:00
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1$ move.l (sp)+,d0 ;Restore d0
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rts
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2$ JSRLIB Forbid ;Waiting for Dos signal?
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sub.l a1,a1
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JSRLIB FindTask
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move.l d0,a0
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move.l TC_SIGWAIT(a0),d0
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move.l TC_SIGRECVD(a0),d1
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JSRLIB Permit
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btst #SIGB_DOS,d0
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beq 3$
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btst #SIGB_DOS,d1
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bne 4$
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3$ lea TC_SIZE(a0),a0 ;No, remove pending Dos packets
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JSRLIB GetMsg
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move.w _EmulatedSR,d0
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or.w #$0700,d0 ;Disable all interrupts
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move.w d0,_EmulatedSR
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moveq #0,d0 ;Disable all exception signals
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moveq #-1,d1
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JSRLIB SetExcept
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1999-10-19 19:28:28 +00:00
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jsr _quit_emulator ;CTRL-C, quit emulator
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1999-10-03 14:16:26 +00:00
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4$ move.l (sp)+,d0
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rts
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*
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* Process Manager 68060 FPU patches
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*
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_Scod060Patch1 fsave -(sp) ;Save FPU state
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tst.b 2(sp) ;Null?
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beq.s 1$
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fmovem.x fp0-fp7,-(sp) ;No, save FPU registers
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fmove.l fpiar,-(sp)
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fmove.l fpsr,-(sp)
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fmove.l fpcr,-(sp)
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pea -1 ;Push "FPU state saved" flag
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1$ move.l d1,-(sp)
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move.l d0,-(sp)
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bsr.s 3$ ;Switch integer registers and stack
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addq.l #8,sp
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tst.b 2(sp) ;New FPU state null or "FPU state saved" flag set?
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beq.s 2$
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addq.l #4,sp ;Flag set, skip it
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fmove.l (sp)+,fpcr ;Restore FPU registers and state
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fmove.l (sp)+,fpsr
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fmove.l (sp)+,fpiar
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fmovem.x (sp)+,fp0-fp7
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2$ frestore (sp)+
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movem.l (sp)+,d0-d1
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rts
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3$ move.l 4(sp),a0 ;Switch integer registers and stack
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move sr,-(sp)
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movem.l d2-d7/a2-a6,-(sp)
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cmp.w #0,a0
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beq.s 4$
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move.l sp,(a0)
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4$ move.l $36(sp),a0
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movem.l (a0)+,d2-d7/a2-a6
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move (a0)+,sr
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move.l a0,sp
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rts
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_Scod060Patch2 move.l d0,-(sp) ;Create 68060 null frame on stack
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move.l d0,-(sp)
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move.l d0,-(sp)
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frestore (sp)+ ;and load it
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rts
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*
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* Thread Manager 68060 FPU patches
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*
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_ThInitFPUPatch tst.b $40(a4)
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bne.s 1$
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moveq #0,d0 ;Create 68060 null frame on stack
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move.l d0,-(a3)
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move.l d0,-(a3)
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move.l d0,-(a3)
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1$ rts
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*
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* Trap handler of main task
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*
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2000-08-20 14:08:44 +00:00
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_TrapHandlerAsm:
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cmp.l #4,(sp) ;Illegal instruction?
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1999-10-03 14:16:26 +00:00
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beq.s doillinstr
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cmp.l #10,(sp) ;A-Line exception?
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beq.s doaline
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cmp.l #8,(sp) ;Privilege violation?
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beq.s doprivviol
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2000-08-20 14:08:44 +00:00
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cmp.l #9,(sp) ;Trace?
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beq dotrace
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cmp.l #3,(sp) ;Illegal Address?
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beq.s doilladdr
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cmp.l #32,(sp)
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blt 1$
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cmp.l #47,(sp)
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ble doTrapXX ; Vector 32-47 : TRAP #0 - 15 Instruction Vectors
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1$: move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler
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rts
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*
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* TRAP #0 - 15 Instruction Vectors
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*
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doTrapXX: move.l a0,(sp) ;Save a0
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move.l usp,a0 ;Get user stack pointer
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move.l 2*4(sp),-(a0) ;Copy 4-word stack frame to user stack
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move.l 1*4(sp),-(a0)
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move.l a0,usp ;Update USP
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move.l (sp)+,a0 ;Restore a0
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addq.l #4*2,sp ;Remove exception frame from supervisor stack
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andi #$d8ff,sr ;Switch to user mode, enable interrupts
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1999-10-03 14:16:26 +00:00
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2000-08-20 14:08:44 +00:00
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move.l $2d*4.w,-(sp) ;Jump to MacOS exception handler
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1999-10-03 14:16:26 +00:00
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rts
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2000-08-20 14:08:44 +00:00
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*
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* trace Vector
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*
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dotrace: move.l a0,(sp) ;Save a0
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move.l usp,a0 ;Get user stack pointer
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move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack
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move.l 2*4(sp),-(a0)
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move.l 1*4(sp),-(a0)
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move.l a0,usp ;Update USP
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move.l (sp)+,a0 ;Restore a0
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lea 6*2(sp),sp ;Remove exception frame from supervisor stack
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andi #$18ff,sr ;Switch to user mode, enable interrupts, disable trace
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move.l $24.w,-(sp) ;Jump to MacOS exception handler
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rts
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1999-10-03 14:16:26 +00:00
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*
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* A-Line handler: call MacOS A-Line handler
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*
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doaline move.l a0,(sp) ;Save a0
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move.l usp,a0 ;Get user stack pointer
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move.l 8(sp),-(a0) ;Copy stack frame to user stack
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move.l 4(sp),-(a0)
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move.l a0,usp ;Update USP
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move.l (sp)+,a0 ;Restore a0
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addq.l #8,sp ;Remove exception frame from supervisor stack
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andi #$d8ff,sr ;Switch to user mode, enable interrupts
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2000-08-20 14:08:44 +00:00
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IFNE 0
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; move.w ([2,sp]),($3800)
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|
|
cmp.w #$a9c3,([2,sp])
|
|
|
|
bne 1$
|
|
|
|
|
|
|
|
move.l d0,-(sp)
|
|
|
|
move.l a0,-(sp)
|
|
|
|
pea afmt(pc)
|
|
|
|
jsr _kprintf
|
|
|
|
lea 3*4(sp),sp
|
|
|
|
1$:
|
|
|
|
ENDC
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
move.l $28.w,-(sp) ;Jump to MacOS exception handler
|
|
|
|
rts
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
afmt: dc.b 'a0=%08lx d0=%08lx\n',0
|
|
|
|
cnop 0,4
|
|
|
|
|
|
|
|
*
|
|
|
|
* Illegal address handler
|
|
|
|
*
|
|
|
|
|
|
|
|
doilladdr: move.l a0,(sp) ;Save a0
|
|
|
|
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack
|
|
|
|
move.l 2*4(sp),-(a0)
|
|
|
|
move.l 1*4(sp),-(a0)
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
|
|
|
|
lea 6*2(sp),sp ;Remove exception frame from supervisor stack
|
|
|
|
andi #$d8ff,sr ;Switch to user mode, enable interrupts
|
|
|
|
|
|
|
|
move.l $0c.w,-(sp) ;Jump to MacOS exception handler
|
|
|
|
rts
|
|
|
|
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
*
|
|
|
|
* Illegal instruction handler: call IllInstrHandler() (which calls EmulOp())
|
|
|
|
* to execute extended opcodes (see emul_op.h)
|
|
|
|
*
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
doillinstr
|
|
|
|
movem.l a0/d0,-(sp)
|
|
|
|
move.w ([6+2*4,sp]),d0
|
|
|
|
and.w #$ff00,d0
|
|
|
|
cmp.w #$7100,d0
|
|
|
|
movem.l (sp)+,a0/d0
|
|
|
|
beq 1$
|
|
|
|
|
|
|
|
move.l a0,(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.l 8(sp),-(a0) ;Copy stack frame to user stack
|
|
|
|
move.l 4(sp),-(a0)
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
|
|
|
|
add.w #3*4,sp ;Remove exception frame from supervisor stack
|
|
|
|
andi #$d8ff,sr ;Switch to user mode, enable interrupts
|
|
|
|
|
|
|
|
move.l $10.w,-(sp) ;Jump to MacOS exception handler
|
|
|
|
rts
|
|
|
|
|
|
|
|
1$:
|
|
|
|
move.l a6,(sp) ;Save a6
|
1999-10-03 14:16:26 +00:00
|
|
|
move.l usp,a6 ;Get user stack pointer
|
|
|
|
|
|
|
|
move.l a6,-10(a6) ;Push USP (a7)
|
|
|
|
move.l 6(sp),-(a6) ;Push PC
|
|
|
|
move.w 4(sp),-(a6) ;Push SR
|
|
|
|
subq.l #4,a6 ;Skip saved USP
|
|
|
|
move.l (sp),-(a6) ;Push old a6
|
|
|
|
movem.l d0-d7/a0-a5,-(a6) ;Push remaining registers
|
|
|
|
move.l a6,usp ;Update USP
|
|
|
|
|
|
|
|
add.w #12,sp ;Remove exception frame from supervisor stack
|
|
|
|
andi #$d8ff,sr ;Switch to user mode, enable interrupts
|
|
|
|
|
|
|
|
move.l a6,-(sp) ;Jump to IllInstrHandler() in main.cpp
|
|
|
|
jsr _IllInstrHandler
|
|
|
|
addq.l #4,sp
|
|
|
|
|
|
|
|
movem.l (sp)+,d0-d7/a0-a6 ;Restore registers
|
|
|
|
addq.l #4,sp ;Skip saved USP (!!)
|
|
|
|
rtr ;Return from exception
|
|
|
|
|
|
|
|
*
|
|
|
|
* Privilege violation handler: MacOS runs in supervisor mode,
|
|
|
|
* so we have to emulate certain privileged instructions
|
|
|
|
*
|
|
|
|
|
|
|
|
doprivviol move.l d0,(sp) ;Save d0
|
|
|
|
move.w ([6,sp]),d0 ;Get instruction word
|
|
|
|
|
|
|
|
cmp.w #$40e7,d0 ;move sr,-(sp)?
|
|
|
|
beq pushsr
|
|
|
|
cmp.w #$46df,d0 ;move (sp)+,sr?
|
|
|
|
beq popsr
|
|
|
|
|
|
|
|
cmp.w #$007c,d0 ;ori #xxxx,sr?
|
|
|
|
beq orisr
|
|
|
|
cmp.w #$027c,d0 ;andi #xxxx,sr?
|
|
|
|
beq andisr
|
|
|
|
|
|
|
|
cmp.w #$46fc,d0 ;move #xxxx,sr?
|
|
|
|
beq movetosrimm
|
|
|
|
|
|
|
|
cmp.w #$46ef,d0 ;move (xxxx,sp),sr?
|
|
|
|
beq movetosrsprel
|
|
|
|
cmp.w #$46d8,d0 ;move (a0)+,sr?
|
|
|
|
beq movetosra0p
|
|
|
|
cmp.w #$46d9,d0 ;move (a1)+,sr?
|
|
|
|
beq movetosra1p
|
|
|
|
|
|
|
|
cmp.w #$40f8,d0 ;move sr,xxxx.w?
|
|
|
|
beq movefromsrabs
|
|
|
|
cmp.w #$40d0,d0 ;move sr,(a0)?
|
|
|
|
beq movefromsra0
|
|
|
|
cmp.w #$40d7,d0 ;move sr,(sp)?
|
2000-08-20 14:08:44 +00:00
|
|
|
beq movefromsrsp ;+++jl+++
|
1999-10-03 14:16:26 +00:00
|
|
|
|
|
|
|
cmp.w #$f327,d0 ;fsave -(sp)?
|
|
|
|
beq fsavepush
|
|
|
|
cmp.w #$f35f,d0 ;frestore (sp)+?
|
|
|
|
beq frestorepop
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$f32d,d0 ;fsave xxx(a5) ?
|
|
|
|
beq fsavea5
|
|
|
|
cmp.w #$f36d,d0 ;frestore xxx(a5) ?
|
|
|
|
beq frestorea5
|
1999-10-03 14:16:26 +00:00
|
|
|
|
|
|
|
cmp.w #$4e73,d0 ;rte?
|
|
|
|
beq pvrte
|
|
|
|
|
|
|
|
cmp.w #$40c0,d0 ;move sr,d0?
|
|
|
|
beq movefromsrd0
|
|
|
|
cmp.w #$40c1,d0 ;move sr,d1?
|
|
|
|
beq movefromsrd1
|
|
|
|
cmp.w #$40c2,d0 ;move sr,d2?
|
|
|
|
beq movefromsrd2
|
|
|
|
cmp.w #$40c3,d0 ;move sr,d3?
|
|
|
|
beq movefromsrd3
|
|
|
|
cmp.w #$40c4,d0 ;move sr,d4?
|
|
|
|
beq movefromsrd4
|
|
|
|
cmp.w #$40c5,d0 ;move sr,d5?
|
|
|
|
beq movefromsrd5
|
|
|
|
cmp.w #$40c6,d0 ;move sr,d6?
|
|
|
|
beq movefromsrd6
|
|
|
|
cmp.w #$40c7,d0 ;move sr,d7?
|
|
|
|
beq movefromsrd7
|
|
|
|
|
|
|
|
cmp.w #$46c0,d0 ;move d0,sr?
|
|
|
|
beq movetosrd0
|
|
|
|
cmp.w #$46c1,d0 ;move d1,sr?
|
|
|
|
beq movetosrd1
|
|
|
|
cmp.w #$46c2,d0 ;move d2,sr?
|
|
|
|
beq movetosrd2
|
|
|
|
cmp.w #$46c3,d0 ;move d3,sr?
|
|
|
|
beq movetosrd3
|
|
|
|
cmp.w #$46c4,d0 ;move d4,sr?
|
|
|
|
beq movetosrd4
|
|
|
|
cmp.w #$46c5,d0 ;move d5,sr?
|
|
|
|
beq movetosrd5
|
|
|
|
cmp.w #$46c6,d0 ;move d6,sr?
|
|
|
|
beq movetosrd6
|
|
|
|
cmp.w #$46c7,d0 ;move d7,sr?
|
|
|
|
beq movetosrd7
|
|
|
|
|
|
|
|
cmp.w #$4e7a,d0 ;movec cr,x?
|
|
|
|
beq movecfromcr
|
|
|
|
cmp.w #$4e7b,d0 ;movec x,cr?
|
|
|
|
beq movectocr
|
|
|
|
|
|
|
|
cmp.w #$f478,d0 ;cpusha dc?
|
|
|
|
beq cpushadc
|
|
|
|
cmp.w #$f4f8,d0 ;cpusha dc/ic?
|
|
|
|
beq cpushadcic
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$4e69,d0 ;move usp,a1
|
|
|
|
beq moveuspa1
|
|
|
|
cmp.w #$4e68,d0 ;move usp,a0
|
|
|
|
beq moveuspa0
|
|
|
|
|
|
|
|
cmp.w #$4e61,d0 ;move a1,usp
|
|
|
|
beq moved1usp
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
pv_unhandled move.l (sp),d0 ;Unhandled instruction, jump to handler in main.cpp
|
|
|
|
move.l a6,(sp) ;Save a6
|
|
|
|
move.l usp,a6 ;Get user stack pointer
|
|
|
|
|
|
|
|
move.l a6,-10(a6) ;Push USP (a7)
|
|
|
|
move.l 6(sp),-(a6) ;Push PC
|
|
|
|
move.w 4(sp),-(a6) ;Push SR
|
|
|
|
subq.l #4,a6 ;Skip saved USP
|
|
|
|
move.l (sp),-(a6) ;Push old a6
|
|
|
|
movem.l d0-d7/a0-a5,-(a6) ;Push remaining registers
|
|
|
|
move.l a6,usp ;Update USP
|
|
|
|
|
|
|
|
add.w #12,sp ;Remove exception frame from supervisor stack
|
|
|
|
andi #$d8ff,sr ;Switch to user mode, enable interrupts
|
|
|
|
|
|
|
|
move.l a6,-(sp) ;Jump to PrivViolHandler() in main.cpp
|
|
|
|
jsr _PrivViolHandler
|
|
|
|
addq.l #4,sp
|
|
|
|
|
|
|
|
movem.l (sp)+,d0-d7/a0-a6 ;Restore registers
|
|
|
|
addq.l #4,sp ;Skip saved USP
|
|
|
|
rtr ;Return from exception
|
|
|
|
|
|
|
|
; move sr,-(sp)
|
|
|
|
pushsr move.l a0,-(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.w 8(sp),d0 ;Get CCR from exception stack frame
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
move.w d0,-(a0) ;Store SR on user stack
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; move (sp)+,sr
|
|
|
|
popsr move.l a0,-(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.w (a0)+,d0 ;Get SR from user stack
|
|
|
|
move.w d0,8(sp) ;Store into CCR on exception stack frame
|
|
|
|
and.w #$00ff,8(sp)
|
2000-08-20 14:08:44 +00:00
|
|
|
and.w #$e700,d0 ;Extract supervisor bits
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w d0,_EmulatedSR ;And save them
|
|
|
|
|
|
|
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled
|
|
|
|
bne 1$
|
|
|
|
tst.l _InterruptFlags
|
|
|
|
beq 1$
|
|
|
|
movem.l d0-d1/a0-a1/a6,-(sp)
|
|
|
|
move.l _SysBase,a6
|
|
|
|
move.l _MainTask,a1
|
|
|
|
move.l _IRQSigMask,d0
|
|
|
|
JSRLIB Signal
|
|
|
|
movem.l (sp)+,d0-d1/a0-a1/a6
|
|
|
|
1$
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; ori #xxxx,sr
|
|
|
|
orisr move.w 4(sp),d0 ;Get CCR from stack
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
or.w ([6,sp],2),d0 ;Or with immediate value
|
|
|
|
move.w d0,4(sp) ;Store into CCR on stack
|
|
|
|
and.w #$00ff,4(sp)
|
2000-08-20 14:08:44 +00:00
|
|
|
and.w #$e700,d0 ;Extract supervisor bits
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w d0,_EmulatedSR ;And save them
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #4,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; andi #xxxx,sr
|
|
|
|
andisr move.w 4(sp),d0 ;Get CCR from stack
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
and.w ([6,sp],2),d0 ;And with immediate value
|
|
|
|
storesr4 move.w d0,4(sp) ;Store into CCR on stack
|
|
|
|
and.w #$00ff,4(sp)
|
2000-08-20 14:08:44 +00:00
|
|
|
and.w #$e700,d0 ;Extract supervisor bits
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w d0,_EmulatedSR ;And save them
|
|
|
|
|
|
|
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled
|
|
|
|
bne.s 1$
|
|
|
|
tst.l _InterruptFlags
|
|
|
|
beq.s 1$
|
|
|
|
movem.l d0-d1/a0-a1/a6,-(sp)
|
|
|
|
move.l _SysBase,a6
|
|
|
|
move.l _MainTask,a1
|
|
|
|
move.l _IRQSigMask,d0
|
|
|
|
JSRLIB Signal
|
|
|
|
movem.l (sp)+,d0-d1/a0-a1/a6
|
|
|
|
1$ move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #4,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; move #xxxx,sr
|
|
|
|
movetosrimm move.w ([6,sp],2),d0 ;Get immediate value
|
|
|
|
bra.s storesr4
|
|
|
|
|
|
|
|
; move (xxxx,sp),sr
|
|
|
|
movetosrsprel move.l a0,-(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.w ([10,sp],2),d0 ;Get offset
|
|
|
|
move.w (a0,d0.w),d0 ;Read word
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
bra.s storesr4
|
|
|
|
|
|
|
|
; move (a0)+,sr
|
|
|
|
movetosra0p move.w (a0)+,d0 ;Read word
|
|
|
|
bra storesr2
|
|
|
|
|
|
|
|
; move (a1)+,sr
|
|
|
|
movetosra1p move.w (a1)+,d0 ;Read word
|
|
|
|
bra storesr2
|
|
|
|
|
|
|
|
; move sr,xxxx.w
|
|
|
|
movefromsrabs move.l a0,-(sp) ;Save a0
|
|
|
|
move.w ([10,sp],2),a0 ;Get address
|
|
|
|
move.w 8(sp),d0 ;Get CCR
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
move.w d0,(a0) ;Store SR
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #4,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; move sr,(a0)
|
|
|
|
movefromsra0 move.w 4(sp),d0 ;Get CCR
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
move.w d0,(a0) ;Store SR
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; move sr,(sp)
|
|
|
|
movefromsrsp move.l a0,-(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
move.w 8(sp),d0 ;Get CCR
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
move.w d0,(a0) ;Store SR
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; fsave -(sp)
|
|
|
|
fsavepush move.l (sp),d0 ;Restore d0
|
|
|
|
move.l a0,(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
fsave -(a0) ;Push FP state
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; frestore (sp)+
|
|
|
|
frestorepop move.l (sp),d0 ;Restore d0
|
|
|
|
move.l a0,(sp) ;Save a0
|
|
|
|
move.l usp,a0 ;Get user stack pointer
|
|
|
|
frestore (a0)+ ;Restore FP state
|
|
|
|
move.l a0,usp ;Update USP
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
; frestore xxx(a5) +jl+
|
|
|
|
frestorea5 move.l (sp),d0 ;Restore d0
|
|
|
|
move.l a0,(sp) ;Save a0
|
|
|
|
move.l a5,a0 ;Get base register
|
|
|
|
add.w ([6,sp],2),a0 ;Add offset to base register
|
|
|
|
frestore (a0) ;Restore FP state from (a0)
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
addq.l #4,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; fsave xxx(a5) +jl+
|
|
|
|
fsavea5: move.l (sp),d0 ;Restore d0
|
|
|
|
move.l a0,(sp) ;Save a0
|
|
|
|
move.l a5,a0 ;Get base register
|
|
|
|
add.w ([6,sp],2),a0 ;Add offset to base register
|
|
|
|
fsave (a0) ;Push FP state to (a0)
|
|
|
|
move.l (sp)+,a0 ;Restore a0
|
|
|
|
addq.l #4,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
; rte
|
|
|
|
pvrte movem.l a0/a1,-(sp) ;Save a0 and a1
|
1999-10-03 14:16:26 +00:00
|
|
|
move.l usp,a0 ;Get user stack pointer
|
2000-08-20 14:08:44 +00:00
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w (a0)+,d0 ;Get SR from user stack
|
2000-08-20 14:08:44 +00:00
|
|
|
move.w d0,8+4(sp) ;Store into CCR on exception stack frame
|
|
|
|
and.w #$c0ff,8+4(sp)
|
|
|
|
and.w #$e700,d0 ;Extract supervisor bits
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w d0,_EmulatedSR ;And save them
|
2000-08-20 14:08:44 +00:00
|
|
|
move.l (a0)+,10+4(sp) ;Store return address in exception stack frame
|
|
|
|
|
|
|
|
move.w (a0)+,d0 ;get format word
|
|
|
|
lsr.w #7,d0 ;get stack frame Id
|
|
|
|
lsr.w #4,d0
|
|
|
|
and.w #$001e,d0
|
|
|
|
move.w (StackFormatTable,pc,d0.w),d0 ; get total stack frame length
|
|
|
|
subq.w #4,d0 ; count only extra words
|
|
|
|
lea 16+4(sp),a1 ; destination address (in supervisor stack)
|
|
|
|
bra 1$
|
|
|
|
|
|
|
|
2$: move.w (a0)+,(a1)+ ; copy additional stack words back to supervisor stack
|
|
|
|
1$: dbf d0,2$
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
move.l a0,usp ;Update USP
|
2000-08-20 14:08:44 +00:00
|
|
|
movem.l (sp)+,a0/a1 ;Restore a0 and a1
|
1999-10-03 14:16:26 +00:00
|
|
|
move.l (sp)+,d0 ;Restore d0
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
; sizes of exceptions stack frames
|
|
|
|
StackFormatTable:
|
|
|
|
dc.w 4 ; Four-word stack frame, format $0
|
|
|
|
dc.w 4 ; Throwaway four-word stack frame, format $1
|
|
|
|
dc.w 6 ; Six-word stack frame, format $2
|
|
|
|
dc.w 6 ; MC68040 floating-point post-instruction stack frame, format $3
|
|
|
|
dc.w 8 ; MC68EC040 and MC68LC040 floating-point unimplemented stack frame, format $4
|
|
|
|
dc.w 4 ; Format $5
|
|
|
|
dc.w 4 ; Format $6
|
|
|
|
dc.w 30 ; MC68040 access error stack frame, Format $7
|
|
|
|
dc.w 29 ; MC68010 bus and address error stack frame, format $8
|
|
|
|
dc.w 10 ; MC68020 and MC68030 coprocessor mid-instruction stack frame, format $9
|
|
|
|
dc.w 16 ; MC68020 and MC68030 short bus cycle stack frame, format $a
|
|
|
|
dc.w 46 ; MC68020 and MC68030 long bus cycle stack frame, format $b
|
|
|
|
dc.w 12 ; CPU32 bus error for prefetches and operands stack frame, format $c
|
|
|
|
dc.w 4 ; Format $d
|
|
|
|
dc.w 4 ; Format $e
|
|
|
|
dc.w 4 ; Format $f
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
; move sr,dx
|
|
|
|
movefromsrd0 addq.l #4,sp ;Skip saved d0
|
|
|
|
moveq #0,d0
|
|
|
|
move.w (sp),d0 ;Get CCR
|
|
|
|
or.w _EmulatedSR,d0 ;Add emulated supervisor bits
|
|
|
|
addq.l #2,2(sp) ;Skip instruction
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd1 move.l (sp)+,d0
|
|
|
|
moveq #0,d1
|
|
|
|
move.w (sp),d1
|
|
|
|
or.w _EmulatedSR,d1
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd2 move.l (sp)+,d0
|
|
|
|
moveq #0,d2
|
|
|
|
move.w (sp),d2
|
|
|
|
or.w _EmulatedSR,d2
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd3 move.l (sp)+,d0
|
|
|
|
moveq #0,d3
|
|
|
|
move.w (sp),d3
|
|
|
|
or.w _EmulatedSR,d3
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd4 move.l (sp)+,d0
|
|
|
|
moveq #0,d4
|
|
|
|
move.w (sp),d4
|
|
|
|
or.w _EmulatedSR,d4
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd5 move.l (sp)+,d0
|
|
|
|
moveq #0,d5
|
|
|
|
move.w (sp),d5
|
|
|
|
or.w _EmulatedSR,d5
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd6 move.l (sp)+,d0
|
|
|
|
moveq #0,d6
|
|
|
|
move.w (sp),d6
|
|
|
|
or.w _EmulatedSR,d6
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movefromsrd7 move.l (sp)+,d0
|
|
|
|
moveq #0,d7
|
|
|
|
move.w (sp),d7
|
|
|
|
or.w _EmulatedSR,d7
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; move dx,sr
|
|
|
|
movetosrd0 move.l (sp),d0
|
|
|
|
storesr2 move.w d0,4(sp)
|
|
|
|
and.w #$00ff,4(sp)
|
2000-08-20 14:08:44 +00:00
|
|
|
and.w #$e700,d0
|
1999-10-03 14:16:26 +00:00
|
|
|
move.w d0,_EmulatedSR
|
|
|
|
|
|
|
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled
|
|
|
|
bne.s 1$
|
|
|
|
tst.l _InterruptFlags
|
|
|
|
beq.s 1$
|
|
|
|
movem.l d0-d1/a0-a1/a6,-(sp)
|
|
|
|
move.l _SysBase,a6
|
|
|
|
move.l _MainTask,a1
|
|
|
|
move.l _IRQSigMask,d0
|
|
|
|
JSRLIB Signal
|
|
|
|
movem.l (sp)+,d0-d1/a0-a1/a6
|
|
|
|
1$ move.l (sp)+,d0
|
|
|
|
addq.l #2,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
movetosrd1 move.l d1,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd2 move.l d2,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd3 move.l d3,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd4 move.l d4,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd5 move.l d5,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd6 move.l d6,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
movetosrd7 move.l d7,d0
|
|
|
|
bra.s storesr2
|
|
|
|
|
|
|
|
; movec cr,x
|
|
|
|
movecfromcr move.w ([6,sp],2),d0 ;Get next instruction word
|
|
|
|
|
|
|
|
cmp.w #$8801,d0 ;movec vbr,a0?
|
|
|
|
beq.s movecvbra0
|
|
|
|
cmp.w #$9801,d0 ;movec vbr,a1?
|
|
|
|
beq.s movecvbra1
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$1801,d0 ;movec vbr,d1?
|
|
|
|
beq movecvbrd1
|
1999-10-03 14:16:26 +00:00
|
|
|
cmp.w #$0002,d0 ;movec cacr,d0?
|
|
|
|
beq.s moveccacrd0
|
|
|
|
cmp.w #$1002,d0 ;movec cacr,d1?
|
|
|
|
beq.s moveccacrd1
|
|
|
|
cmp.w #$0003,d0 ;movec tc,d0?
|
|
|
|
beq.s movectcd0
|
|
|
|
cmp.w #$1003,d0 ;movec tc,d1?
|
|
|
|
beq.s movectcd1
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$1000,d0 ;movec SFC,d1?
|
|
|
|
beq movecsfcd1
|
|
|
|
cmp.w #$1001,d0 ;movec DFC,d1?
|
|
|
|
beq movecdfcd1
|
|
|
|
cmp.w #$0806,d0 ;movec URP,d0?
|
|
|
|
beq movecurpd0
|
|
|
|
cmp.w #$0807,d0 ;movec SRP,d0?
|
|
|
|
beq.s movecsrpd0
|
|
|
|
cmp.w #$0004,d0 ;movec ITT0,d0
|
|
|
|
beq.s movecitt0d0
|
|
|
|
cmp.w #$0005,d0 ;movec ITT1,d0
|
|
|
|
beq.s movecitt1d0
|
|
|
|
cmp.w #$0006,d0 ;movec DTT0,d0
|
|
|
|
beq.s movecdtt0d0
|
|
|
|
cmp.w #$0007,d0 ;movec DTT1,d0
|
|
|
|
beq.s movecdtt1d0
|
1999-10-03 14:16:26 +00:00
|
|
|
|
|
|
|
bra pv_unhandled
|
|
|
|
|
|
|
|
; movec cacr,d0
|
|
|
|
moveccacrd0 move.l (sp)+,d0
|
|
|
|
move.l #$3111,d0 ;All caches and bursts on
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec cacr,d1
|
|
|
|
moveccacrd1 move.l (sp)+,d0
|
|
|
|
move.l #$3111,d1 ;All caches and bursts on
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec vbr,a0
|
|
|
|
movecvbra0 move.l (sp)+,d0
|
|
|
|
sub.l a0,a0 ;VBR always appears to be at 0
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec vbr,a1
|
|
|
|
movecvbra1 move.l (sp)+,d0
|
|
|
|
sub.l a1,a1 ;VBR always appears to be at 0
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
; movec vbr,d1
|
|
|
|
movecvbrd1 move.l (sp)+,d0
|
|
|
|
moveq.l #0,d1 ;VBR always appears to be at 0
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
; movec tc,d0
|
|
|
|
movectcd0 addq.l #4,sp
|
|
|
|
moveq #0,d0 ;MMU is always off
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
; movec tc,d1 +jl+
|
|
|
|
movectcd1 move.l (sp)+,d0 ;Restore d0
|
|
|
|
moveq #0,d1 ;MMU is always off
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec SFC,d1 +jl+
|
|
|
|
movecsfcd1: move.l (sp)+,d0 ;Restore d0
|
|
|
|
moveq #0,d1 ;MMU is always off
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec DFC,d1 +jl+
|
|
|
|
movecdfcd1: move.l (sp)+,d0 ;Restore d0
|
1999-10-03 14:16:26 +00:00
|
|
|
moveq #0,d1 ;MMU is always off
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
movecurpd0: ; movec URP,d0 +jl+
|
|
|
|
movecsrpd0: ; movec SRP,d0
|
|
|
|
movecitt0d0: ; movec ITT0,d0
|
|
|
|
movecitt1d0: ; movec ITT1,d0
|
|
|
|
movecdtt0d0: ; movec DTT0,d0
|
|
|
|
movecdtt1d0: ; movec DTT1,d0
|
|
|
|
addq.l #4,sp
|
|
|
|
moveq.l #0,d0 ;MMU is always off
|
|
|
|
addq.l #4,2(sp) ;skip instruction
|
|
|
|
rte
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
; movec x,cr
|
|
|
|
movectocr move.w ([6,sp],2),d0 ;Get next instruction word
|
|
|
|
|
|
|
|
cmp.w #$0801,d0 ;movec d0,vbr?
|
|
|
|
beq.s movectovbr
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$1801,d0 ;movec d1,vbr?
|
|
|
|
beq.s movectovbr
|
1999-10-03 14:16:26 +00:00
|
|
|
cmp.w #$0002,d0 ;movec d0,cacr?
|
|
|
|
beq.s movectocacr
|
|
|
|
cmp.w #$1002,d0 ;movec d1,cacr?
|
|
|
|
beq.s movectocacr
|
2000-08-20 14:08:44 +00:00
|
|
|
cmp.w #$1000,d0 ;movec d1,SFC?
|
|
|
|
beq.s movectoxfc
|
|
|
|
cmp.w #$1001,d0 ;movec d1,DFC?
|
|
|
|
beq.s movectoxfc
|
1999-10-03 14:16:26 +00:00
|
|
|
|
|
|
|
bra pv_unhandled
|
|
|
|
|
|
|
|
; movec x,vbr
|
|
|
|
movectovbr move.l (sp)+,d0 ;Ignore moves to VBR
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
|
|
|
; movec dx,cacr
|
|
|
|
movectocacr movem.l d1/a0-a1/a6,-(sp) ;Move to CACR, clear caches
|
|
|
|
move.l _SysBase,a6
|
|
|
|
JSRLIB CacheClearU
|
|
|
|
movem.l (sp)+,d1/a0-a1/a6
|
|
|
|
move.l (sp)+,d0
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
2000-08-20 14:08:44 +00:00
|
|
|
; movec x,SFC
|
|
|
|
; movec x,DFC
|
|
|
|
movectoxfc move.l (sp)+,d0 ;Ignore moves to SFC, DFC
|
|
|
|
addq.l #4,2(sp)
|
|
|
|
rte
|
|
|
|
|
1999-10-03 14:16:26 +00:00
|
|
|
; cpusha
|
|
|
|
cpushadc
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cpushadcic movem.l d1/a0-a1/a6,-(sp) ;Clear caches
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move.l _SysBase,a6
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JSRLIB CacheClearU
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movem.l (sp)+,d1/a0-a1/a6
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move.l (sp)+,d0
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addq.l #2,2(sp)
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rte
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2000-08-20 14:08:44 +00:00
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; move usp,a1 +jl+
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moveuspa1: move.l (sp)+,d0
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move usp,a1
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addq.l #2,2(sp)
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rte
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; move usp,a0 +jl+
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moveuspa0: move.l (sp)+,d0
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move usp,a0
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addq.l #2,2(sp)
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rte
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; move a1,usp +jl+
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moved1usp: move.l (sp)+,d0
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move a1,usp
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addq.l #2,2(sp)
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rte
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;
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|
; Trigger NMI (Pop up debugger)
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;
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_AsmTriggerNMI:
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move.l d0,-(sp) ;Save d0
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move.w #$007c,-(sp) ;Yes, fake NMI stack frame
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pea 1$
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move.w _EmulatedSR,d0
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and.w #$f8ff,d0 ;Set interrupt level in SR
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move.w d0,-(sp)
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move.w d0,_EmulatedSR
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move.l $7c.w,-(sp) ;Jump to MacOS NMI handler
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rts
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1$ move.l (sp)+,d0 ;Restore d0
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rts
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1999-10-03 14:16:26 +00:00
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END
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