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https://github.com/kanjitalk755/macemu.git
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Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model.
This commit is contained in:
gbeauche
parent
e3c5f1769d
commit
0c255e1fbd
@ -200,6 +200,16 @@ LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
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}
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LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
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LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
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{
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#if defined(__x86_64__)
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POPQm(d, X86_NOREG, X86_NOREG, 1);
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#else
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POPLm(d, X86_NOREG, X86_NOREG, 1);
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#endif
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}
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LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
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LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
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{
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BTLir(i, r);
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@ -925,6 +935,12 @@ LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
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}
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LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
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LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
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{
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XORLir(i, d);
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}
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LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
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LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
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{
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ANDLir(i, d);
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@ -1208,6 +1224,14 @@ LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
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}
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LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
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LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
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{
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emit_byte(0x8f);
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emit_byte(0x05);
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emit_long(d);
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}
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LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
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LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
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{
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emit_byte(0x0f);
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@ -2500,6 +2524,14 @@ LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
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}
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LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
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LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
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{
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emit_byte(0x81);
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emit_byte(0xf0+d);
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emit_long(i);
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}
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LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
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LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
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{
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if (optimize_imm8 && isbyte(i)) {
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@ -3214,6 +3246,18 @@ static __inline__ void raw_reg_to_flags(int r)
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raw_sahf(0);
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}
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#define FLAG_NREG3 0 /* Set to -1 if any register will do */
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static __inline__ void raw_flags_set_zero(int s, int tmp)
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{
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raw_mov_l_rr(tmp,s);
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raw_lahf(s); /* flags into ah */
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raw_and_l_ri(s,0xffffbfff);
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raw_and_l_ri(tmp,0x00004000);
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raw_xor_l_ri(tmp,0x00004000);
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raw_or_l(s,tmp);
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raw_sahf(s);
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}
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#else
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#define FLAG_NREG1 -1 /* Set to -1 if any register will do */
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@ -3240,6 +3284,19 @@ static __inline__ void raw_reg_to_flags(int r)
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raw_popfl();
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}
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#define FLAG_NREG3 -1 /* Set to -1 if any register will do */
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static __inline__ void raw_flags_set_zero(int s, int tmp)
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{
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raw_mov_l_rr(tmp,s);
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raw_pushfl();
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raw_pop_l_r(s);
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raw_and_l_ri(s,0xffffffbf);
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raw_and_l_ri(tmp,0x00000040);
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raw_xor_l_ri(tmp,0x00000040);
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raw_or_l(s,tmp);
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raw_push_l_r(s);
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raw_popfl();
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}
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#endif
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/* Apparently, there are enough instructions between flag store and
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@ -3265,22 +3322,6 @@ static __inline__ void raw_load_flagx(uae_u32 target, uae_u32 r)
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raw_mov_l_rm(target,(uintptr)live.state[r].mem);
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}
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#define NATIVE_FLAG_Z 0x40
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static __inline__ void raw_flags_set_zero(int f, int r, int t)
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{
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// FIXME: this is really suboptimal
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raw_pushfl();
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raw_pop_l_r(f);
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raw_and_l_ri(f,~NATIVE_FLAG_Z);
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raw_test_l_rr(r,r);
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raw_mov_l_ri(r,0);
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raw_mov_l_ri(t,NATIVE_FLAG_Z);
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raw_cmov_l_rr(r,t,NATIVE_CC_EQ);
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raw_or_l(f,r);
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raw_push_l_r(f);
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raw_popfl();
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}
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static __inline__ void raw_inc_sp(int off)
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{
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raw_add_l_ri(ESP_INDEX,off);
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@ -348,8 +348,7 @@ DECLARE_MIDFUNC(setcc(W1 d, IMM cc));
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DECLARE_MIDFUNC(setcc_m(IMM d, IMM cc));
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DECLARE_MIDFUNC(cmov_l_rr(RW4 d, R4 s, IMM cc));
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DECLARE_MIDFUNC(cmov_l_rm(RW4 d, IMM s, IMM cc));
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/* Set native Z flag only if register is zero */
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DECLARE_MIDFUNC(setzflg_l(RW4 r));
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DECLARE_MIDFUNC(bsf_l_rr(W4 d, R4 s));
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DECLARE_MIDFUNC(pop_m(IMM d));
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DECLARE_MIDFUNC(push_m(IMM d));
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DECLARE_MIDFUNC(pop_l(W4 d));
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@ -516,6 +515,8 @@ extern void writelong_clobber(int address, int source, int tmp);
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extern void get_n_addr(int address, int dest, int tmp);
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extern void get_n_addr_jmp(int address, int dest, int tmp);
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extern void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp);
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/* Set native Z flag only if register is zero */
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extern void set_zero(int r, int tmp);
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extern int kill_rodent(int r);
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extern void sync_m68k_pc(void);
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extern uae_u32 get_const(int r);
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@ -121,6 +121,9 @@ static compop_func *nfcompfunctbl[65536];
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static cpuop_func *nfcpufunctbl[65536];
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uae_u8* comp_pc_p;
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// From main_unix.cpp
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extern bool ThirtyThreeBitAddressing;
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// From newcpu.cpp
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extern bool quit_program;
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@ -2934,30 +2937,30 @@ MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
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}
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MENDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
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MIDFUNC(1,setzflg_l,(RW4 r))
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MIDFUNC(2,bsf_l_rr,(W4 d, W4 s))
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{
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if (setzflg_uses_bsf) {
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CLOBBER_BSF;
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r=rmw(r,4,4);
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raw_bsf_l_rr(r,r);
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unlock2(r);
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}
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else {
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Dif (live.flags_in_flags!=VALID) {
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write_log("setzflg() wanted flags in native flags, they are %d\n",
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live.flags_in_flags);
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abort();
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}
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r=readreg(r,4);
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int f=writereg(S11,4);
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int t=writereg(S12,4);
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raw_flags_set_zero(f,r,t);
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unlock2(f);
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unlock2(r);
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unlock2(t);
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}
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CLOBBER_BSF;
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s = readreg(s, 4);
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d = writereg(d, 4);
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raw_bsf_l_rr(d, s);
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unlock2(s);
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unlock2(d);
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}
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MENDFUNC(1,setzflg_l,(RW4 r))
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MENDFUNC(2,bsf_l_rr,(W4 d, W4 s))
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/* Set the Z flag depending on the value in s. Note that the
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value has to be 0 or -1 (or, more precisely, for non-zero
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values, bit 14 must be set)! */
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MIDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
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{
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CLOBBER_BSF;
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s=rmw_specific(s,4,4,FLAG_NREG3);
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tmp=writereg(tmp,4);
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raw_flags_set_zero(s, tmp);
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unlock2(tmp);
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unlock2(s);
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}
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MENDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
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MIDFUNC(2,imul_32_32,(RW4 d, R4 s))
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{
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@ -4879,6 +4882,14 @@ MENDFUNC(2,fmul_rr,(FRW d, FR s))
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* Support functions exposed to gencomp. CREATE time *
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********************************************************************/
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void set_zero(int r, int tmp)
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{
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if (setzflg_uses_bsf)
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bsf_l_rr(r,r);
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else
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simulate_bsf(tmp,r);
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}
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int kill_rodent(int r)
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{
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return KILLTHERAT &&
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@ -5366,8 +5377,8 @@ static void writemem_real(int address, int source, int size, int tmp, int clobbe
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f=source;
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#if SIZEOF_VOID_P == 8
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/* HACK: address calculation is suboptimal and possibly broken */
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sign_extend_32_rr(address, address);
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if (!ThirtyThreeBitAddressing)
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sign_extend_32_rr(address, address);
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#endif
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switch(size) {
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@ -5430,8 +5441,8 @@ static void readmem_real(int address, int dest, int size, int tmp)
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f=dest;
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#if SIZEOF_VOID_P == 8
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/* HACK: address calculation is suboptimal and possibly broken */
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sign_extend_32_rr(address, address);
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if (!ThirtyThreeBitAddressing)
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sign_extend_32_rr(address, address);
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#endif
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switch(size) {
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@ -1100,7 +1100,7 @@ genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
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"\tint one=scratchie++;\n"
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"\tif (needed_flags&FLAG_Z) {\n"
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"\tmov_l_ri(zero,0);\n"
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"\tmov_l_ri(one,1);\n"
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"\tmov_l_ri(one,-1);\n"
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"\tmake_flags_live();\n"
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"\tcmov_l_rr(zero,one,5);\n"
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"\t}\n");
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@ -1123,7 +1123,7 @@ genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
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comprintf("\tlive_flags();\n");
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comprintf("\tif (needed_flags&FLAG_Z) {\n"
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"\tcmov_l_rr(zero,one,5);\n"
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"\tsetzflg_l(zero);\n"
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"\tset_zero(zero, one);\n" /* No longer need one */
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"\tlive_flags();\n"
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"\t}\n");
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comprintf("\tend_needflags();\n");
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@ -1365,6 +1365,7 @@ gen_opcode (unsigned long int opcode)
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genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
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start_brace();
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comprintf("\tint s=scratchie++;\n"
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"\tint tmp=scratchie++;\n"
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"\tmov_l_rr(s,src);\n");
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if (curi->size == sz_byte)
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comprintf("\tand_l_ri(s,7);\n");
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@ -1380,6 +1381,7 @@ gen_opcode (unsigned long int opcode)
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case i_BCLR: op="btr"; break;
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case i_BSET: op="bts"; break;
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case i_BTST: op="bt"; need_write=0; break;
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default: abort();
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}
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comprintf("\t%s_l_rr(dst,s);\n" /* Answer now in C */
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"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
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@ -1387,7 +1389,7 @@ gen_opcode (unsigned long int opcode)
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"\tdont_care_flags();\n",op);
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if (!noflags) {
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comprintf("\tstart_needflags();\n"
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"\tsetzflg_l(s);\n"
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"\tset_zero(s,tmp);\n"
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"\tlive_flags();\n"
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"\tend_needflags();\n");
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}
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