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handle CR cache though it's not efficient with current approach without
superblock (traces) optimization.
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@ -198,13 +198,49 @@ void powerpc_dyngen::gen_record_cr0_T0(void)
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gen_compare_T0_im(0, 0);
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gen_compare_T0_im(0, 0);
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}
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}
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/**
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* Prepare condition register cache for branch
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*
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* This was meant to be a CR caching system but gain is almost
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* zero. However, this shows the ability to handle a CR cache
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* forwards and actually, a superblock-level (traces) optimizer
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* with proper code generation will benefit from it.
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**/
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#define USE_CR_CACHE 1
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void powerpc_dyngen::gen_prepare_RC(int bi)
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void powerpc_dyngen::gen_prepare_RC(int bi)
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{
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{
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const int crf = bi / 4;
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const int crf = bi / 4;
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const int crb = bi % 4;
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const int crb = bi % 4;
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#if USE_CR_CACHE
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if (rc_cache.crf() == crf) {
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if (crb != 3) {
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// Rematerialize (LT, GT, EQ) if they are not live
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if (rc_cache.val_status() == RC_cache::STATUS_VALID)
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gen_commit_rc_cache_cr(crf);
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else
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gen_load_RC_cr(crf);
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}
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else {
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// Rematerialize SO if it is not in cache
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if (rc_cache.so_status() == RC_cache::STATUS_VALID)
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gen_commit_so_cache_cr(crf);
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else
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gen_load_RC_cr(crf);
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}
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invalidate_cr_cache();
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}
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else {
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// Reload flags from memory
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gen_commit_cr();
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gen_load_RC_cr(crf);
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}
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#else
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gen_commit_cr();
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gen_commit_cr();
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gen_load_RC_cr(crf);
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gen_load_RC_cr(crf);
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#endif
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}
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}
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void powerpc_dyngen::gen_bc_A0(int bo, int bi, uint32 npc)
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void powerpc_dyngen::gen_bc_A0(int bo, int bi, uint32 npc)
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