Macintosh-Tools
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macemu
mirror of https://github.com/kanjitalk755/macemu.git
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fixed merge error and deleted unnecessary files

This commit is contained in:
kanjitalk755 2021-05-04 18:33:50 +09:00
parent 65028aec4a
commit 1aaeaf05c4
57 changed files with 120 additions and 20950 deletions
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75
BasiliskII/src/MacOSX/BasiliskII.xcodeproj/project.pbxproj
View File

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@ -410,7 +409,7 @@
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E413D8FE20D260B900E437D8 /* VERSION */,
E413D8FE20D260B900E437D8 /* VERSION_ */,
);
name = slirp;
path = ../slirp;
@ -444,12 +443,11 @@
E4ED8EE024E39BC400843219 /* compemu.cpp */,
E4ED8EE124E39BC400843219 /* compstbl.cpp */,
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E417913123D7D67C0009AD63 /* defs68k.c */,
E4CF025926396211006FDAEA /* cpufunctbl.cpp */,
);
name = "gencpu output";
sourceTree = "<group>";
@ -583,16 +581,16 @@
753252E51F5359040024025B /* build68k.c */,
7539E0A81F23B25A006B2DF2 /* compiler */,
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E43D1D9D2638F6E0008957D9 /* registers.h */,
7539E0D01F23B25A006B2DF2 /* spcflags.h */,
7539E0D11F23B25A006B2DF2 /* table68k */,
);
@ -614,7 +612,8 @@
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isa = PBXGroup;
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@ -832,12 +831,11 @@
name = "Run Script";
outputPaths = (
$BUILT_PRODUCTS_DIR/gencpu_output/cpuemu.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/cpuemu_nf.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/cpustbl.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/cpustbl_nf.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/defs68k.c,
$BUILT_PRODUCTS_DIR/gencpu_output/compemu.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/compstbl.cpp,
$BUILT_PRODUCTS_DIR/gencpu_output/cpufunctbl.cpp,
);
runOnlyForDeploymentPostprocessing = 0;
shellPath = /bin/sh;
@ -851,26 +849,24 @@
buildActionMask = 2147483647;
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757A2BF01F5AF9D6003EDB01 /* user_strings_unix.cpp in Sources */,
E413D92D20D260BC00E437D8 /* tcp_timer.c in Sources */,
E413D92820D260BC00E437D8 /* tcp_subr.c in Sources */,
E4257923264116F70061C1F1 /* fpu_ieee.cpp in Sources */,
7539E1991F23B25A006B2DF2 /* flags.cpp in Sources */,
7539E2921F23C56F006B2DF2 /* scsi_dummy.cpp in Sources */,
E413D93A20D2614E00E437D8 /* extfs_macosx.cpp in Sources */,
@ -931,9 +926,11 @@
E413D92120D260BC00E437D8 /* tftp.c in Sources */,
7539E1731F23B25A006B2DF2 /* scsi.cpp in Sources */,
7539E12B1F23B25A006B2DF2 /* disk.cpp in Sources */,
E40A4005263C306A00B76E31 /* fpu_mpfr.cpp in Sources */,
E413D92320D260BC00E437D8 /* ip_icmp.c in Sources */,
7539E1E31F23B25A006B2DF2 /* xpram.cpp in Sources */,
7539E2681F23B32A006B2DF2 /* rpc_unix.cpp in Sources */,
E4CF025A26396211006FDAEA /* cpufunctbl.cpp in Sources */,
E413D92F20D260BC00E437D8 /* bootp.c in Sources */,
7539E2911F23C56F006B2DF2 /* prefs_editor_dummy.cpp in Sources */,
);
@ -1094,6 +1091,8 @@
"GCC_PREPROCESSOR_DEFINITIONS[arch=arm64]" = "$(inherited)";
"GCC_PREPROCESSOR_DEFINITIONS[arch=x86_64]" = (
"$(inherited)",
CPU_x86_64,
JIT,
"USE_JIT=1",
);
GCC_SYMBOLS_PRIVATE_EXTERN = NO;
@ -1102,6 +1101,7 @@
GCC_WARN_CHECK_SWITCH_STATEMENTS = NO;
GCC_WARN_UNUSED_VARIABLE = NO;
HEADER_SEARCH_PATHS = (
/opt/homebrew/include,
/Library/Frameworks/SDL2.framework/Headers,
../MacOSX,
../include,
@ -1112,11 +1112,15 @@
INFOPLIST_FILE = "$(SRCROOT)/Info.plist";
INSTALL_PATH = "$(HOME)/Applications";
LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks";
LIBRARY_SEARCH_PATHS = /opt/homebrew/lib;
MACOSX_DEPLOYMENT_TARGET = 10.7;
ONLY_ACTIVE_ARCH = NO;
OTHER_CFLAGS = "";
OTHER_LDFLAGS = "";
"OTHER_LDFLAGS[arch=arm64]" = "";
"OTHER_LDFLAGS[arch=arm64]" = (
"-lgmp",
"-lmpfr",
);
"OTHER_LDFLAGS[arch=x86_64]" = (
"-Wl,-no_pie",
"-pagezero_size",
@ -1162,6 +1166,8 @@
"GCC_PREPROCESSOR_DEFINITIONS[arch=arm64]" = "$(inherited)";
"GCC_PREPROCESSOR_DEFINITIONS[arch=x86_64]" = (
"$(inherited)",
CPU_x86_64,
JIT,
"USE_JIT=1",
);
GCC_SYMBOLS_PRIVATE_EXTERN = NO;
@ -1170,6 +1176,7 @@
GCC_WARN_CHECK_SWITCH_STATEMENTS = NO;
GCC_WARN_UNUSED_VARIABLE = NO;
HEADER_SEARCH_PATHS = (
/opt/homebrew/include,
/Library/Frameworks/SDL2.framework/Headers,
../MacOSX,
../include,
@ -1180,10 +1187,14 @@
INFOPLIST_FILE = "$(SRCROOT)/Info.plist";
INSTALL_PATH = "$(HOME)/Applications";
LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks";
LIBRARY_SEARCH_PATHS = /opt/homebrew/lib;
MACOSX_DEPLOYMENT_TARGET = 10.7;
OTHER_CFLAGS = "";
OTHER_LDFLAGS = "";
"OTHER_LDFLAGS[arch=arm64]" = "";
"OTHER_LDFLAGS[arch=arm64]" = (
"-lgmp",
"-lmpfr",
);
"OTHER_LDFLAGS[arch=x86_64]" = (
"-Wl,-no_pie",
"-pagezero_size",

18
BasiliskII/src/MacOSX/config.h
View File

@ -681,7 +681,11 @@
#define SIZEOF_LONG 8
/* The size of `long double', as computed by sizeof. */
#ifdef CPU_x86_64
#define SIZEOF_LONG_DOUBLE 16
#else
#define SIZEOF_LONG_DOUBLE 8
#endif
/* The size of `long long', as computed by sizeof. */
#define SIZEOF_LONG_LONG 8
@ -815,7 +819,21 @@
<inttypes.h> don't define. */
/* #undef uintmax_t */
#define UPDATE_UAE
#ifdef UPDATE_UAE
#define CPU_64_BIT
#define USE_INLINING
#ifdef CPU_x86_64
#define FPU_IEEE
#define WINUAE_ARANYM
#else
#define FPU_MPFR
#define DIRECT_ADDRESSING 1
#endif
#else
#define FPU_IEEE
#endif
#if USE_JIT
#define DIRECT_ADDRESSING 1

19
BasiliskII/src/Unix/main_unix.cpp
View File

@ -94,8 +94,13 @@ using std::string;
#include "rpc.h"
#if USE_JIT
#ifdef UPDATE_UAE
extern void (*flush_icache)(void); // from compemu_support.cpp
extern bool UseJIT;
#else
extern void flush_icache_range(uint8 *start, uint32 size); // from compemu_support.cpp
#endif
#endif
#ifdef ENABLE_MON
# include "mon.h"
@ -289,9 +294,14 @@ static void sigsegv_dump_state(sigsegv_info_t *sip)
fprintf(stderr, "\n");
#if EMULATED_68K
uaecptr nextpc;
#ifdef UPDATE_UAE
extern void m68k_dumpstate(FILE *, uaecptr *nextpc);
m68k_dumpstate(stderr, &nextpc);
#else
extern void m68k_dumpstate(uaecptr *nextpc);
m68k_dumpstate(&nextpc);
#endif
#endif
#if USE_JIT && JIT_DEBUG
extern void compiler_dumpstate(void);
compiler_dumpstate();
@ -990,8 +1000,12 @@ void FlushCodeCache(void *start, uint32 size)
{
#if USE_JIT
if (UseJIT)
#ifdef UPDATE_UAE
flush_icache();
#else
flush_icache_range((uint8 *)start, size);
#endif
#endif
#if !EMULATED_68K && defined(__NetBSD__)
m68k_sync_icache(start, size);
#endif
@ -1007,8 +1021,13 @@ static void sigint_handler(...)
{
#if EMULATED_68K
uaecptr nextpc;
#ifdef UPDATE_UAE
extern void m68k_dumpstate(FILE *, uaecptr *nextpc);
m68k_dumpstate(stderr, &nextpc);
#else
extern void m68k_dumpstate(uaecptr *nextpc);
m68k_dumpstate(&nextpc);
#endif
#endif
VideoQuitFullScreen();
const char *arg[4] = {"mon", "-m", "-r", NULL};

8
BasiliskII/src/Unix/sysdeps.h
View File

@ -490,4 +490,12 @@ static inline uae_u32 do_byteswap_16(uae_u32 v)
#endif
#define REGPARAM2
#ifndef UNUSED
#define UNUSED(x) ((void)x)
#endif
#define unlikely(x) __builtin_expect(!!(x), 0)
#define ALWAYS_INLINE inline __attribute__((always_inline))
#define memptr uint32
#endif

7
BasiliskII/src/include/main.h
View File

@ -34,8 +34,15 @@ extern bool TwentyFourBitAddressing;
// 68k register structure (for Execute68k())
struct M68kRegisters {
uint32 d[8];
#ifdef UPDATE_UAE
memptr a[8];
uint16 sr;
memptr usp, isp, msp;
memptr pc;
#else
uint32 a[8];
uint16 sr;
#endif
};
// General functions

80
BasiliskII/src/uae_cpu/Makefile.am
View File

@ -1,80 +0,0 @@
#
# Note: this Makefile only contains rules for the source
# generator tools.
#
#
# suppress warnings about overriding LDFLAGS and CPPFLAGS
#
AUTOMAKE_OPTIONS = -Wno-gnu
AM_CPPFLAGS = $(DEFINES) \
"-I$(srcdir)/../include" \
"-I$(srcdir)/../Unix" \
"-I$(builddir)/.." \
"-I$(builddir)" \
"-I$(srcdir)"
CC = $(CC_FOR_BUILD)
CXX = $(CXX_FOR_BUILD)
LDFLAGS = $(LDFLAGS_FOR_BUILD)
CPPFLAGS = $(CPPFLAGS_FOR_BUILD)
CFLAGS = $(CFLAGS_FOR_BUILD)
CXXFLAGS = $(CXXFLAGS_FOR_BUILD)
LIBS=-lm
CFLAGS_NOWARN = $(DBGSP)
AM_CFLAGS = $(CFLAGS_NOWARN) $(WFLAGS)
AM_CXXFLAGS = $(CFLAGS_NOWARN) $(WFLAGS)
noinst_PROGRAMS = build68k gencpu
if USE_JIT
noinst_PROGRAMS += gencomp
endif
BUILT_SOURCES = \
cpudefs.cpp \
cpuemu.cpp \
cpustbl.cpp \
cpufunctbl.cpp \
cputbl.h \
$(empty)
build68k_SOURCES = build68k.c
gencpu_SOURCES = gencpu.c m68k.h readcpu.cpp readcpu.h cpudefs.cpp
gencomp_SOURCES =
if GENCOMP_ARCH_X86
gencomp_SOURCES += compiler/gencomp.c
endif
if GENCOMP_ARCH_ARM
gencomp_SOURCES += compiler/gencomp_arm.c
endif
gencomp_SOURCES += readcpu.cpp cpudefs.cpp
if USE_JIT
BUILT_SOURCES += compemu.cpp compstbl.cpp comptbl.h
endif
cpudefs.cpp: build68k$(EXEEXT) $(srcdir)/table68k
$(AM_V_GEN)./build68k <$(srcdir)/table68k > $@
cpuemu.cpp: gencpu$(EXEEXT)
$(AM_V_GEN)./gencpu$(EXEEXT)
cpustbl.cpp cpufunctbl.cpp cputbl.h: cpuemu.cpp
compemu.cpp: gencomp$(EXEEXT)
$(AM_V_GEN)./gencomp$(EXEEXT)
compstbl.cpp comptbl.h: compemu.cpp
CLEANFILES = $(BUILT_SOURCES)
EXTRA_DIST = \
table68k \
compiler/codegen_arm.cpp compiler/codegen_arm.h \
compiler/compemu_midfunc_arm.cpp compiler/compemu_midfunc_arm.h \
compiler/compemu_midfunc_arm2.cpp compiler/compemu_midfunc_arm2.h \
compiler/test_codegen_arm.c \
compiler/codegen_x86.cpp compiler/codegen_x86.h \
compiler/compemu_midfunc_x86.cpp compiler/compemu_midfunc_x86.h \
compiler/test_codegen_x86.cpp \
$(empty)

326
BasiliskII/src/uae_cpu/aranym_glue.cpp
View File

@ -1,326 +0,0 @@
/*
* aranym_glue.cpp - CPU interface
*
* Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* This file is part of the ARAnyM project which builds a new and powerful
* TOS/FreeMiNT compatible virtual machine running on almost any hardware.
*
* ARAnyM is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* ARAnyM is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ARAnyM; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "sysdeps.h"
#include "cpu_emulation.h"
#include "newcpu.h"
#include "hardware.h"
#include "scc.h"
#include "input.h"
#ifdef USE_JIT
# include "compiler/compemu.h"
#endif
#include "nf_objs.h"
#include "debug.h"
// RAM and ROM pointers
memptr RAMBase = 0; // RAM base (Atari address space) gb-- init is important
uint8 *RAMBaseHost; // RAM base (host address space)
uint32 RAMSize = 0x00e00000; // Size of RAM
memptr ROMBase = 0x00e00000; // ROM base (Atari address space)
uint8 *ROMBaseHost; // ROM base (host address space)
uint32 ROMSize = 0x00100000; // Size of ROM
uint32 RealROMSize; // Real size of ROM
memptr HWBase = 0x00f00000; // HW base (Atari address space)
uint8 *HWBaseHost; // HW base (host address space)
uint32 HWSize = 0x00100000; // Size of HW space
memptr FastRAMBase = 0x01000000; // Fast-RAM base (Atari address space)
uint8 *FastRAMBaseHost; // Fast-RAM base (host address space)
#ifdef HW_SIGSEGV
uint8 *FakeIOBaseHost;
#endif
#ifdef FIXED_VIDEORAM
memptr VideoRAMBase = ARANYMVRAMSTART; // VideoRAM base (Atari address space)
#else
memptr VideoRAMBase; // VideoRAM base (Atari address space)
#endif
uint8 *VideoRAMBaseHost;// VideoRAM base (host address space)
//uint32 VideoRAMSize; // Size of VideoRAM
#ifndef NOT_MALLOC
uintptr MEMBaseDiff; // Global offset between a Atari address and its Host equivalent
uintptr ROMBaseDiff;
uintptr FastRAMBaseDiff;
#endif
uintptr VMEMBaseDiff; // Global offset between a Atari VideoRAM address and /dev/fb0 mmap
#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS)
SDL_mutex *spcflags_lock;
#endif
#if defined(ENABLE_REALSTOP)
SDL_cond *stop_condition;
#endif
/*
* Initialize 680x0 emulation
*/
bool InitMEM() {
InitMEMBaseDiff(RAMBaseHost, RAMBase);
InitROMBaseDiff(ROMBaseHost, ROMBase);
InitFastRAMBaseDiff(FastRAMBaseHost, FastRAMBase);
InitVMEMBaseDiff(VideoRAMBaseHost, VideoRAMBase);
return true;
}
bool Init680x0(void)
{
init_m68k();
#if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS)
if ((spcflags_lock = SDL_CreateMutex()) == NULL) {
panicbug("Error by SDL_CreateMutex()");
exit(EXIT_FAILURE);
}
#endif
#if ENABLE_REALSTOP
if ((stop_condition = SDL_CreateCond()) == NULL) {
panicbug("Error by SDL_CreateCond()");
exit(EXIT_FAILURE);
}
#endif
#ifdef USE_JIT
if (bx_options.jit.jit) compiler_init();
#endif
return true;
}
/*
* Instr. RESET
*/
void AtariReset(void)
{
// reset Atari hardware here
HWReset();
// reset NatFeats here
NFReset();
// reset the input devices (input.cpp)
InputReset();
}
/*
* Reset CPU
*/
void Reset680x0(void)
{
m68k_reset();
}
/*
* Deinitialize 680x0 emulation
*/
void Exit680x0(void)
{
#ifdef USE_JIT
if (bx_options.jit.jit) compiler_exit();
#endif
exit_m68k();
}
/*
* Reset and start 680x0 emulation
*/
void Start680x0(void)
{
m68k_reset();
#ifdef USE_JIT
if (bx_options.jit.jit) {
m68k_compile_execute();
}
else
#endif
m68k_execute();
}
/*
* Restart running 680x0 emulation safely from different thread
*/
void Restart680x0(void)
{
quit_program = 2;
TriggerNMI();
}
/*
* Quit 680x0 emulation safely from different thread
*/
void Quit680x0(void)
{
quit_program = 1;
TriggerNMI();
}
int MFPdoInterrupt(void)
{
return getMFP()->doInterrupt();
}
int SCCdoInterrupt(void)
{
return getSCC()->doInterrupt();
}
/*
* Trigger interrupts
*/
void TriggerInternalIRQ(void)
{
SPCFLAGS_SET( SPCFLAG_INTERNAL_IRQ );
}
void TriggerInt3(void)
{
SPCFLAGS_SET( SPCFLAG_INT3 );
}
void TriggerVBL(void)
{
SPCFLAGS_SET( SPCFLAG_VBL );
}
void TriggerInt5(void)
{
SPCFLAGS_SET( SPCFLAG_INT5 );
}
void TriggerSCC(bool enable)
{
if (enable)
SPCFLAGS_SET( SPCFLAG_SCC );
else
SPCFLAGS_CLEAR( SPCFLAG_SCC );
}
void TriggerMFP(bool enable)
{
if (enable)
SPCFLAGS_SET( SPCFLAG_MFP );
else
SPCFLAGS_CLEAR( SPCFLAG_MFP );
}
void TriggerNMI(void)
{
SPCFLAGS_SET( SPCFLAG_BRK ); // use _BRK for NMI
}
#ifndef REBOOT_OR_HALT
#define REBOOT_OR_HALT 0 // halt by default
#endif
#if REBOOT_OR_HALT == 1
# define CPU_MSG "CPU: Rebooting"
# define CPU_ACTION Restart680x0()
#else
# define CPU_MSG "CPU: Halting"
# define CPU_ACTION Quit680x0()
#endif
#ifdef ENABLE_EPSLIMITER
#ifndef EPS_LIMIT
# define EPS_LIMIT 10000 /* this might be too high if ARAnyM is slowed down by printing the bus errors on console */
#endif
void check_eps_limit(uaecptr pc)
{
static long last_exception_time=-1;
static long exception_per_sec=0;
static long exception_per_sec_pc=0;
static uaecptr prevpc = 0;
if (bx_options.cpu.eps_enabled) {
if (last_exception_time == -1) {
last_exception_time = SDL_GetTicks();
}
exception_per_sec++;
if (pc == prevpc) {
/* BUS ERRORs occur at the same PC - watch out! */
exception_per_sec_pc++;
}
else {
exception_per_sec_pc = 0;
prevpc = pc;
}
if (SDL_GetTicks() - last_exception_time > 1000) {
last_exception_time = SDL_GetTicks();
if (exception_per_sec_pc > bx_options.cpu.eps_max ||
exception_per_sec > EPS_LIMIT /* make it configurable */) {
panicbug("CPU: Exception per second limit reached: %ld/%ld",
exception_per_sec_pc, exception_per_sec);
/* would be cool to open SDL dialog here: */
/* [Exception per seconds limit reached. XXXXX exception
occured in the last second. The limit is set to YYYYY
in your config file. Do you want to continue emulation,
reset ARAnyM or quit ?][Continue] [Reset] [Quit]
*/
panicbug(CPU_MSG);
CPU_ACTION;
}
exception_per_sec = 0;
exception_per_sec_pc = 0;
}
}
}
#endif
void report_double_bus_error()
{
panicbug("CPU: Double bus fault detected !");
/* would be cool to open SDL dialog here: */
/* [Double bus fault detected. The emulated system crashed badly.
Do you want to reset ARAnyM or quit ?] [Reset] [Quit]"
*/
panicbug(CPU_MSG);
CPU_ACTION;
}
#ifdef FLIGHT_RECORDER
extern bool cpu_flight_recorder_active;
void cpu_flight_recorder(int activate) { cpu_flight_recorder_active = activate; }
#endif

2730
BasiliskII/src/uae_cpu/compiler/codegen_arm.cpp
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File diff suppressed because it is too large Load Diff

1292
BasiliskII/src/uae_cpu/compiler/codegen_arm.h
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File diff suppressed because it is too large Load Diff

2
BasiliskII/src/uae_cpu/compiler/compemu1.cpp
View File

@ -1,2 +0,0 @@
#define PART_1
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu2.cpp
View File

@ -1,2 +0,0 @@
#define PART_2
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu3.cpp
View File

@ -1,2 +0,0 @@
#define PART_3
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu4.cpp
View File

@ -1,2 +0,0 @@
#define PART_4
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu5.cpp
View File

@ -1,2 +0,0 @@
#define PART_5
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu6.cpp
View File

@ -1,2 +0,0 @@
#define PART_6
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu7.cpp
View File

@ -1,2 +0,0 @@
#define PART_7
#include "compemu.cpp"

2
BasiliskII/src/uae_cpu/compiler/compemu8.cpp
View File

@ -1,2 +0,0 @@
#define PART_8
#include "compemu.cpp"

4
BasiliskII/src/uae_cpu/compiler/compemu_fpp.cpp
View File

@ -37,6 +37,8 @@
* Adapted for JIT compilation (c) Bernd Meyer, 2000
*/
#ifdef USE_JIT
#include "sysdeps.h"
#include <cmath>
@ -2083,3 +2085,5 @@ void comp_fpp_opp(uae_u32 opcode, uae_u16 extra)
}
FAIL(1);
}
#endif

1967
BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp
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File diff suppressed because it is too large Load Diff

186
BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h
View File

@ -1,186 +0,0 @@
/*
* compiler/compemu_midfunc_arm.h - Native MIDFUNCS for ARM
*
* Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
*
* Adaptation for Basilisk II and improvements, copyright 2000-2002
* Gwenole Beauchesne
*
* Basilisk II (C) 1997-2002 Christian Bauer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Note:
* File is included by compemu.h
*
*/
// Arm optimized midfunc
DECLARE_MIDFUNC(arm_ADD_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_ADD_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(arm_ADD_l_ri8(RW4 d, IMM i));
DECLARE_MIDFUNC(arm_SUB_l_ri8(RW4 d, IMM i));
DECLARE_MIDFUNC(arm_AND_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(arm_AND_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(arm_AND_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_AND_l_ri8(RW4 d, IMM i));
DECLARE_MIDFUNC(arm_EOR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(arm_EOR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_EOR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(arm_ORR_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(arm_ORR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(arm_ORR_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(arm_ROR_l_ri8(RW4 r, IMM i));
// Emulated midfunc
DECLARE_MIDFUNC(bt_l_ri(RR4 r, IMM i));
DECLARE_MIDFUNC(bt_l_rr(RR4 r, RR4 b));
DECLARE_MIDFUNC(btc_l_rr(RW4 r, RR4 b));
DECLARE_MIDFUNC(bts_l_rr(RW4 r, RR4 b));
DECLARE_MIDFUNC(btr_l_rr(RW4 r, RR4 b));
DECLARE_MIDFUNC(mov_l_rm(W4 d, IMM s));
DECLARE_MIDFUNC(mov_l_rm_indexed(W4 d, IMM base, RR4 index, IMM factor));
DECLARE_MIDFUNC(mov_l_mi(IMM d, IMM s));
DECLARE_MIDFUNC(mov_w_mi(IMM d, IMM s));
DECLARE_MIDFUNC(mov_b_mi(IMM d, IMM s));
DECLARE_MIDFUNC(rol_b_ri(RW1 r, IMM i));
DECLARE_MIDFUNC(rol_w_ri(RW2 r, IMM i));
DECLARE_MIDFUNC(rol_l_rr(RW4 d, RR1 r));
DECLARE_MIDFUNC(rol_w_rr(RW2 d, RR1 r));
DECLARE_MIDFUNC(rol_b_rr(RW1 d, RR1 r));
DECLARE_MIDFUNC(rol_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(shll_l_rr(RW4 d, RR1 r));
DECLARE_MIDFUNC(shll_w_rr(RW2 d, RR1 r));
DECLARE_MIDFUNC(shll_b_rr(RW1 d, RR1 r));
DECLARE_MIDFUNC(ror_b_ri(RR1 r, IMM i));
DECLARE_MIDFUNC(ror_w_ri(RR2 r, IMM i));
DECLARE_MIDFUNC(ror_l_ri(RR4 r, IMM i));
DECLARE_MIDFUNC(ror_l_rr(RR4 d, RR1 r));
DECLARE_MIDFUNC(ror_w_rr(RR2 d, RR1 r));
DECLARE_MIDFUNC(ror_b_rr(RR1 d, RR1 r));
DECLARE_MIDFUNC(shrl_l_rr(RW4 d, RR1 r));
DECLARE_MIDFUNC(shrl_w_rr(RW2 d, RR1 r));
DECLARE_MIDFUNC(shrl_b_rr(RW1 d, RR1 r));
DECLARE_MIDFUNC(shra_l_rr(RW4 d, RR1 r));
DECLARE_MIDFUNC(shra_w_rr(RW2 d, RR1 r));
DECLARE_MIDFUNC(shra_b_rr(RW1 d, RR1 r));
DECLARE_MIDFUNC(shll_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(shll_w_ri(RW2 r, IMM i));
DECLARE_MIDFUNC(shll_b_ri(RW1 r, IMM i));
DECLARE_MIDFUNC(shrl_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(shrl_w_ri(RW2 r, IMM i));
DECLARE_MIDFUNC(shrl_b_ri(RW1 r, IMM i));
DECLARE_MIDFUNC(shra_l_ri(RW4 r, IMM i));
DECLARE_MIDFUNC(shra_w_ri(RW2 r, IMM i));
DECLARE_MIDFUNC(shra_b_ri(RW1 r, IMM i));
DECLARE_MIDFUNC(setcc(W1 d, IMM cc));
DECLARE_MIDFUNC(setcc_m(IMM d, IMM cc));
DECLARE_MIDFUNC(cmov_l_rr(RW4 d, RR4 s, IMM cc));
DECLARE_MIDFUNC(bsf_l_rr(W4 d, RR4 s));
DECLARE_MIDFUNC(pop_l(W4 d));
DECLARE_MIDFUNC(push_l(RR4 s));
DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s));
DECLARE_MIDFUNC(sign_extend_8_rr(W4 d, RR1 s));
DECLARE_MIDFUNC(zero_extend_16_rr(W4 d, RR2 s));
DECLARE_MIDFUNC(zero_extend_8_rr(W4 d, RR1 s));
DECLARE_MIDFUNC(simulate_bsf(W4 tmp, RW4 s));
DECLARE_MIDFUNC(imul_64_32(RW4 d, RW4 s));
DECLARE_MIDFUNC(mul_64_32(RW4 d, RW4 s));
DECLARE_MIDFUNC(imul_32_32(RW4 d, RR4 s));
DECLARE_MIDFUNC(mov_b_rr(W1 d, RR1 s));
DECLARE_MIDFUNC(mov_w_rr(W2 d, RR2 s));
DECLARE_MIDFUNC(mov_l_rR(W4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_w_rR(W2 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_l_brR(W4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_w_brR(W2 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_b_brR(W1 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_l_Ri(RR4 d, IMM i, IMM offset));
DECLARE_MIDFUNC(mov_w_Ri(RR4 d, IMM i, IMM offset));
DECLARE_MIDFUNC(mov_l_Rr(RR4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_w_Rr(RR4 d, RR2 s, IMM offset));
DECLARE_MIDFUNC(lea_l_brr(W4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(lea_l_brr_indexed(W4 d, RR4 s, RR4 index, IMM factor, IMM offset));
DECLARE_MIDFUNC(lea_l_rr_indexed(W4 d, RR4 s, RR4 index, IMM factor));
DECLARE_MIDFUNC(mov_l_bRr(RR4 d, RR4 s, IMM offset));
DECLARE_MIDFUNC(mov_w_bRr(RR4 d, RR2 s, IMM offset));
DECLARE_MIDFUNC(mov_b_bRr(RR4 d, RR1 s, IMM offset));
DECLARE_MIDFUNC(mid_bswap_32(RW4 r));
DECLARE_MIDFUNC(mid_bswap_16(RW2 r));
DECLARE_MIDFUNC(mov_l_rr(W4 d, RR4 s));
DECLARE_MIDFUNC(mov_l_mr(IMM d, RR4 s));
DECLARE_MIDFUNC(mov_w_mr(IMM d, RR2 s));
DECLARE_MIDFUNC(mov_w_rm(W2 d, IMM s));
DECLARE_MIDFUNC(mov_b_mr(IMM d, RR1 s));
DECLARE_MIDFUNC(mov_b_rm(W1 d, IMM s));
DECLARE_MIDFUNC(mov_l_ri(W4 d, IMM s));
DECLARE_MIDFUNC(mov_w_ri(W2 d, IMM s));
DECLARE_MIDFUNC(mov_b_ri(W1 d, IMM s));
DECLARE_MIDFUNC(test_l_ri(RR4 d, IMM i));
DECLARE_MIDFUNC(test_l_rr(RR4 d, RR4 s));
DECLARE_MIDFUNC(test_w_rr(RR2 d, RR2 s));
DECLARE_MIDFUNC(test_b_rr(RR1 d, RR1 s));
DECLARE_MIDFUNC(and_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(and_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(and_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(and_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(or_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(or_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(or_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(or_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(adc_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(adc_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(adc_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(add_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(add_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(add_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(sub_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(sub_w_ri(RW2 d, IMM i));
DECLARE_MIDFUNC(sub_b_ri(RW1 d, IMM i));
DECLARE_MIDFUNC(add_l_ri(RW4 d, IMM i));
DECLARE_MIDFUNC(add_w_ri(RW2 d, IMM i));
DECLARE_MIDFUNC(add_b_ri(RW1 d, IMM i));
DECLARE_MIDFUNC(sbb_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(sbb_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(sbb_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(sub_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(sub_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(sub_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(cmp_l(RR4 d, RR4 s));
DECLARE_MIDFUNC(cmp_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(cmp_b(RR1 d, RR1 s));
DECLARE_MIDFUNC(xor_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(xor_w(RW2 d, RR2 s));
DECLARE_MIDFUNC(xor_b(RW1 d, RR1 s));
DECLARE_MIDFUNC(call_r_02(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2));
DECLARE_MIDFUNC(call_r_11(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize));
DECLARE_MIDFUNC(live_flags(void));
DECLARE_MIDFUNC(dont_care_flags(void));
DECLARE_MIDFUNC(duplicate_carry(void));
DECLARE_MIDFUNC(restore_carry(void));
DECLARE_MIDFUNC(start_needflags(void));
DECLARE_MIDFUNC(end_needflags(void));
DECLARE_MIDFUNC(make_flags_live(void));
DECLARE_MIDFUNC(forget_about(W4 r));
DECLARE_MIDFUNC(nop(void));
DECLARE_MIDFUNC(f_forget_about(FW r));

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BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.cpp
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BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.h
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@ -1,348 +0,0 @@
/*
* compiler/compemu_midfunc_arm2.h - Native MIDFUNCS for ARM (JIT v2)
*
* Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
*
* Adaptation for Basilisk II and improvements, copyright 2000-2002
* Gwenole Beauchesne
*
* Basilisk II (C) 1997-2002 Christian Bauer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Note:
* File is included by compemu.h
*
*/
// Arm optimized midfunc
extern const uae_u32 ARM_CCR_MAP[];
DECLARE_MIDFUNC(restore_inverted_carry(void));
// ADD
DECLARE_MIDFUNC(jnf_ADD(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_ADD_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_ADD_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_ADD_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_ADD_b_imm(W4 d, RR1 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_w_imm(W4 d, RR2 s, IMM v));
DECLARE_MIDFUNC(jff_ADD_l_imm(W4 d, RR4 s, IMM v));
// ADDA
DECLARE_MIDFUNC(jnf_ADDA_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jnf_ADDA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_ADDA_l(W4 d, RR4 s));
// ADDX
DECLARE_MIDFUNC(jnf_ADDX(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_b(W4 d, RR1 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_w(W4 d, RR2 s, RR4 v));
DECLARE_MIDFUNC(jff_ADDX_l(W4 d, RR4 s, RR4 v));
// AND
DECLARE_MIDFUNC(jnf_AND(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_AND_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_AND_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_AND_l(W4 d, RR4 s, RR4 v));
// ANDSR
DECLARE_MIDFUNC(jff_ANDSR(IMM s, IMM x));
// ASL
DECLARE_MIDFUNC(jff_ASL_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASL_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASL_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASL_l_reg(W4 d, RR4 s, RR4 i));
// ASLW
DECLARE_MIDFUNC(jff_ASLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ASLW(W4 d, RR4 s));
// ASR
DECLARE_MIDFUNC(jnf_ASR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_ASR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_ASR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ASR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ASR_l_reg(W4 d, RR4 s, RR4 i));
// ASRW
DECLARE_MIDFUNC(jff_ASRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ASRW(W4 d, RR4 s));
// BCHG
DECLARE_MIDFUNC(jnf_BCHG_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCHG_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCHG_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCHG_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCHG_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCHG_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCHG_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCHG_l(RW4 d, RR4 s));
// BCLR
DECLARE_MIDFUNC(jnf_BCLR_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCLR_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BCLR_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BCLR_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCLR_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BCLR_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BCLR_l(RW4 d, RR4 s));
// BSET
DECLARE_MIDFUNC(jnf_BSET_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BSET_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jnf_BSET_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jnf_BSET_l(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BSET_b_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BSET_l_imm(RW4 d, IMM s));
DECLARE_MIDFUNC(jff_BSET_b(RW4 d, RR4 s));
DECLARE_MIDFUNC(jff_BSET_l(RW4 d, RR4 s));
// BTST
DECLARE_MIDFUNC(jff_BTST_b_imm(RR4 d, IMM s));
DECLARE_MIDFUNC(jff_BTST_l_imm(RR4 d, IMM s));
DECLARE_MIDFUNC(jff_BTST_b(RR4 d, RR4 s));
DECLARE_MIDFUNC(jff_BTST_l(RR4 d, RR4 s));
// CLR
DECLARE_MIDFUNC (jnf_CLR(W4 d));
DECLARE_MIDFUNC (jff_CLR(W4 d));
// CMP
DECLARE_MIDFUNC(jff_CMP_b(RR1 d, RR1 s));
DECLARE_MIDFUNC(jff_CMP_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(jff_CMP_l(RR4 d, RR4 s));
// CMPA
DECLARE_MIDFUNC(jff_CMPA_b(RR1 d, RR1 s));
DECLARE_MIDFUNC(jff_CMPA_w(RR2 d, RR2 s));
DECLARE_MIDFUNC(jff_CMPA_l(RR4 d, RR4 s));
// EOR
DECLARE_MIDFUNC(jnf_EOR(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_EOR_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_EOR_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_EOR_l(W4 d, RR4 s, RR4 v));
// EORSR
DECLARE_MIDFUNC(jff_EORSR(IMM s, IMM x));
// EXT
DECLARE_MIDFUNC(jnf_EXT_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_EXT_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_EXT_l(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_b(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_w(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_EXT_l(W4 d, RR4 s));
// LSL
DECLARE_MIDFUNC(jnf_LSL_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSL_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSL_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSL_l_reg(W4 d, RR4 s, RR4 i));
// LSLW
DECLARE_MIDFUNC(jff_LSLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_LSLW(W4 d, RR4 s));
// LSR
DECLARE_MIDFUNC(jnf_LSR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_b_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_w_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jff_LSR_l_imm(W4 d, RR4 s, IMM i));
DECLARE_MIDFUNC(jnf_LSR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_LSR_l_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_b_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_w_reg(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_LSR_l_reg(W4 d, RR4 s, RR4 i));
// LSRW
DECLARE_MIDFUNC(jff_LSRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_LSRW(W4 d, RR4 s));
// MOVE
DECLARE_MIDFUNC(jnf_MOVE(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_MOVE_b_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jff_MOVE_w_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jff_MOVE_l_imm(W4 d, IMM i));
DECLARE_MIDFUNC(jff_MOVE_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_MOVE_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_MOVE_l(W4 d, RR4 s));
// MOVE16
DECLARE_MIDFUNC(jnf_MOVE16(RR4 d, RR4 s));
// MOVEA
DECLARE_MIDFUNC(jnf_MOVEA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_MOVEA_l(W4 d, RR4 s));
// MULS
DECLARE_MIDFUNC (jnf_MULS(RW4 d, RR4 s));
DECLARE_MIDFUNC (jff_MULS(RW4 d, RR4 s));
DECLARE_MIDFUNC (jnf_MULS32(RW4 d, RR4 s));
DECLARE_MIDFUNC (jff_MULS32(RW4 d, RR4 s));
DECLARE_MIDFUNC (jnf_MULS64(RW4 d, RW4 s));
DECLARE_MIDFUNC (jff_MULS64(RW4 d, RW4 s));
// MULU
DECLARE_MIDFUNC (jnf_MULU(RW4 d, RR4 s));
DECLARE_MIDFUNC (jff_MULU(RW4 d, RR4 s));
DECLARE_MIDFUNC (jnf_MULU32(RW4 d, RR4 s));
DECLARE_MIDFUNC (jff_MULU32(RW4 d, RR4 s));
DECLARE_MIDFUNC (jnf_MULU64(RW4 d, RW4 s));
DECLARE_MIDFUNC (jff_MULU64(RW4 d, RW4 s));
// NEG
DECLARE_MIDFUNC(jnf_NEG(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NEG_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NEG_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NEG_l(W4 d, RR4 s));
// NEGX
DECLARE_MIDFUNC(jnf_NEGX(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NEGX_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NEGX_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NEGX_l(W4 d, RR4 s));
// NOT
DECLARE_MIDFUNC(jnf_NOT(W4 d, RR4 s));
DECLARE_MIDFUNC(jff_NOT_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jff_NOT_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jff_NOT_l(W4 d, RR4 s));
// OR
DECLARE_MIDFUNC(jnf_OR(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_OR_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_OR_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_OR_l(W4 d, RR4 s, RR4 v));
// ORSR
DECLARE_MIDFUNC(jff_ORSR(IMM s, IMM x));
// ROL
DECLARE_MIDFUNC(jnf_ROL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROL_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROL_l(W4 d, RR4 s, RR4 i));
// ROLW
DECLARE_MIDFUNC(jff_ROLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROLW(W4 d, RR4 s));
// RORW
DECLARE_MIDFUNC(jff_RORW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_RORW(W4 d, RR4 s));
// ROXL
DECLARE_MIDFUNC(jnf_ROXL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXL_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXL_l(W4 d, RR4 s, RR4 i));
// ROXLW
DECLARE_MIDFUNC(jff_ROXLW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROXLW(W4 d, RR4 s));
// ROR
DECLARE_MIDFUNC(jnf_ROR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROR_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROR_l(W4 d, RR4 s, RR4 i));
// ROXR
DECLARE_MIDFUNC(jnf_ROXR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jnf_ROXR_l(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_b(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_w(W4 d, RR4 s, RR4 i));
DECLARE_MIDFUNC(jff_ROXR_l(W4 d, RR4 s, RR4 i));
// ROXRW
DECLARE_MIDFUNC(jff_ROXRW(W4 d, RR4 s));
DECLARE_MIDFUNC(jnf_ROXRW(W4 d, RR4 s));
// SUB
DECLARE_MIDFUNC(jnf_SUB_b_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_b(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_SUB_w_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_w(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jnf_SUB_l_imm(W4 d, RR4 s, IMM v));
DECLARE_MIDFUNC(jnf_SUB_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUB_b(W4 d, RR1 s, RR1 v));
DECLARE_MIDFUNC(jff_SUB_w(W4 d, RR2 s, RR2 v));
DECLARE_MIDFUNC(jff_SUB_l(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUB_b_imm(W4 d, RR1 s, IMM v));
DECLARE_MIDFUNC(jff_SUB_w_imm(W4 d, RR2 s, IMM v));
DECLARE_MIDFUNC(jff_SUB_l_imm(W4 d, RR4 s, IMM v));
// SUBA
DECLARE_MIDFUNC(jnf_SUBA_b(W4 d, RR1 s));
DECLARE_MIDFUNC(jnf_SUBA_w(W4 d, RR2 s));
DECLARE_MIDFUNC(jnf_SUBA_l(W4 d, RR4 s));
// SUBX
DECLARE_MIDFUNC(jnf_SUBX(W4 d, RR4 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_b(W4 d, RR1 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_w(W4 d, RR2 s, RR4 v));
DECLARE_MIDFUNC(jff_SUBX_l(W4 d, RR4 s, RR4 v));
// SWAP
DECLARE_MIDFUNC (jnf_SWAP(RW4 d));
DECLARE_MIDFUNC (jff_SWAP(RW4 d));
// TST
DECLARE_MIDFUNC (jff_TST_b(RR1 s));
DECLARE_MIDFUNC (jff_TST_w(RR2 s));
DECLARE_MIDFUNC (jff_TST_l(RR4 s));

18
BasiliskII/src/uae_cpu/compiler/compemu_support.cpp
View File

@ -29,15 +29,17 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef USE_JIT
#ifdef UAE
#define writemem_special writemem
#define readmem_special readmem
#else
#if !FIXED_ADDRESSING
#error "Only Fixed Addressing is supported with the JIT Compiler"
#endif
//#if !FIXED_ADDRESSING
//#error "Only Fixed Addressing is supported with the JIT Compiler"
//#endif
#if defined(X86_ASSEMBLY) && !SAHF_SETO_PROFITABLE
#error "Only [LS]AHF scheme to [gs]et flags is supported with the JIT Compiler"
@ -3557,11 +3559,11 @@ void get_n_addr(int address, int dest, int tmp)
#ifdef NATMEM_OFFSET
if (canbang) {
#if FIXED_ADDRESSING
//#if FIXED_ADDRESSING
lea_l_brr(dest,address,MEMBaseDiff);
#else
# error "Only fixed adressing mode supported"
#endif
//#else
//# error "Only fixed adressing mode supported"
//#endif
forget_about(tmp);
(void) f;
(void) a;
@ -5486,3 +5488,5 @@ setjmpagain:
#endif
#endif /* JIT */
#endif

5
BasiliskII/src/uae_cpu/compiler/compstbla.cpp
View File

@ -1,5 +0,0 @@
/*
* compstbl.cpp must be compiled twice, once for the generator program
* and once for the actual executable
*/
#include "compstbl.cpp"

52
BasiliskII/src/uae_cpu/compiler/flags_arm.h
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@ -1,52 +0,0 @@
/*
* compiler/flags_arm.h - Native flags definitions for ARM
*
* Copyright (c) 2013 Jens Heitmann of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
*
* Adaptation for Basilisk II and improvements, copyright 2000-2002
* Gwenole Beauchesne
*
* Basilisk II (C) 1997-2002 Christian Bauer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef NATIVE_FLAGS_ARM_H
#define NATIVE_FLAGS_ARM_H
/* Native integer code conditions */
enum {
NATIVE_CC_EQ = 0,
NATIVE_CC_NE = 1,
NATIVE_CC_CS = 2,
NATIVE_CC_CC = 3,
NATIVE_CC_MI = 4,
NATIVE_CC_PL = 5,
NATIVE_CC_VS = 6,
NATIVE_CC_VC = 7,
NATIVE_CC_HI = 8,
NATIVE_CC_LS = 9,
NATIVE_CC_GE = 10,
NATIVE_CC_LT = 11,
NATIVE_CC_GT = 12,
NATIVE_CC_LE = 13,
NATIVE_CC_AL = 14
};
#endif /* NATIVE_FLAGS_ARM_H */

5082
BasiliskII/src/uae_cpu/compiler/gencomp_arm.c
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File diff suppressed because it is too large Load Diff

264
BasiliskII/src/uae_cpu/compiler/test_codegen_arm.c
View File

@ -1,264 +0,0 @@
/* Example of using sigaction() to setup a signal handler with 3 arguments
* including siginfo_t.
*/
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <string.h>
#include "flags_arm.h"
#include "codegen_arm.h"
#define TEST(c,ex,s) { c; if (opcode != ex) printf("(%s) Invalid opcode %x expected %x\n", s, opcode, ex); }
int opcode;
void emit_long(v) {
opcode = v;
}
int main (int argc, char *argv[])
{
TEST(MOV_ri(8, 15), 0xe3a0800f, "mov r8,#15");
TEST(MOV_rr(8,9), 0xe1a08009, "mov r8, r9");
TEST(MOV_rrLSLi(8,9,5), 0xe1a08289, "lsl r8, r9, #5");
TEST(MOV_rrLSLr(8,9,7), 0xe1a08719, "lsl r8, r9, r7");
TEST(MOV_rrLSRi(8,9,5), 0xe1a082a9, "lsr r8, r9, #5");
TEST(MOV_rrLSRr(8,9,7), 0xe1a08739, "lsr r8, r9, r7");
TEST(MOV_rrASRi(8,9,5), 0xe1a082c9, "asr r8, r9, #5");
TEST(MOV_rrASRr(8,9,7), 0xe1a08759, "asr r8, r9, r7");
TEST(MOV_rrRORi(8,9,5), 0xe1a082e9, "ror r8, r9, #5");
TEST(MOV_rrRORr(8,9,7), 0xe1a08779, "ror r8, r9, r7");
TEST(MOV_rrRRX(8,9), 0xe1a08069, "rrx r8, r9");
TEST(MOVS_ri(8, 15), 0xe3b0800f, "movs r8,#15");
TEST(MOVS_rr(8,9), 0xe1b08009, "movs r8, r9");
TEST(MOVS_rrLSLi(8,9,5), 0xe1b08289, "lsls r8, r9, #5");
TEST(MOVS_rrLSLr(8,9,7), 0xe1b08719, "lsls r8, r9, r7");
TEST(MOVS_rrLSRi(8,9,5), 0xe1b082a9, "lsrs r8, r9, #5");
TEST(MOVS_rrLSRr(8,9,7), 0xe1b08739, "lsrs r8, r9, r7");
TEST(MOVS_rrASRi(8,9,5), 0xe1b082c9, "asrs r8, r9, #5");
TEST(MOVS_rrASRr(8,9,7), 0xe1b08759, "asrs r8, r9, r7");
TEST(MOVS_rrRORi(8,9,5), 0xe1b082e9, "rors r8, r9, #5");
TEST(MOVS_rrRORr(8,9,7), 0xe1b08779, "rors r8, r9, r7");
TEST(MOVS_rrRRX(8,9), 0xe1b08069, "rrxs r8, r9");
TEST(MVN_ri(8, 15), 0xe3e0800f, "mvn r8,#15");
TEST(MVN_rr(8,9), 0xe1e08009, "mvn r8, r9");
TEST(MVN_rrLSLi(8,9,5), 0xe1e08289, "mvn r8, r9, lsl #5");
TEST(MVN_rrLSLr(8,9,7), 0xe1e08719, "mvn r8, r9, lsl r7");
TEST(MVN_rrLSRi(8,9,5), 0xe1e082a9, "mvn r8, r9, lsr #5");
TEST(MVN_rrLSRr(8,9,7), 0xe1e08739, "mvn r8, r9, lsr r7");
TEST(MVN_rrASRi(8,9,5), 0xe1e082c9, "mvn r8, r9, asr #5");
TEST(MVN_rrASRr(8,9,7), 0xe1e08759, "mvn r8, r9, asr r7");
TEST(MVN_rrRORi(8,9,5), 0xe1e082e9, "mvn r8, r9, ror #5");
TEST(MVN_rrRORr(8,9,7), 0xe1e08779, "mvn r8, r9, ror r7");
TEST(MVN_rrRRX(8,9), 0xe1e08069, "mvn r8, r9, rrx");
TEST(CMP_ri(8, 15), 0xe358000f, "cmp r8,#15");
TEST(CMP_rr(8,9), 0xe1580009, "cmp r8, r9");
TEST(CMP_rrLSLi(8,9,5), 0xe1580289, "cmp r8, r9, #5");
TEST(CMP_rrLSLr(8,9,7), 0xe1580719, "cmp r8, r9, r7");
TEST(CMP_rrLSRi(8,9,5), 0xe15802a9, "cmp r8, r9, #5");
TEST(CMP_rrLSRr(8,9,7), 0xe1580739, "cmp r8, r9, r7");
TEST(CMP_rrASRi(8,9,5), 0xe15802c9, "cmp r8, r9, #5");
TEST(CMP_rrASRr(8,9,7), 0xe1580759, "cmp r8, r9, r7");
TEST(CMP_rrRORi(8,9,5), 0xe15802e9, "cmp r8, r9, #5");
TEST(CMP_rrRORr(8,9,7), 0xe1580779, "cmp r8, r9, r7");
TEST(CMP_rrRRX(8,9), 0xe1580069, "cmp r8, r9");
TEST(CMP_ri(8, 0x81), 0xe3580081, "cmp r8,#0x81");
TEST(CMP_ri(8, 0x204), 0xe3580f81, "cmp r8,#0x204");
TEST(CMP_ri(8, 0x810), 0xe3580e81, "cmp r8,#0x8100");
TEST(CMP_ri(8, 0x2040), 0xe3580d81, "cmp r8,#0x2040");
TEST(CMP_ri(8, 0x8100), 0xe3580c81, "cmp r8,#0x8100");
TEST(CMP_ri(8, 0x20400), 0xe3580b81, "cmp r8,#0x20400");
TEST(CMP_ri(8, 0x81000), 0xe3580a81, "cmp r8,#0x81000");
TEST(CMP_ri(8, 0x204000), 0xe3580981, "cmp r8,#0x204000");
TEST(CMP_ri(8, 0x810000), 0xe3580881, "cmp r8,#0x810000");
TEST(CMP_ri(8, 0x2040000), 0xe3580781, "cmp r8,#0x2040000");
TEST(CMP_ri(8, 0x8100000), 0xe3580681, "cmp r8,#0x8100000");
TEST(CMP_ri(8, 0x20400000), 0xe3580581, "cmp r8,#0x20400000");
TEST(CMP_ri(8, 0x81000000), 0xe3580481, "cmp r8,#0x81000000");
TEST(CMP_ri(8, 0x04000002), 0xe3580381, "cmp r8,#0x04000002");
TEST(CMP_ri(8, 0x10000008), 0xe3580281, "cmp r8,#0x10000008");
TEST(CMP_ri(8, 0x40000020), 0xe3580181, "cmp r8,#0x40000020");
TEST(CMP_ri(8, 0x1200), 0xe3580c12, "cmp r8,#0x1200");
TEST(CMP_ri(8, 0x120000), 0xe3580812, "cmp r8,#0x120000");
TEST(CMP_ri(8, 0x12000000), 0xe3580412, "cmp r8,#0x12000000");
TEST(BEQ_i(5), 0x0a000005, "beq #5");
TEST(BNE_i(5), 0x1a000005, "bne #5");
TEST(BCS_i(5), 0x2a000005, "bcs #5");
TEST(BCC_i(5), 0x3a000005, "bcc #5");
TEST(BMI_i(5), 0x4a000005, "bmi #5");
TEST(BPL_i(5), 0x5a000005, "bpl #5");
TEST(BVS_i(5), 0x6a000005, "bvs #5");
TEST(BVC_i(5), 0x7a000005, "bvc #5");
TEST(BHI_i(5), 0x8a000005, "bhi #5");
TEST(BLS_i(5), 0x9a000005, "bls #5");
TEST(BGE_i(5), 0xaa000005, "bge #5");
TEST(BLT_i(5), 0xba000005, "blt #5");
TEST(BGT_i(5), 0xca000005, "bgt #5");
TEST(BLE_i(5), 0xda000005, "ble #5");
TEST(B_i(5), 0xea000005, "b #5");
TEST(BL_i(5), 0xeb000005, "bl #5");
TEST(BLX_r(8), 0xe12fff38, "blx r8");
TEST(BX_r(8), 0xe12fff18, "bx r8");
TEST(EOR_rri(6, 8, 15), 0xe228600f, "eor r6, r8,#15");
TEST(EOR_rrr(6, 8,9), 0xe0286009, "eor r6, r8, r9");
TEST(EOR_rrrLSLi(6,8,9,5), 0xe0286289, "eor r6, r8, r9, lsl #5");
TEST(EOR_rrrLSLr(6,8,9,7), 0xe0286719, "eor r6, r8, r9, lsl r7");
TEST(EOR_rrrLSRi(6,8,9,5), 0xe02862a9, "eor r6, r8, r9, lsr #5");
TEST(EOR_rrrLSRr(6,8,9,7), 0xe0286739, "eor r6, r8, r9, lsr r7");
TEST(EOR_rrrASRi(6,8,9,5), 0xe02862c9, "eor r6, r8, r9, asr #5");
TEST(EOR_rrrASRr(6,8,9,7), 0xe0286759, "eor r6, r8, r9, asr r7");
TEST(EOR_rrrRORi(6,8,9,5), 0xe02862e9, "eor r6, r8, r9, ror #5");
TEST(EOR_rrrRORr(6,8,9,7), 0xe0286779, "eor r6, r8, r9, ror r7");
TEST(EOR_rrrRRX(6,8,9), 0xe0286069, "eor r6, r8, r9, rrx");
TEST(EORS_rri(6, 8, 15), 0xe238600f, "eors r6, r8,#15");
TEST(EORS_rrr(6, 8,9), 0xe0386009, "eors r6, r8, r9");
TEST(EORS_rrrLSLi(6,8,9,5), 0xe0386289, "eors r6, r8, r9, lsl #5");
TEST(EORS_rrrLSLr(6,8,9,7), 0xe0386719, "eors r6, r8, r9, lsr r7");
TEST(EORS_rrrLSRi(6,8,9,5), 0xe03862a9, "eors r6, r8, r9, lsr #5");
TEST(EORS_rrrLSRr(6,8,9,7), 0xe0386739, "eors r6, r8, r9, lsr r7");
TEST(EORS_rrrASRi(6,8,9,5), 0xe03862c9, "eors r6, r8, r9, asr #5");
TEST(EORS_rrrASRr(6,8,9,7), 0xe0386759, "eors r6, r8, r9, asr r7");
TEST(EORS_rrrRORi(6,8,9,5), 0xe03862e9, "eors r6, r8, r9, ror #5");
TEST(EORS_rrrRORr(6,8,9,7), 0xe0386779, "eors r6, r8, r9, ror r7");
TEST(EORS_rrrRRX(6,8,9), 0xe0386069, "eors r6, r8, r9, rrx");
TEST(MRS_CPSR(6), 0xe10f6000, "mrs r6, CPSR");
TEST(MRS_SPSR(6), 0xe14f6000, "mrs r6, SPSR");
TEST(MSR_CPSR_i(5), 0xe329f005, "msr CPSR_fc, #5");
TEST(MSR_CPSR_r(5), 0xe129f005, "msr CPSR_fc, r5");
TEST(MSR_CPSRf_i(5), 0xe328f005, "msr CPSR_f, #5");
TEST(MSR_CPSRf_r(5), 0xe128f005, "msr CPSR_f, r5");
TEST(MSR_CPSRc_i(5), 0xe321f005, "msr CPSR_c, #5");
TEST(MSR_CPSRc_r(5), 0xe121f005, "msr CPSR_c, r5");
TEST(PUSH(6), 0xe92d0040, "push {r6}");
TEST(POP(6), 0xe8bd0040, "pop {r6}");
TEST(BIC_rri(0, 0, 0x9f000000), 0xe3c0049f, "bic r0, r0, #0x9f000000");
TEST(BIC_rri(2, 3, 0xff00), 0xe3c32cff, "bic r2, r3, #0xff00");
TEST(BIC_rri(3, 4, 0xff), 0xe3c430ff, "bic r3, r4, #0xff");
TEST(ORR_rrrLSRi(0, 1, 2, 16), 0xe1810822, "orr r0, r1, r2, lsr #16");
TEST(ORR_rrrLSRi(0, 1, 2, 24), 0xe1810c22, "orr r0, r1, r2, lsr #24");
TEST(LDR_rR(8, 9), 0xe5998000, "ldr r8, [r9]");
TEST(LDR_rRI(8, 9, 4), 0xe5998004, "ldr r8, [r9, #4]");
TEST(LDR_rRi(8, 9, 4), 0xe5198004, "ldr r8, [r9, #-4]");
TEST(LDR_rRR(8, 9, 7), 0xe7998007, "ldr r8, [r9, r7]");
TEST(LDR_rRr(8, 9, 7), 0xe7198007, "ldr r8, [r9, -r7]");
TEST(LDR_rRR_LSLi(8, 9, 7, 5), 0xe7998287, "ldr r8, [r9, r7, lsl #5]");
TEST(LDR_rRr_LSLi(8, 9, 7, 5), 0xe7198287, "ldr r8, [r9, -r7, lsl #5]");
TEST(LDR_rRR_LSRi(8, 9, 7, 5), 0xe79982a7, "ldr r8, [r9, r7, lsr #5]");
TEST(LDR_rRr_LSRi(8, 9, 7, 5), 0xe71982a7, "ldr r8, [r9, -r7, lsr #5]");
TEST(LDR_rRR_ASRi(8, 9, 7, 5), 0xe79982c7, "ldr r8, [r9, r7, asr #5]");
TEST(LDR_rRr_ASRi(8, 9, 7, 5), 0xe71982c7, "ldr r8, [r9, -r7, asr #5]");
TEST(LDR_rRR_RORi(8, 9, 7, 5), 0xe79982e7, "ldr r8, [r9, r7, ror #5]");
TEST(LDR_rRr_RORi(8, 9, 7, 5), 0xe71982e7, "ldr r8, [r9, -r7, ror #5]");
TEST(LDR_rRR_RRX(8, 9, 7), 0xe7998067, "ldr r8, [r9, r7, rrx]");
TEST(LDR_rRr_RRX(8, 9, 7), 0xe7198067, "ldr r8, [r9, -r7, rrx]");
TEST(LDRB_rR(8, 9), 0xe5d98000, "ldrb r8, [r9]");
TEST(LDRB_rRI(8, 9, 4), 0xe5d98004, "ldrb r8, [r9, #4]");
TEST(LDRB_rRi(8, 9, 4), 0xe5598004, "ldrb r8, [r9, #-4]");
TEST(LDRB_rRR(8, 9, 7), 0xe7d98007, "ldrb r8, [r9, r7]");
TEST(LDRB_rRr(8, 9, 7), 0xe7598007, "ldrb r8, [r9, -r7]");
TEST(LDRB_rRR_LSLi(8, 9, 7, 5), 0xe7d98287, "ldrb r8, [r9, r7, lsl #5]");
TEST(LDRB_rRr_LSLi(8, 9, 7, 5), 0xe7598287, "ldrb r8, [r9, -r7, lsl #5]");
TEST(LDRB_rRR_LSRi(8, 9, 7, 5), 0xe7d982a7, "ldrb r8, [r9, r7, lsr #5]");
TEST(LDRB_rRr_LSRi(8, 9, 7, 5), 0xe75982a7, "ldrb r8, [r9, -r7, lsr #5]");
TEST(LDRB_rRR_ASRi(8, 9, 7, 5), 0xe7d982c7, "ldrb r8, [r9, r7, asr #5]");
TEST(LDRB_rRr_ASRi(8, 9, 7, 5), 0xe75982c7, "ldrb r8, [r9, -r7, asr #5]");
TEST(LDRB_rRR_RORi(8, 9, 7, 5), 0xe7d982e7, "ldrb r8, [r9, r7, ror #5]");
TEST(LDRB_rRr_RORi(8, 9, 7, 5), 0xe75982e7, "ldrb r8, [r9, -r7, ror #5]");
TEST(LDRB_rRR_RRX(8, 9, 7), 0xe7d98067, "ldrb r8, [r9, r7, rrx]");
TEST(LDRB_rRr_RRX(8, 9, 7), 0xe7598067, "ldrb r8, [r9, -r7, rrx]");
TEST(LDRSB_rR(8, 9), 0xe1d980d0, "ldrsb r8, [r9]");
TEST(LDRSB_rRI(8, 9, 4), 0xe1d980d4, "ldrsb r8, [r9, #4]");
TEST(LDRSB_rRi(8, 9, 4), 0xe15980d4, "ldrsb r8, [r9, #-4]");
TEST(LDRSB_rRR(8, 9, 7), 0xe19980d7, "ldrsb r8, [r9, r7]");
TEST(LDRSB_rRr(8, 9, 7), 0xe11980d7, "ldrsb r8, [r9, -r7]");
TEST(LDRSH_rR(8, 9), 0xe1d980f0, "ldrsh r8, [r9]");
TEST(LDRSH_rRI(8, 9, 4), 0xe1d980f4, "ldrsh r8, [r9, #4]");
TEST(LDRSH_rRi(8, 9, 4), 0xe15980f4, "ldrsh r8, [r9, #-4]");
TEST(LDRSH_rRR(8, 9, 7), 0xe19980f7, "ldrsh r8, [r9, r7]");
TEST(LDRSH_rRr(8, 9, 7), 0xe11980f7, "ldrsh r8, [r9, -r7]");
TEST(LDRH_rR(8, 9), 0xe1d980b0, "ldrh r8, [r9]");
TEST(LDRH_rRI(8, 9, 4), 0xe1d980b4, "ldrh r8, [r9, #4]");
TEST(LDRH_rRi(8, 9, 4), 0xe15980b4, "ldrh r8, [r9, #-4]");
TEST(LDRH_rRR(8, 9, 7), 0xe19980b7, "ldrh r8, [r9, r7]");
TEST(LDRH_rRr(8, 9, 7), 0xe11980b7, "ldrh r8, [r9, -r7]");
TEST(STR_rRR(8,9,7), 0xe7898007, "str r8, [r9, r7]");
TEST(STR_rRr(8,9,7), 0xe7098007, "str r8, [r9, -r7]");
TEST(STRB_rR(5, 6), 0xe5c65000, "strb r5,[r6]");
TEST(STRH_rR(8, 9), 0xe1c980b0, "strh r8, [r9]");
TEST(STRH_rRI(8, 9, 4), 0xe1c980b4, "strh r8, [r9, #4]");
TEST(STRH_rRi(8, 9, 4), 0xe14980b4, "strh r8, [r9, #-4]");
TEST(STRH_rRR(8, 9, 7), 0xe18980b7, "strh r8, [r9, r7]");
TEST(STRH_rRr(8, 9, 7), 0xe10980b7, "strh r8, [r9, -r7]");
TEST(CLZ_rr(2, 3), 0xe16f2f13, "clz r2,r3");
TEST(REV_rr(2, 3), 0xe6bf2f33, "rev r2, r3");
TEST(REV16_rr(2, 3), 0xe6bf2fb3, "rev16 r2, r3");
TEST(REVSH_rr(2, 3), 0xe6ff2fb3, "revsh r2, r3");
TEST(SXTB_rr(2,3), 0xe6af2073, "sxtb r2,r3");
TEST(SXTB_rr(3,4), 0xe6af3074, "sxtb r3,r4");
TEST(SXTB_rr_ROR8(2,3), 0xe6af2473, "sxtb r2, r3, ror #8");
TEST(SXTB_rr_ROR16(2,3), 0xe6af2873, "sxtb r2, r3, ror #16");
TEST(SXTB_rr_ROR24(2,3), 0xe6af2c73, "sxtb r2, r3, ror #24");
TEST(SXTH_rr(2,3), 0xe6bf2073, "sxth r2, r3");
TEST(SXTH_rr_ROR8(2,3), 0xe6bf2473, "sxth r2, r3, ror #8");
TEST(SXTH_rr_ROR16(2,3), 0xe6bf2873, "sxth r2, r3, ror #16");
TEST(SXTH_rr_ROR24(2,3), 0xe6bf2c73, "sxth r2, r3, ror #24");
TEST(UXTB_rr(2,3), 0xe6ef2073, "uxtb r2, r3");
TEST(UXTB_rr_ROR8(2,3), 0xe6ef2473, "uxtb r2, r3, ror #8");
TEST(UXTB_rr_ROR16(2,3), 0xe6ef2873, "uxtb r2, r3, ror #16");
TEST(UXTB_rr_ROR24(2,3), 0xe6ef2c73, "uxtb r2, r3, ror #24");
TEST(UXTH_rr(2,3), 0xe6ff2073, "uxth r2, r3");
TEST(UXTH_rr_ROR8(2,3), 0xe6ff2473, "uxth r2, r3, ror #8");
TEST(UXTH_rr_ROR16(2,3), 0xe6ff2873, "uxth r2, r3, ror #16");
TEST(UXTH_rr_ROR24(2,3), 0xe6ff2c73, "uxth r2, r3, ror #24");
TEST(REV_rr(2,3), 0xe6bf2f33, "rev r2, r3");
TEST(REV16_rr(2,3), 0xe6bf2fb3, "rev16 r2, r3");
TEST(REVSH_rr(2,3), 0xe6ff2fb3, "revsh r2, r3");
TEST(CC_MOV_ri(NATIVE_CC_CS, 4,1), 0x23a04001, "movcs r4, #1");
TEST(CC_MOV_ri(NATIVE_CC_CC, 4,1), 0x33a04001, "movcc r4, #1");
int imm = 0x9f;
TEST(ADDS_rri(0, 0, imm << 24), 0xe290049f, "adds r0, r0, 0x9f000000");
TEST(PKHBT_rrr(1, 2, 3), 0xe6821013, "pkhbt r1,r2,r3");
TEST(MVN_ri8(1,2), 0xe3e01002, "mvn r1,#2");
TEST(ORR_rri8RORi(1,2,0x12,24), 0xe3821c12, "orr r1, r2, #0x1200");
TEST(PKHTB_rrrASRi(1, 2, 3, 4), 0xe6821253, "pkhtb r1,r2,r3,ASR #4");
TEST(PKHBT_rrrLSLi(1, 2, 3, 4), 0xe6821213, "pkhbt r1,r2,r3,LSL #4");
TEST(MUL_rrr(1,2,3), 0xe0010392, "mul r1, r2, r3");
TEST(MULS_rrr(1,2,3), 0xe0110392, "muls r1, r2, r3");
}

1008
BasiliskII/src/uae_cpu/compiler/test_codegen_x86.cpp
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File diff suppressed because it is too large Load Diff

5
BasiliskII/src/uae_cpu/cpudefsa.cpp
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@ -1,5 +0,0 @@
/*
* cpudefs.cpp must be compiled twice, once for the generator program
* and once for the actual executable
*/
#include "cpudefs.cpp"

2
BasiliskII/src/uae_cpu/cpuemu1.cpp
View File

@ -1,2 +0,0 @@
#define PART_1
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu1_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_1
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu2.cpp
View File

@ -1,2 +0,0 @@
#define PART_2
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu2_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_2
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu3.cpp
View File

@ -1,2 +0,0 @@
#define PART_3
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu3_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_3
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu4.cpp
View File

@ -1,2 +0,0 @@
#define PART_4
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu4_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_4
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu5.cpp
View File

@ -1,2 +0,0 @@
#define PART_5
#include "cpuemu.cpp"

4
BasiliskII/src/uae_cpu/cpuemu5_nf.cpp
View File

@ -1,4 +0,0 @@
#define NOFLAGS 1
#define PART_5
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu6.cpp
View File

@ -1,2 +0,0 @@
#define PART_6
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu6_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_6
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu7.cpp
View File

@ -1,2 +0,0 @@
#define PART_7
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu7_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_7
#include "cpuemu.cpp"

2
BasiliskII/src/uae_cpu/cpuemu8.cpp
View File

@ -1,2 +0,0 @@
#define PART_8
#include "cpuemu.cpp"

3
BasiliskII/src/uae_cpu/cpuemu8_nf.cpp
View File

@ -1,3 +0,0 @@
#define NOFLAGS 1
#define PART_8
#include "cpuemu.cpp"

5
BasiliskII/src/uae_cpu/cpufunctbla.cpp
View File

@ -1,5 +0,0 @@
/*
* cpufunctbl.cpp must be compiled twice, once for the generator program
* and once for the actual executable
*/
#include "cpufunctbl.cpp"

1096
BasiliskII/src/uae_cpu/cpummu.cpp
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File diff suppressed because it is too large Load Diff

312
BasiliskII/src/uae_cpu/cpuopti.c
View File

@ -1,312 +0,0 @@
/*
* UAE - The Un*x Amiga Emulator
*
* cpuopti.c - Small optimizer for cpu*.s files
* Based on work by Tauno Taipaleenmaki
*
* Copyright 1996 Bernd Schmidt
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <ctype.h>
#include <stdio.h>
#include <string.h>
#include "sysdeps.h"
struct line {
struct line *next, *prev;
int delet;
char *data;
};
struct func {
struct line *first_line, *last_line;
int initial_offset;
};
static void oops(void)
{
fprintf(stderr, "Don't know how to optimize this file.\n");
exit(1);
}
static char * match(struct line *l, const char *m)
{
char *str = l->data;
int len = strlen(m);
while (isspace(*str))
str++;
if (strncmp(str, m, len) != 0)
return NULL;
return str + len;
}
static int insn_references_reg (struct line *l, char *reg)
{
if (reg[0] != 'e') {
fprintf(stderr, "Unknown register?!?\n");
exit(1);
}
if (strstr (l->data, reg) != 0)
return 1;
if (strstr (l->data, reg+1) != 0)
return 1;
if (strcmp (reg, "eax") == 0
&& (strstr (l->data, "%al") != 0 || strstr (l->data, "%ah") != 0))
return 1;
if (strcmp (reg, "ebx") == 0
&& (strstr (l->data, "%bl") != 0 || strstr (l->data, "%bh") != 0))
return 1;
if (strcmp (reg, "ecx") == 0
&& (strstr (l->data, "%cl") != 0 || strstr (l->data, "%ch") != 0))
return 1;
if (strcmp (reg, "edx") == 0
&& (strstr (l->data, "%dl") != 0 || strstr (l->data, "%dh") != 0))
return 1;
return 0;
}
static void do_function(struct func *f)
{
int v;
int pops_at_end = 0;
struct line *l, *l1, *fl, *l2;
char *s, *s2;
int in_pop_area = 1;
f->initial_offset = 0;
l = f->last_line;
fl = f->first_line;
if (match(l,".LFE"))
l = l->prev;
if (!match(l,"ret"))
oops();
while (!match(fl, "op_"))
fl = fl->next;
fl = fl->next;
/* Try reordering the insns at the end of the function so that the
* pops are all at the end. */
l2 = l->prev;
/* Tolerate one stack adjustment */
if (match (l2, "addl $") && strstr(l2->data, "esp") != 0)
l2 = l2->prev;
for (;;) {
char *forbidden_reg;
struct line *l3, *l4;
while (match (l2, "popl %"))
l2 = l2->prev;
l3 = l2;
for (;;) {
forbidden_reg = match (l3, "popl %");
if (forbidden_reg)
break;
if (l3 == fl)
goto reordered;
/* Jumps and labels put an end to our attempts... */
if (strstr (l3->data, ".L") != 0)
goto reordered;
/* Likewise accesses to the stack pointer... */
if (strstr (l3->data, "esp") != 0)
goto reordered;
/* Function calls... */
if (strstr (l3->data, "call") != 0)
goto reordered;
l3 = l3->prev;
}
if (l3 == l2)
exit(1);
for (l4 = l2; l4 != l3; l4 = l4->prev) {
/* The register may not be referenced by any of the insns that we
* move the popl past */
if (insn_references_reg (l4, forbidden_reg))
goto reordered;
}
l3->prev->next = l3->next;
l3->next->prev = l3->prev;
l2->next->prev = l3;
l3->next = l2->next;
l2->next = l3;
l3->prev = l2;
}
reordered:
l = l->prev;
s = match (l, "addl $");
s2 = match (fl, "subl $");
l1 = l;
if (s == 0) {
char *t = match (l, "popl %");
if (t != 0 && (strcmp (t, "ecx") == 0 || strcmp (t, "edx") == 0)) {
s = "4,%esp";
l = l->prev;
t = match (l, "popl %");
if (t != 0 && (strcmp (t, "ecx") == 0 || strcmp (t, "edx") == 0)) {
s = "8,%esp";
l = l->prev;
}
}
} else {
l = l->prev;
}
if (s && s2) {
int v = 0;
if (strcmp (s, s2) != 0) {
fprintf (stderr, "Stack adjustment not matching.\n");
return;
}
while (isdigit(*s)) {
v = v * 10 + (*s) - '0';
s++;
}
if (strcmp (s, ",%esp") != 0) {
fprintf (stderr, "Not adjusting the stack pointer.\n");
return;
}
f->initial_offset = v;
fl->delet = 3;
fl = fl->next;
l1->delet = 2;
l1 = l1->prev;
while (l1 != l) {
l1->delet = 1;
l1 = l1->prev;
}
}
while (in_pop_area) {
char *popm, *pushm;
popm = match (l, "popl %");
pushm = match (fl, "pushl %");
if (popm && pushm && strcmp(pushm, popm) == 0) {
pops_at_end++;
fl->delet = l->delet = 1;
} else
in_pop_area = 0;
l = l->prev;
fl = fl->next;
}
if (f->initial_offset)
f->initial_offset += 4 * pops_at_end;
}
static void output_function(struct func *f)
{
struct line *l = f->first_line;
while (l) {
switch (l->delet) {
case 1:
break;
case 0:
printf("%s\n", l->data);
break;
case 2:
if (f->initial_offset)
printf("\taddl $%d,%%esp\n", f->initial_offset);
break;
case 3:
if (f->initial_offset)
printf("\tsubl $%d,%%esp\n", f->initial_offset);
break;
}
l = l->next;
}
}
int main(int argc, char **argv)
{
FILE *infile = stdin;
char tmp[4096];
#ifdef __mc68000__
if(system("perl machdep/cpuopti")==-1) {
perror("perl machdep/cpuopti");
return 10;
} else return 0;
#endif
/* For debugging... */
if (argc == 2)
infile = fopen (argv[1], "r");
for(;;) {
char *s;
if ((fgets(tmp, 4095, infile)) == NULL)
break;
s = strchr (tmp, '\n');
if (s != NULL)
*s = 0;
if (strncmp(tmp, ".globl op_", 10) == 0) {
struct line *first_line = NULL, *prev = NULL;
struct line **nextp = &first_line;
struct func f;
int nr_rets = 0;
int can_opt = 1;
do {
struct line *current;
if (strcmp (tmp, "#APP") != 0 && strcmp (tmp, "#NO_APP") != 0) {
current = *nextp = (struct line *)malloc(sizeof (struct line));
nextp = &current->next;
current->prev = prev; prev = current;
current->next = NULL;
current->delet = 0;
current->data = strdup (tmp);
if (match (current, "movl %esp,%ebp") || match (current, "enter")) {
fprintf (stderr, "GCC failed to eliminate fp: %s\n", first_line->data);
can_opt = 0;
}
if (match (current, "ret"))
nr_rets++;
}
if ((fgets(tmp, 4095, infile)) == NULL)
oops();
s = strchr (tmp, '\n');
if (s != NULL)
*s = 0;
} while (strncmp (tmp,".Lfe", 4) != 0);
f.first_line = first_line;
f.last_line = prev;
if (nr_rets == 1 && can_opt)
do_function(&f);
/*else
fprintf(stderr, "Too many RET instructions: %s\n", first_line->data);*/
output_function(&f);
}
printf("%s\n", tmp);
}
return 0;
}

2
BasiliskII/src/uae_cpu/cpustbl_nf.cpp
View File

@ -1,2 +0,0 @@
#define NOFLAGS 1
#include "cpustbl.cpp"

5
BasiliskII/src/uae_cpu/cpustbla.cpp
View File

@ -1,5 +0,0 @@
/*
* cpustbl.cpp must be compiled twice, once for the generator program
* and once for the actual executable
*/
#include "cpustbl.cpp"

82
BasiliskII/src/uae_cpu/debug.cpp
View File

@ -1,82 +0,0 @@
/*
* debug.cpp - CPU debugger
*
* Copyright (c) 2001-2010 Milan Jurik of ARAnyM dev team (see AUTHORS)
*
* Inspired by Bernd Schmidt's UAE
*
* This file is part of the ARAnyM project which builds a new and powerful
* TOS/FreeMiNT compatible virtual machine running on almost any hardware.
*
* ARAnyM is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* ARAnyM is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ARAnyM; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* UAE - The Un*x Amiga Emulator
*
* Debugger
*
* (c) 1995 Bernd Schmidt
*
*/
#include "sysdeps.h"
#include "memory.h"
#include "newcpu.h"
#include "debug.h"
#include "input.h"
#include "cpu_emulation.h"
#include "main.h"
static int debugger_active = 0;
int debugging = 0;
int irqindebug = 0;
int ignore_irq = 0;
void activate_debugger (void)
{
#ifdef DEBUGGER
ndebug::do_skip = false;
#endif
debugger_active = 1;
SPCFLAGS_SET( SPCFLAG_BRK );
debugging = 1;
/* use_debugger = 1; */
}
void deactivate_debugger(void)
{
debugging = 0;
debugger_active = 0;
}
void debug (void)
{
if (ignore_irq && regs.s && !regs.m ) {
SPCFLAGS_SET( SPCFLAG_BRK );
return;
}
#ifdef DEBUGGER
ndebug::run();
#endif
}
/*
vim:ts=4:sw=4:
*/

5
BasiliskII/src/uae_cpu/fpu/fpu_ieee.cpp
View File

@ -98,6 +98,9 @@
*/
#include "sysdeps.h"
#ifdef FPU_IEEE
#include <cstdio>
#include "memory.h"
#include "readcpu.h"
@ -2471,3 +2474,5 @@ PUBLIC void FFPU fpu_reset (void)
fpu_exit();
fpu_init(FPU is_integral);
}
#endif

5
BasiliskII/src/uae_cpu/fpu/fpu_mpfr.cpp
View File

@ -19,6 +19,9 @@
*/
#include "sysdeps.h"
#ifdef FPU_MPFR
#include <cstdio>
#include "memory.h"
#include "readcpu.h"
@ -2108,3 +2111,5 @@ uae_u32 fpu_get_fpcr(void)
{
return get_fpcr();
}
#endif

606
BasiliskII/src/uae_cpu/memory-uae.h
View File

@ -1,606 +0,0 @@
/*
* memory.h - memory management
*
* Copyright (c) 2001-2006 Milan Jurik of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* This file is part of the ARAnyM project which builds a new and powerful
* TOS/FreeMiNT compatible virtual machine running on almost any hardware.
*
* ARAnyM is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* ARAnyM is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ARAnyM; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* UAE - The Un*x Amiga Emulator
*
* memory management
*
* Copyright 1995 Bernd Schmidt
*/
#ifndef UAE_MEMORY_H
#define UAE_MEMORY_H
#include "sysdeps.h"
#include "string.h"
#include "hardware.h"
#include "parameters.h"
#include "registers.h"
#include "cpummu.h"
#include "readcpu.h"
# include <csetjmp>
// newcpu.h
extern void Exception (int, uaecptr);
#ifdef EXCEPTIONS_VIA_LONGJMP
extern JMP_BUF excep_env;
#define SAVE_EXCEPTION \
JMP_BUF excep_env_old; \
memcpy(excep_env_old, excep_env, sizeof(JMP_BUF))
#define RESTORE_EXCEPTION \
memcpy(excep_env, excep_env_old, sizeof(JMP_BUF))
#define TRY(var) int var = SETJMP(excep_env); if (!var)
#define CATCH(var) else
#define THROW(n) LONGJMP(excep_env, n)
#define THROW_AGAIN(var) LONGJMP(excep_env, var)
#define VOLATILE volatile
#else
struct m68k_exception {
int prb;
m68k_exception (int exc) : prb (exc) {}
operator int() { return prb; }
};
#define SAVE_EXCEPTION
#define RESTORE_EXCEPTION
#define TRY(var) try
#define CATCH(var) catch(m68k_exception var)
#define THROW(n) throw m68k_exception(n)
#define THROW_AGAIN(var) throw
#define VOLATILE
#endif /* EXCEPTIONS_VIA_LONGJMP */
extern int in_exception_2;
#define STRAM_END 0x0e00000UL // should be replaced by global ROMBase as soon as ROMBase will be a constant
#define ROM_END 0x0e80000UL // should be replaced by ROMBase + RealROMSize if we are going to work with larger TOS ROMs than 512 kilobytes
#define FastRAM_BEGIN 0x1000000UL // should be replaced by global FastRAMBase as soon as FastRAMBase will be a constant
#ifdef FixedSizeFastRAM
#define FastRAM_SIZE (FixedSizeFastRAM * 1024 * 1024)
#else
#define FastRAM_SIZE FastRAMSize
#endif
#ifdef FIXED_VIDEORAM
#define ARANYMVRAMSTART 0xf0000000UL
#endif
#define ARANYMVRAMSIZE 0x00100000 // should be a variable to protect VGA card offscreen memory
#ifdef FIXED_VIDEORAM
extern uintptr VMEMBaseDiff;
#else
extern uae_u32 VideoRAMBase;
#endif
#ifdef ARAM_PAGE_CHECK
extern uaecptr pc_page, read_page, write_page;
extern uintptr pc_offset, read_offset, write_offset;
# ifdef PROTECT2K
# define ARAM_PAGE_MASK 0x7ff
# else
# ifdef FULLMMU
# define ARAM_PAGE_MASK 0xfff
# else
# define ARAM_PAGE_MASK 0xfffff
# endif
# endif
#endif
extern uintptr MEMBaseDiff;
extern uintptr ROMBaseDiff;
extern uintptr FastRAMBaseDiff;
# define InitMEMBaseDiff(va, ra) (MEMBaseDiff = (uintptr)(va) - (uintptr)(ra))
# define InitROMBaseDiff(va, ra) (ROMBaseDiff = (uintptr)(va) - (uintptr)(ra))
# define InitFastRAMBaseDiff(va, ra) (FastRAMBaseDiff = (uintptr)(va) - (uintptr)(ra))
#ifdef FIXED_VIDEORAM
#define InitVMEMBaseDiff(va, ra) (VMEMBaseDiff = (uintptr)(va) - (uintptr)(ra))
#else
#define InitVMEMBaseDiff(va, ra) (ra = (uintptr)(va) + MEMBaseDiff)
#endif
extern "C" void breakpt(void);
static inline uae_u64 do_get_mem_quad(uae_u64 *a) {return SDL_SwapBE64(*a);}
static inline void do_put_mem_quad(uae_u64 *a, uae_u64 v) {*a = SDL_SwapBE64(v);}
#ifndef NOCHECKBOUNDARY
static ALWAYS_INLINE bool test_ram_boundary(uaecptr addr, int size, bool super, bool write)
{
if (addr <= (FastRAM_BEGIN + FastRAM_SIZE - size)) {
#ifdef PROTECT2K
// protect first 2kB of RAM - access in supervisor mode only
if (!super && addr < 0x00000800UL)
return false;
#endif
// check for write access to protected areas:
// - first two longwords of ST-RAM are non-writable (ROM shadow)
// - non-writable area between end of ST-RAM and begin of FastRAM
if (!write || addr >= FastRAM_BEGIN || (addr >= 8 && addr <= (STRAM_END - size)))
return true;
}
#ifdef FIXED_VIDEORAM
return addr >= ARANYMVRAMSTART && addr <= (ARANYMVRAMSTART + ARANYMVRAMSIZE - size);
#else
return addr >= VideoRAMBase && addr <= (VideoRAMBase + ARANYMVRAMSIZE - size);
#endif
}
/*
* "size" is the size of the memory access (byte = 1, word = 2, long = 4)
*/
static ALWAYS_INLINE void check_ram_boundary(uaecptr addr, int size, bool write)
{
if (test_ram_boundary(addr, size, regs.s, write))
return;
// D(bug("BUS ERROR %s at $%x\n", (write ? "writing" : "reading"), addr));
regs.mmu_fault_addr = addr;
regs.mmu_ssw = ((size & 3) << 5) | (write ? 0 : (1 << 8)); /* MMU_SW_RW */
breakpt();
THROW(2);
}
#else
static inline bool test_ram_boundary(uaecptr, int, bool, bool) { return 1; }
static inline void check_ram_boundary(uaecptr, int, bool) { }
#endif
#ifdef FIXED_VIDEORAM
# define do_get_real_address(a) ((uae_u8 *)(((uaecptr)(a) < ARANYMVRAMSTART) ? ((uaecptr)(a) + MEMBaseDiff) : ((uaecptr)(a) + VMEMBaseDiff)))
#else
# define do_get_real_address(a) ((uae_u8 *)((uintptr)(a) + MEMBaseDiff))
#endif
static inline uae_u8 *phys_get_real_address(uaecptr addr)
{
return do_get_real_address(addr);
}
#ifndef NOCHECKBOUNDARY
static inline bool phys_valid_address(uaecptr addr, bool write, int sz)
{
return test_ram_boundary(addr, sz, regs.s, write);
}
#else
static inline bool phys_valid_address(uaecptr, bool, int) { return true; }
#endif
static inline uae_u64 phys_get_quad(uaecptr addr)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ read_page) <= ARAM_PAGE_MASK))
return do_get_mem_quad((uae_u64*)(addr + read_offset));
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) return HWget_l(addr); /* TODO: must be HWget_q */
#endif
check_ram_boundary(addr, 8, false);
uae_u64 * const m = (uae_u64 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
read_page = addr;
read_offset = (uintptr)m - (uintptr)addr;
#endif
return do_get_mem_quad(m);
}
static inline uae_u32 phys_get_long(uaecptr addr)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ read_page) <= ARAM_PAGE_MASK))
return do_get_mem_long((uae_u32*)(addr + read_offset));
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) return HWget_l(addr);
#endif
check_ram_boundary(addr, 4, false);
uae_u32 * const m = (uae_u32 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
read_page = addr;
read_offset = (uintptr)m - (uintptr)addr;
#endif
return do_get_mem_long(m);
}
static inline uae_u32 phys_get_word(uaecptr addr)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ read_page) <= ARAM_PAGE_MASK))
return do_get_mem_word((uae_u16*)(addr + read_offset));
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) return HWget_w(addr);
#endif
check_ram_boundary(addr, 2, false);
uae_u16 * const m = (uae_u16 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
read_page = addr;
read_offset = (uintptr)m - (uintptr)addr;
#endif
return do_get_mem_word(m);
}
static inline uae_u32 phys_get_byte(uaecptr addr)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ read_page) <= ARAM_PAGE_MASK))
return do_get_mem_byte((uae_u8*)(addr + read_offset));
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) return HWget_b(addr);
#endif
check_ram_boundary(addr, 1, false);
uae_u8 * const m = (uae_u8 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
read_page = addr;
read_offset = (uintptr)m - (uintptr)addr;
#endif
return do_get_mem_byte(m);
}
static inline void phys_put_quad(uaecptr addr, uae_u64 l)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ write_page) <= ARAM_PAGE_MASK)) {
do_put_mem_quad((uae_u64*)(addr + write_offset), l);
return;
}
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) {
HWput_l(addr, l); /* TODO: must be HWput_q */
return;
}
#endif
check_ram_boundary(addr, 8, true);
uae_u64 * const m = (uae_u64 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
write_page = addr;
write_offset = (uintptr)m - (uintptr)addr;
#endif
do_put_mem_quad(m, l);
}
static inline void phys_put_long(uaecptr addr, uae_u32 l)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ write_page) <= ARAM_PAGE_MASK)) {
do_put_mem_long((uae_u32*)(addr + write_offset), l);
return;
}
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) {
HWput_l(addr, l);
return;
}
#endif
check_ram_boundary(addr, 4, true);
uae_u32 * const m = (uae_u32 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
write_page = addr;
write_offset = (uintptr)m - (uintptr)addr;
#endif
do_put_mem_long(m, l);
}
static inline void phys_put_word(uaecptr addr, uae_u32 w)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ write_page) <= ARAM_PAGE_MASK)) {
do_put_mem_word((uae_u16*)(addr + write_offset), w);
return;
}
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) {
HWput_w(addr, w);
return;
}
#endif
check_ram_boundary(addr, 2, true);
uae_u16 * const m = (uae_u16 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
write_page = addr;
write_offset = (uintptr)m - (uintptr)addr;
#endif
do_put_mem_word(m, w);
}
static inline void phys_put_byte(uaecptr addr, uae_u32 b)
{
#ifdef ARAM_PAGE_CHECK
if (((addr ^ write_page) <= ARAM_PAGE_MASK)) {
do_put_mem_byte((uae_u8*)(addr + write_offset), b);
return;
}
#endif
#ifndef HW_SIGSEGV
addr = addr < 0xff000000 ? addr : addr & 0x00ffffff;
if ((addr & 0xfff00000) == 0x00f00000) {
HWput_b(addr, b);
return;
}
#endif
check_ram_boundary(addr, 1, true);
uae_u8 * const m = (uae_u8 *)phys_get_real_address(addr);
#ifdef ARAM_PAGE_CHECK
write_page = addr;
write_offset = (uintptr)m - (uintptr)addr;
#endif
do_put_mem_byte(m, b);
}
#ifdef FULLMMU
static ALWAYS_INLINE bool is_unaligned(uaecptr addr, int size)
{
return unlikely((addr & (size - 1)) && (addr ^ (addr + size - 1)) & 0x1000);
}
static ALWAYS_INLINE uae_u8 *mmu_get_real_address(uaecptr addr, struct mmu_atc_line *cl)
{
return do_get_real_address(cl->phys + addr);
}
static ALWAYS_INLINE uae_u32 mmu_get_quad(uaecptr addr, int data)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 0, &cl)))
return do_get_mem_quad((uae_u64 *)mmu_get_real_address(addr, cl));
return mmu_get_quad_slow(addr, regs.s, data, cl);
}
static ALWAYS_INLINE uae_u64 get_quad(uaecptr addr)
{
return mmu_get_quad(addr, 1);
}
static ALWAYS_INLINE uae_u32 mmu_get_long(uaecptr addr, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 0, &cl)))
return do_get_mem_long((uae_u32 *)mmu_get_real_address(addr, cl));
return mmu_get_long_slow(addr, regs.s, data, size, cl);
}
static ALWAYS_INLINE uae_u32 get_long(uaecptr addr)
{
if (unlikely(is_unaligned(addr, 4)))
return mmu_get_long_unaligned(addr, 1);
return mmu_get_long(addr, 1, sz_long);
}
static ALWAYS_INLINE uae_u16 mmu_get_word(uaecptr addr, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 0, &cl)))
return do_get_mem_word((uae_u16 *)mmu_get_real_address(addr, cl));
return mmu_get_word_slow(addr, regs.s, data, size, cl);
}
static ALWAYS_INLINE uae_u16 get_word(uaecptr addr)
{
if (unlikely(is_unaligned(addr, 2)))
return mmu_get_word_unaligned(addr, 1);
return mmu_get_word(addr, 1, sz_word);
}
static ALWAYS_INLINE uae_u8 mmu_get_byte(uaecptr addr, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 0, &cl)))
return do_get_mem_byte((uae_u8 *)mmu_get_real_address(addr, cl));
return mmu_get_byte_slow(addr, regs.s, data, size, cl);
}
static ALWAYS_INLINE uae_u8 get_byte(uaecptr addr)
{
return mmu_get_byte(addr, 1, sz_byte);
}
static ALWAYS_INLINE void mmu_put_quad(uaecptr addr, uae_u64 val, int data)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 1, &cl)))
do_put_mem_quad((uae_u64 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_quad_slow(addr, val, regs.s, data, cl);
}
static ALWAYS_INLINE void put_quad(uaecptr addr, uae_u32 val)
{
mmu_put_quad(addr, val, 1);
}
static ALWAYS_INLINE void mmu_put_long(uaecptr addr, uae_u32 val, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 1, &cl)))
do_put_mem_long((uae_u32 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_long_slow(addr, val, regs.s, data, size, cl);
}
static ALWAYS_INLINE void put_long(uaecptr addr, uae_u32 val)
{
if (unlikely(is_unaligned(addr, 4)))
mmu_put_long_unaligned(addr, val, 1);
else
mmu_put_long(addr, val, 1, sz_long);
}
static ALWAYS_INLINE void mmu_put_word(uaecptr addr, uae_u16 val, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 1, &cl)))
do_put_mem_word((uae_u16 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_word_slow(addr, val, regs.s, data, size, cl);
}
static ALWAYS_INLINE void put_word(uaecptr addr, uae_u16 val)
{
if (unlikely(is_unaligned(addr, 2)))
mmu_put_word_unaligned(addr, val, 1);
else
mmu_put_word(addr, val, 1, sz_word);
}
static ALWAYS_INLINE void mmu_put_byte(uaecptr addr, uae_u8 val, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_lookup(addr, data, 1, &cl)))
do_put_mem_byte((uae_u8 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_byte_slow(addr, val, regs.s, data, size, cl);
}
static ALWAYS_INLINE void put_byte(uaecptr addr, uae_u8 val)
{
mmu_put_byte(addr, val, 1, sz_byte);
}
static inline uae_u8 *get_real_address(uaecptr addr, int write, int sz)
{
(void)sz;
return phys_get_real_address(mmu_translate(addr, regs.s, 1, write));
}
static ALWAYS_INLINE uae_u32 mmu_get_user_long(uaecptr addr, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 0, &cl)))
return do_get_mem_long((uae_u32 *)mmu_get_real_address(addr, cl));
return mmu_get_long_slow(addr, super, data, size, cl);
}
static ALWAYS_INLINE uae_u16 mmu_get_user_word(uaecptr addr, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 0, &cl)))
return do_get_mem_word((uae_u16 *)mmu_get_real_address(addr, cl));
return mmu_get_word_slow(addr, super, data, size, cl);
}
static ALWAYS_INLINE uae_u8 mmu_get_user_byte(uaecptr addr, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 0, &cl)))
return do_get_mem_byte((uae_u8 *)mmu_get_real_address(addr, cl));
return mmu_get_byte_slow(addr, super, data, size, cl);
}
static ALWAYS_INLINE void mmu_put_user_long(uaecptr addr, uae_u32 val, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 1, &cl)))
do_put_mem_long((uae_u32 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_long_slow(addr, val, super, data, size, cl);
}
static ALWAYS_INLINE void mmu_put_user_word(uaecptr addr, uae_u16 val, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 1, &cl)))
do_put_mem_word((uae_u16 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_word_slow(addr, val, super, data, size, cl);
}
static ALWAYS_INLINE void mmu_put_user_byte(uaecptr addr, uae_u8 val, int super, int data, int size)
{
struct mmu_atc_line *cl;
if (likely(mmu_user_lookup(addr, super, data, 1, &cl)))
do_put_mem_byte((uae_u8 *)mmu_get_real_address(addr, cl), val);
else
mmu_put_byte_slow(addr, val, super, data, size, cl);
}
static inline bool valid_address(uaecptr addr, bool write, int sz)
{
SAVE_EXCEPTION;
TRY(prb) {
(void)sz;
check_ram_boundary(mmu_translate(addr, regs.s, 1, (write ? 1 : 0)), sz, write);
RESTORE_EXCEPTION;
return true;
}
CATCH(prb) {
RESTORE_EXCEPTION;
return false;
}
}
#else
# define get_quad(a) phys_get_quad(a)
# define get_long(a) phys_get_long(a)
# define get_word(a) phys_get_word(a)
# define get_byte(a) phys_get_byte(a)
# define put_quad(a,b) phys_put_quad(a,b)
# define put_long(a,b) phys_put_long(a,b)
# define put_word(a,b) phys_put_word(a,b)
# define put_byte(a,b) phys_put_byte(a,b)
# define get_real_address(a,w,s) phys_get_real_address(a)
#define valid_address(a,w,s) phys_valid_address(a,w,s)
#endif
static inline void flush_internals() {
#ifdef ARAM_PAGE_CHECK
pc_page = 0xeeeeeeee;
read_page = 0xeeeeeeee;
write_page = 0xeeeeeeee;
#endif
}
#endif /* MEMORY_H */
/*
vim:ts=4:sw=4:
*/

59
BasiliskII/src/uae_cpu/memory.cpp
View File

@ -1,59 +0,0 @@
/*
* memory.cpp - memory management
*
* Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
*
* Inspired by Christian Bauer's Basilisk II
*
* This file is part of the ARAnyM project which builds a new and powerful
* TOS/FreeMiNT compatible virtual machine running on almost any hardware.
*
* ARAnyM is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* ARAnyM is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ARAnyM; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* UAE - The Un*x Amiga Emulator
*
* Memory management
*
* (c) 1995 Bernd Schmidt
*/
#include "sysdeps.h"
#include "memory.h"
#define DEBUG 0
#include "debug.h"
#ifdef ARAM_PAGE_CHECK
uaecptr pc_page = 0xeeeeeeee;
uintptr pc_offset = 0;
uaecptr read_page = 0xeeeeeeee;
uintptr read_offset = 0;
uaecptr write_page = 0xeeeeeeee;
uintptr write_offset = 0;
#endif
extern "C" void breakpt(void)
{
// bug("bus err: pc=%08x, sp=%08x, addr=%08x", m68k_getpc(), regs.regs[15], regs.mmu_fault_addr);
}
#if !KNOWN_ALLOC && !NORMAL_ADDRESSING
// This part need rewrite for ARAnyM !!
// It can be taken from hatari.
#error Not prepared for your platform, maybe you need memory banks from hatari
#endif /* !KNOWN_ALLOC && !NORMAL_ADDRESSING */

142
BasiliskII/src/uae_cpu/noflags.h
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@ -1,142 +0,0 @@
#ifndef NOFLAGS_H
#define NOFLAGS_H
/* Undefine everything that will *set* flags. Note: Leave *reading*
flags alone ;-). We assume that nobody does something like
SET_ZFLG(a=b+c), i.e. expect side effects of the macros. That would
be a stupid thing to do when using macros.
*/
/* Gwenole Beauchesne pointed out that CAS and CAS2 use flag_cmp to set
flags that are then used internally, and that thus the noflags versions
of those instructions were broken. Oops!
Easy fix: Leave flag_cmp alone. It is only used by CMP* and CAS*
instructions. For CAS*, noflags is a bad idea. For CMP*, which has
setting flags as its only function, the noflags version is kinda pointless,
anyway.
Note that this will only work while using the optflag_* routines ---
as we do on all (one ;-) platforms that will ever use the noflags
versions, anyway.
However, if you try to compile without optimized flags, the "SET_ZFLAG"
macro will be left unchanged, to make CAS and CAS2 work right. Of course,
this is contrary to the whole idea of noflags, but better be right than
be fast.
Another problem exists with one of the bitfield operations. Once again,
one of the operations sets a flag, and looks at it later. And the CHK2
instruction does so as well. For those, a different solution is possible.
the *_ALWAYS versions of the SET_?FLG macros shall remain untouched by
the redefinitions in this file.
Unfortunately, they are defined in terms of the macros we *do* redefine.
So here comes a bit of trickery....
*/
#define NOFLAGS_CMP 0
#undef SET_NFLG_ALWAYS
static inline void SET_NFLG_ALWAYS(uae_u32 x)
{
SET_NFLG(x); /* This has not yet been redefined */
}
#undef SET_CFLG_ALWAYS
static inline void SET_CFLG_ALWAYS(uae_u32 x)
{
SET_CFLG(x); /* This has not yet been redefined */
}
#undef CPUFUNC
#define CPUFUNC(x) x##_nf
#ifndef OPTIMIZED_FLAGS
#undef SET_ZFLG
#define SET_ZFLG(y) do {uae_u32 dummy=(y); } while (0)
#endif
#undef SET_CFLG
#define SET_CFLG(y) do {uae_u32 dummy=(y); } while (0)
#undef SET_VFLG
#define SET_VFLG(y) do {uae_u32 dummy=(y); } while (0)
#undef SET_NFLG
#define SET_NFLG(y) do {uae_u32 dummy=(y); } while (0)
#undef SET_XFLG
#define SET_XFLG(y) do {uae_u32 dummy=(y); } while (0)
#undef CLEAR_CZNV
#define CLEAR_CZNV()
#undef IOR_CZNV
#define IOR_CZNV(y) do {uae_u32 dummy=(y); } while (0)
#undef SET_CZNV
#define SET_CZNV(y) do {uae_u32 dummy=(y); } while (0)
#undef COPY_CARRY
#define COPY_CARRY()
#ifdef optflag_testl
#undef optflag_testl
#endif
#ifdef optflag_testw
#undef optflag_testw
#endif
#ifdef optflag_testb
#undef optflag_testb
#endif
#ifdef optflag_addl
#undef optflag_addl
#endif
#ifdef optflag_addw
#undef optflag_addw
#endif
#ifdef optflag_addb
#undef optflag_addb
#endif
#ifdef optflag_subl
#undef optflag_subl
#endif
#ifdef optflag_subw
#undef optflag_subw
#endif
#ifdef optflag_subb
#undef optflag_subb
#endif
#if NOFLAGS_CMP
#ifdef optflag_cmpl
#undef optflag_cmpl
#endif
#ifdef optflag_cmpw
#undef optflag_cmpw
#endif
#ifdef optflag_cmpb
#undef optflag_cmpb
#endif
#endif
#define optflag_testl(v) do { } while (0)
#define optflag_testw(v) do { } while (0)
#define optflag_testb(v) do { } while (0)
#define optflag_addl(v, s, d) (v = (uae_s32)(d) + (uae_s32)(s))
#define optflag_addw(v, s, d) (v = (uae_s16)(d) + (uae_s16)(s))
#define optflag_addb(v, s, d) (v = (uae_s8)(d) + (uae_s8)(s))
#define optflag_subl(v, s, d) (v = (uae_s32)(d) - (uae_s32)(s))
#define optflag_subw(v, s, d) (v = (uae_s16)(d) - (uae_s16)(s))
#define optflag_subb(v, s, d) (v = (uae_s8)(d) - (uae_s8)(s))
#if NOFLAGS_CMP
/* These are just for completeness sake */
#define optflag_cmpl(s, d) do { } while (0)
#define optflag_cmpw(s, d) do { } while (0)
#define optflag_cmpb(s, d) do { } while (0)
#endif
#endif

5
BasiliskII/src/uae_cpu/readcpua.cpp
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@ -1,5 +0,0 @@
/*
* readcpu.cpp must be compiled twice, once for the generator program
* and once for the actual executable
*/
#include "readcpu.cpp"