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Handle dcbz. Ignore unaligned load/store multiple. Fix icbi/isync.

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This commit is contained in:
gbeauche 2003-09-28 21:22:59 +00:00
parent 4e5e13d92d
commit 2a86a4f62a
2 changed files with 23 additions and 2 deletions
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2
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-decode.cpp
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@ -267,7 +267,7 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
X_form, 31, 246, CFLOW_NORMAL
},
{ "dcbz",
EXECUTE_0(nop),
EXECUTE_2(dcbz, operand_RA_or_0, operand_RB),
NULL,
X_form, 31, 1014, CFLOW_NORMAL
},

23
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-execute.cpp
View File

@ -564,8 +564,15 @@ void powerpc_cpu::execute_loadstore_multiple(uint32 opcode)
uint32 ea = a + d;
// FIXME: generate exception if ea is not word-aligned
if ((ea & 3) != 0)
if ((ea & 3) != 0) {
#ifdef SHEEPSHAVER
D(bug("unaligned EA load/store multiple\n"));
increment_pc(4);
return;
#else
abort();
#endif
}
int r = LD ? rD_field::extract(opcode) : rS_field::extract(opcode);
while (r <= 31) {
@ -1065,11 +1072,25 @@ void powerpc_cpu::execute_mftbr(uint32 opcode)
void powerpc_cpu::execute_icbi(uint32 opcode)
{
// TODO: record address range of code to invalidate
increment_pc(4);
}
void powerpc_cpu::execute_isync(uint32 opcode)
{
invalidate_cache();
increment_pc(4);
}
/**
* (Fake) data cache management
**/
template< class RA, class RB >
void powerpc_cpu::execute_dcbz(uint32 opcode)
{
uint32 ea = RA::get(this, opcode) + RB::get(this, opcode);
vm_memset(ea - (ea % 32), 0, 32);
increment_pc(4);
}
/**