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Try to recognize and handle PowerPC 970 (G5). Untested as I don't have such

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platforms handy.
This commit is contained in:
gbeauche 2004-07-01 22:55:02 +00:00
parent ecbb2163ff
commit 32a6ac321c
3 changed files with 31 additions and 0 deletions
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2
SheepShaver/src/Unix/main_unix.cpp
View File

@ -648,6 +648,8 @@ int main(int argc, char **argv)
PVR = 0x80010000;
else if (strcmp(value, "7457") == 0)
PVR = 0x80020000;
else if (strcmp(value, "PPC970") == 0)
PVR = 0x00390000;
else
printf("WARNING: Unknown CPU type '%s', assuming 604\n", value);
}

18
SheepShaver/src/name_registry.cpp
View File

@ -277,6 +277,24 @@ void DoPatchNameRegistry(void)
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
break;
case 0x39: // 970
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-block-size", u32.ptr(), 4);
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-sets", u32.ptr(), 4);
u32.set_value(0x8000);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-size", u32.ptr(), 4);
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-block-size", u32.ptr(), 4);
u32.set_value(512);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-sets", u32.ptr(), 4);
u32.set_value(0x10000);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-size", u32.ptr(), 4);
u32.set_value(256);
RegistryPropertyCreate(power_pc.ptr(), "tlb-sets", u32.ptr(), 4);
u32.set_value(0x1000);
RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
break;
default:
break;
}

11
SheepShaver/src/rom_patches.cpp
View File

@ -911,6 +911,17 @@ static bool patch_nanokernel_boot(void)
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
break;
case 0x39: // 970
lp[0] = htonl(0x1000); // Page size
lp[1] = htonl(0x8000); // Data cache size
lp[2] = htonl(0x10000); // Inst cache size
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
lp[6] = htonl(0x00800080); // Inst cache block size/Data cache block size
lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x02000004); // TLB total size/TLB assoc
break;
default:
printf("WARNING: Unknown CPU type\n");
break;