mirror of
https://github.com/kanjitalk755/macemu.git
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Add some FPU instructions. Minor clean-ups.
This commit is contained in:
gbeauche
parent
ee7cea923a
commit
45289042e6
@ -1,4 +1,4 @@
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/******************************** -*- C -*- ****************************
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/******************** -*- mode: C; tab-width: 8 -*- ********************
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*
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* Run-time assembler for i386 and x86-64
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*
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@ -95,7 +95,7 @@
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/* --- Register set -------------------------------------------------------- */
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typedef enum {
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enum {
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#if X86_FLAT_REGISTERS
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X86_NOREG = 0,
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X86_Reg8L_Base = 0x10,
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@ -106,14 +106,14 @@ typedef enum {
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#else
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X86_NOREG = -1,
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X86_Reg8L_Base = 0,
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X86_Reg8H_Base = 0,
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X86_Reg8H_Base = 16,
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X86_Reg16_Base = 0,
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X86_Reg32_Base = 0,
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X86_Reg64_Base = 0,
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#endif
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} X86_Base_Reg_No;
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};
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typedef enum {
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enum {
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X86_AL = X86_Reg8L_Base,
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X86_CL, X86_DL, X86_BL,
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X86_AH, X86_CH, X86_DH, X86_BH,
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@ -121,31 +121,31 @@ typedef enum {
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X86_R12B, X86_R13B, X86_R14B, X86_R15B,
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X86_SPL = X86_Reg8H_Base + 4,
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X86_BPL, X86_SIL, X86_DIL
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} X86_Reg8_No;
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};
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typedef enum {
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enum {
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X86_AX = X86_Reg16_Base,
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X86_CX, X86_DX, X86_BX,
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X86_SP, X86_BP, X86_SI, X86_DI,
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X86_R8W, X86_R9W, X86_R10W, X86_R11W,
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X86_R12W, X86_R13W, X86_R14W, X86_R15W
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} X86_Reg16_No;
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};
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typedef enum {
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enum {
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X86_EAX = X86_Reg32_Base,
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X86_ECX, X86_EDX, X86_EBX,
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X86_ESP, X86_EBP, X86_ESI, X86_EDI,
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X86_R8D, X86_R9D, X86_R10D, X86_R11D,
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X86_R12D, X86_R13D, X86_R14D, X86_R15D
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} X86_Reg32_No;
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};
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typedef enum {
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enum {
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X86_RAX = X86_Reg64_Base,
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X86_RCX, X86_RDX, X86_RBX,
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X86_RSP, X86_RBP, X86_RSI, X86_RDI,
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X86_R8, X86_R9, X86_R10, X86_R11,
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X86_R12, X86_R13, X86_R14, X86_R15
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} X86_Reg64_No;
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};
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/* Register control and access
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*
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@ -473,11 +473,12 @@ typedef unsigned int _ul;
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* + r = register operand
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* + m = memory operand (disp,base,index,scale)
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* + sr/sm = a star preceding a register or memory
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* + 0 = top of stack register (for FPU instructions)
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*/
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/* --- ALU instructions ---------------------------------------------------- */
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typedef enum {
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enum {
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X86_ADD = 0,
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X86_OR = 1,
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X86_ADC = 2,
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@ -486,8 +487,7 @@ typedef enum {
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X86_SUB = 5,
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X86_XOR = 6,
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X86_CMP = 7,
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X86_NALU
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} X86_ALU_Opcode;
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};
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/* _format Opcd ,Mod ,r ,m ,mem=dsp+sib ,imm... */
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@ -718,7 +718,7 @@ typedef enum {
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/* --- Shift/Rotate instructions ------------------------------------------- */
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typedef enum {
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enum {
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X86_ROL = 0,
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X86_ROR = 1,
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X86_RCL = 2,
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@ -726,7 +726,7 @@ typedef enum {
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X86_SHL = 4,
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X86_SHR = 5,
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X86_SAR = 7,
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} X86_Shift_Opcode;
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};
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/* _format Opcd ,Mod ,r ,m ,mem=dsp+sib ,imm... */
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@ -945,12 +945,12 @@ typedef enum {
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/* --- Bit test instructions ----------------------------------------------- */
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typedef enum {
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enum {
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X86_BT = 4,
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X86_BTS = 5,
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X86_BTR = 6,
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X86_BTC = 7,
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} X86_Bit_Test_Opcode;
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};
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/* _format Opcd ,Mod ,r ,m ,mem=dsp+sib ,imm... */
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@ -1061,14 +1061,14 @@ typedef enum {
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/* --- Unary and Multiply/Divide instructions ------------------------------ */
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typedef enum {
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enum {
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X86_NOT = 2,
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X86_NEG = 3,
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X86_MUL = 4,
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X86_IMUL = 5,
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X86_DIV = 6,
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X86_IDIV = 7,
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} X86_Unary_Opcode;
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};
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/* _format Opcd ,Mod ,r ,m ,mem=dsp+sib ,imm... */
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@ -1472,8 +1472,9 @@ typedef enum {
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#define LAHF() _m32only( _O (0x9f ))
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#define SAHF() _m32only( _O (0x9e ))
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#define RDTSC() _OO (0xff31 )
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/* _format Opcd ,Mod ,r ,m ,mem=dsp+sib ,imm... */
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#define RDTSC() _OO (0xff31 )
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#define ENTERii(W, B) _O_W_B (0xc8 ,_su16(W),_su8(B))
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@ -1483,4 +1484,100 @@ typedef enum {
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#define NOP() _O (0x90 )
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/* --- FLoating-Point instructions ----------------------------------------- */
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#define _ESCmi(D,B,I,S,OP) (_REXLrm(0,B,I), _O_r_X(0xd8|(OP & 7), (OP >> 3), D,B,I,S))
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#define FLDr(R) _OOr(0xd9c0,_rN(R))
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#define FLDLm(D,B,I,S) _ESCmi(D,B,I,S,005)
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#define FLDSm(D,B,I,S) _ESCmi(D,B,I,S,001)
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#define FLDTm(D,B,I,S) _ESCmi(D,B,I,S,053)
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#define FSTr(R) _OOr(0xddd0,_rN(R))
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#define FSTSm(D,B,I,S) _ESCmi(D,B,I,S,021)
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#define FSTLm(D,B,I,S) _ESCmi(D,B,I,S,025)
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#define FSTPr(R) _OOr(0xddd8,_rN(R))
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#define FSTPSm(D,B,I,S) _ESCmi(D,B,I,S,031)
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#define FSTPLm(D,B,I,S) _ESCmi(D,B,I,S,035)
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#define FSTPTm(D,B,I,S) _ESCmi(D,B,I,S,073)
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#define FADDr0(R) _OOr(0xd8c0,_rN(R))
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#define FADD0r(R) _OOr(0xdcc0,_rN(R))
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#define FADDP0r(R) _OOr(0xdec0,_rN(R))
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#define FADDSm(D,B,I,S) _ESCmi(D,B,I,S,000)
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#define FADDLm(D,B,I,S) _ESCmi(D,B,I,S,004)
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#define FSUBSm(D,B,I,S) _ESCmi(D,B,I,S,040)
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#define FSUBLm(D,B,I,S) _ESCmi(D,B,I,S,044)
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#define FSUBr0(R) _OOr(0xd8e0,_rN(R))
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#define FSUB0r(R) _OOr(0xdce8,_rN(R))
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#define FSUBP0r(R) _OOr(0xdee8,_rN(R))
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#define FSUBRr0(R) _OOr(0xd8e8,_rN(R))
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#define FSUBR0r(R) _OOr(0xdce0,_rN(R))
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#define FSUBRP0r(R) _OOr(0xdee0,_rN(R))
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#define FSUBRSm(D,B,I,S) _ESCmi(D,B,I,S,050)
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#define FSUBRLm(D,B,I,S) _ESCmi(D,B,I,S,054)
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#define FMULr0(R) _OOr(0xd8c8,_rN(R))
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#define FMUL0r(R) _OOr(0xdcc8,_rN(R))
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#define FMULP0r(R) _OOr(0xdec8,_rN(R))
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#define FMULSm(D,B,I,S) _ESCmi(D,B,I,S,010)
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#define FMULLm(D,B,I,S) _ESCmi(D,B,I,S,014)
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#define FDIVr0(R) _OOr(0xd8f0,_rN(R))
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#define FDIV0r(R) _OOr(0xdcf8,_rN(R))
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#define FDIVP0r(R) _OOr(0xdef8,_rN(R))
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#define FDIVSm(D,B,I,S) _ESCmi(D,B,I,S,060)
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#define FDIVLm(D,B,I,S) _ESCmi(D,B,I,S,064)
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#define FDIVRr0(R) _OOr(0xd8f8,_rN(R))
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#define FDIVR0r(R) _OOr(0xdcf0,_rN(R))
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#define FDIVRP0r(R) _OOr(0xdef0,_rN(R))
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#define FDIVRSm(D,B,I,S) _ESCmi(D,B,I,S,070)
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#define FDIVRLm(D,B,I,S) _ESCmi(D,B,I,S,074)
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#define FCMOVBr0(R) _OOr(0xdac0,_rN(R))
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#define FCMOVBEr0(R) _OOr(0xdad0,_rN(R))
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#define FCMOVEr0(R) _OOr(0xdac8,_rN(R))
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#define FCMOVNBr0(R) _OOr(0xdbc0,_rN(R))
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#define FCMOVNBEr0(R) _OOr(0xdbd0,_rN(R))
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#define FCMOVNEr0(R) _OOr(0xdbc8,_rN(R))
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#define FCMOVNUr0(R) _OOr(0xdbd8,_rN(R))
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#define FCMOVUr0(R) _OOr(0xdad8,_rN(R))
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#define FCOMIr0(R) _OOr(0xdbf0,_rN(R))
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#define FCOMIPr0(R) _OOr(0xdff0,_rN(R))
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#define FCOMr(R) _OOr(0xd8d0,_rN(R))
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#define FCOMSm(D,B,I,S) _ESCmi(D,B,I,S,020)
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#define FCOMLm(D,B,I,S) _ESCmi(D,B,I,S,024)
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#define FCOMPr(R) _OOr(0xd8d8,_rN(R))
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#define FCOMPSm(D,B,I,S) _ESCmi(D,B,I,S,030)
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#define FCOMPLm(D,B,I,S) _ESCmi(D,B,I,S,034)
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#define FUCOMIr0(R) _OOr(0xdbe8,_rN(R))
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#define FUCOMIPr0(R) _OOr(0xdfe8,_rN(R))
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#define FUCOMPr(R) _OOr(0xdde8,_rN(R))
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#define FUCOMr(R) _OOr(0xdde0,_rN(R))
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#define FIADDLm(D,B,I,S) _ESCmi(D,B,I,S,002)
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#define FICOMLm(D,B,I,S) _ESCmi(D,B,I,S,022)
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#define FICOMPLm(D,B,I,S) _ESCmi(D,B,I,S,032)
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#define FIDIVLm(D,B,I,S) _ESCmi(D,B,I,S,062)
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#define FIDIVRLm(D,B,I,S) _ESCmi(D,B,I,S,072)
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#define FILDLm(D,B,I,S) _ESCmi(D,B,I,S,003)
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#define FILDQm(D,B,I,S) _ESCmi(D,B,I,S,057)
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#define FIMULLm(D,B,I,S) _ESCmi(D,B,I,S,012)
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#define FISTLm(D,B,I,S) _ESCmi(D,B,I,S,023)
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#define FISTPLm(D,B,I,S) _ESCmi(D,B,I,S,033)
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#define FISTPQm(D,B,I,S) _ESCmi(D,B,I,S,077)
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#define FISUBLm(D,B,I,S) _ESCmi(D,B,I,S,042)
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#define FISUBRLm(D,B,I,S) _ESCmi(D,B,I,S,052)
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#define FREEr(R) _OOr(0xddc0,_rN(R))
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#define FXCHr(R) _OOr(0xd9c8,_rN(R))
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#endif /* X86_RTASM_H */
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