From 48a41966fdb21154a166031f7ec1cdf2f05f8b6f Mon Sep 17 00:00:00 2001 From: uyjulian Date: Sun, 1 Sep 2019 16:56:03 -0500 Subject: [PATCH] Sync with ARAnyM compiler sources --- BasiliskII/src/Unix/main_unix.cpp | 4 +- BasiliskII/src/Unix/timer_unix.cpp | 28 +- .../src/uae_cpu/compiler/codegen_arm.cpp | 161 +- BasiliskII/src/uae_cpu/compiler/codegen_arm.h | 66 +- .../src/uae_cpu/compiler/codegen_x86.cpp | 2153 +------------ BasiliskII/src/uae_cpu/compiler/codegen_x86.h | 50 +- BasiliskII/src/uae_cpu/compiler/compemu.h | 89 +- .../src/uae_cpu/compiler/compemu_fpp.cpp | 2832 ++++++++++------- .../uae_cpu/compiler/compemu_midfunc_arm.cpp | 143 - .../uae_cpu/compiler/compemu_midfunc_arm.h | 2 + .../uae_cpu/compiler/compemu_midfunc_arm2.cpp | 233 -- .../uae_cpu/compiler/compemu_midfunc_x86.cpp | 369 +-- .../uae_cpu/compiler/compemu_midfunc_x86.h | 19 +- .../src/uae_cpu/compiler/compemu_support.cpp | 426 +-- BasiliskII/src/uae_cpu/compiler/gencomp.c | 695 ++-- BasiliskII/src/uae_cpu/compiler/gencomp_arm.c | 110 +- BasiliskII/src/uae_cpu/gencpu.c | 108 +- BasiliskII/src/uae_cpu/m68k.h | 711 ++++- BasiliskII/src/uae_cpu/newcpu.cpp | 10 +- BasiliskII/src/uae_cpu/noflags.h | 4 +- 20 files changed, 3100 insertions(+), 5113 deletions(-) diff --git a/BasiliskII/src/Unix/main_unix.cpp b/BasiliskII/src/Unix/main_unix.cpp index fd51fee8..6d17121f 100644 --- a/BasiliskII/src/Unix/main_unix.cpp +++ b/BasiliskII/src/Unix/main_unix.cpp @@ -57,7 +57,7 @@ using std::string; #include "sigsegv.h" #if USE_JIT -extern void flush_icache_range(uint8 *start, uint32 size); // from compemu_support.cpp +extern void (*flush_icache)(void); // from compemu_support.cpp #endif @@ -542,7 +542,7 @@ void FlushCodeCache(void *start, uint32 size) { #if USE_JIT if (UseJIT) - flush_icache_range((uint8 *)start, size); + flush_icache(); #endif } diff --git a/BasiliskII/src/Unix/timer_unix.cpp b/BasiliskII/src/Unix/timer_unix.cpp index 03225ef5..6fb8cf3e 100644 --- a/BasiliskII/src/Unix/timer_unix.cpp +++ b/BasiliskII/src/Unix/timer_unix.cpp @@ -22,9 +22,9 @@ #include "macos_util.h" #include "timer.h" -// #ifdef USE_SDL -// # include -// #endif +#ifdef USE_SDL +# include +#endif #include @@ -341,19 +341,19 @@ void Delay_usec(uint32 usec) // #endif // #endif -// SDL_mutex *idle_lock; -// SDL_cond *idle_cond; +SDL_mutex *idle_lock; +SDL_cond *idle_cond; void idle_wait(void) { //This causes events to not process randomly in JIT so commented out - // if (!idle_lock) - // idle_lock = SDL_CreateMutex(); - // if (!idle_cond) - // idle_cond = SDL_CreateCond(); - // SDL_LockMutex(idle_lock); - // SDL_CondWait(idle_cond, idle_lock); - // SDL_UnlockMutex(idle_lock); + if (!idle_lock) + idle_lock = SDL_CreateMutex(); + if (!idle_cond) + idle_cond = SDL_CreateCond(); + SDL_LockMutex(idle_lock); + SDL_CondWait(idle_cond, idle_lock); + SDL_UnlockMutex(idle_lock); // #ifdef IDLE_USES_COND_WAIT // pthread_mutex_lock(&idle_lock); @@ -386,8 +386,8 @@ void idle_wait(void) void idle_resume(void) { //This causes events to not process randomly in JIT so commented out - // if (idle_cond) - // SDL_CondSignal(idle_cond); + if (idle_cond) + SDL_CondSignal(idle_cond); // #ifdef IDLE_USES_COND_WAIT // pthread_cond_signal(&idle_cond); // #else diff --git a/BasiliskII/src/uae_cpu/compiler/codegen_arm.cpp b/BasiliskII/src/uae_cpu/compiler/codegen_arm.cpp index fb7e69c7..01c49e30 100644 --- a/BasiliskII/src/uae_cpu/compiler/codegen_arm.cpp +++ b/BasiliskII/src/uae_cpu/compiler/codegen_arm.cpp @@ -190,13 +190,11 @@ LOWFUNC(NONE,WRITE,1,raw_push_l_r,(RR4 r)) { PUSH(r); } -LENDFUNC(NONE,WRITE,1,raw_push_l_r,(RR4 r)) LOWFUNC(NONE,READ,1,raw_pop_l_r,(RR4 r)) { POP(r); } -LENDFUNC(NONE,READ,1,raw_pop_l_r,(RR4 r)) LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, RR1 s)) { @@ -210,7 +208,6 @@ LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, RR1 s)) BIC_rri(d, d, 0xFF); // bic %[d],%[d],#0xFF ORR_rrrLSRi(d, d, REG_WORK2, 24); // orr %[d],%[d], R3 LSR #24 } -LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, RR1 s)) LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, RR2 s)) { @@ -228,13 +225,11 @@ LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, RR2 s)) ORR_rrrLSRi(d, d, REG_WORK2, 16); // orr %[d], %[d], r3, lsr #16 #endif } -LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, RR2 s)) LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, RR4 s)) { ADCS_rrr(d, d, s); // adcs %[d],%[d],%[s] } -LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, RR1 s)) { @@ -246,7 +241,6 @@ LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, RR1 s)) BIC_rri(d, d, 0xFF); // bic %[d],%[d],#0xFF ORR_rrrLSRi(d, d, REG_WORK2, 24); // orr %[d],%[d], r3 LSR #24 } -LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, RR2 s)) { @@ -263,13 +257,11 @@ LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, RR2 s)) ORR_rrrLSRi(d, d, REG_WORK2, 16); // orr r7, r7, r3, LSR #16 #endif } -LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, RR4 s)) { ADDS_rrr(d, d, s); // adds %[d], %[d], %[s] } -LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) { @@ -305,7 +297,6 @@ LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) { @@ -316,7 +307,6 @@ LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) BIC_rri(d, d, 0xFF); // bic %[d],%[d], #0xFF ORR_rrrLSRi(d, d, REG_WORK2, 24); // orr %[d],%[d], r3, lsr #24 } -LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) { @@ -334,7 +324,6 @@ LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, RR1 s)) { @@ -348,7 +337,6 @@ LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, RR1 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, RR2 s)) { @@ -362,7 +350,6 @@ LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, RR2 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, RR4 s)) { @@ -372,7 +359,6 @@ LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, RR4 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) { @@ -396,7 +382,6 @@ LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, RR4 s)) { @@ -414,7 +399,6 @@ LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, RR4 s)) CC_ORR_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_Z_FLAG); // orr r3,r3,#0x40000000 MSR_CPSR_r(REG_WORK2); // msr cpsr,r3 } -LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, RR4 s)) LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) { @@ -435,7 +419,6 @@ LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) ORR_rrrLSLi(r,r,REG_WORK1, 8); // orr r6, r6, r2, lsl #8 #endif } -LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) { @@ -448,7 +431,6 @@ LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) EOR_rrrLSRi(r, r, REG_WORK1, 8); // eor r6, r6, r2, lsr #8 #endif } -LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(RR4 r, IMM i)) { @@ -460,7 +442,6 @@ LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(RR4 r, IMM i)) CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG); // orr r3, r3, #0x20000000 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(RR4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(RR4 r, RR4 b)) { @@ -473,7 +454,6 @@ LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(RR4 r, RR4 b)) CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG); // bic r3, r3, #0x20000000 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(RR4 r, RR4 b)) LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, RR4 b)) { @@ -488,7 +468,6 @@ LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, RR4 b)) EOR_rrr(r, r, REG_WORK1); // eor r6, r6, r2 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, RR4 b)) LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, RR4 b)) { @@ -503,7 +482,6 @@ LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, RR4 b)) BIC_rrr(r, r, REG_WORK1); // bic r6, r6, r2 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, RR4 b)) LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, RR4 b)) { @@ -518,7 +496,6 @@ LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, RR4 b)) ORR_rrr(r, r, REG_WORK1); // orr r6, r6, r2 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, RR4 b)) LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, RR4 s, IMM cc)) { @@ -543,7 +520,6 @@ LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, RR4 s, IMM cc)) } //: } -LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, RR4 s, IMM cc)) LOWFUNC(WRITE,NONE,2,raw_cmp_b,(RR1 d, RR1 s)) { @@ -560,7 +536,6 @@ LOWFUNC(WRITE,NONE,2,raw_cmp_b,(RR1 d, RR1 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_cmp_b,(RR1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_cmp_w,(RR2 d, RR2 s)) { @@ -578,7 +553,6 @@ LOWFUNC(WRITE,NONE,2,raw_cmp_w,(RR2 d, RR2 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_cmp_w,(RR2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_cmp_l,(RR4 d, RR4 s)) { @@ -588,14 +562,12 @@ LOWFUNC(WRITE,NONE,2,raw_cmp_l,(RR4 d, RR4 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_cmp_l,(RR4 d, RR4 s)) LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, RR4 s)) { SMULL_rrrr(REG_WORK1, REG_WORK2, d, s); // smull r2,r3,r7,r6 MOV_rr(d, REG_WORK1); // mov r7,r2 } -LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, RR4 s)) LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) { @@ -603,7 +575,6 @@ LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) MOV_rr(MUL_NREG1, REG_WORK1); // mov r7,r2 MOV_rr(MUL_NREG2, REG_WORK2); } -LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) { @@ -621,7 +592,6 @@ LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) { @@ -649,7 +619,6 @@ LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, I //; #endif } -LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) { @@ -664,7 +633,6 @@ LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) ADD_rrrLSLi(d, s, index, shft); // ADD R7,R6,R5,LSL #2 } -LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, RR4 s, IMM offset)) { @@ -686,7 +654,6 @@ LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, RR4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(RR4 d, RR1 s, IMM offset)) { @@ -704,7 +671,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(RR4 d, RR1 s, IMM offset)) //: #endif } -LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(RR4 d, RR1 s, IMM offset)) LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) { @@ -725,7 +691,6 @@ LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, RR1 s)) { @@ -743,14 +708,12 @@ LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, RR1 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, RR1 s)) LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) { BIC_rri(d, d, 0xff); // bic %[d], %[d], #0xff ORR_rri(d, d, (s & 0xff)); // orr %[d], %[d], #%[s] } -LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) { @@ -771,7 +734,6 @@ LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) //: #endif } -LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s)) { @@ -779,7 +741,6 @@ LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s)) BIC_rri(d, d, 0x0ff); // bic %[d], %[d], #0xff ORR_rrr(d, d, REG_WORK1); // orr %[d], %[d], r2 } -LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, RR1 s)) LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, RR4 s, IMM offset)) { @@ -797,7 +758,6 @@ LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, RR4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(RR4 d, RR4 s, IMM offset)) { @@ -815,7 +775,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(RR4 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(RR4 d, RR4 s, IMM offset)) LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) { @@ -843,7 +802,6 @@ LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, RR4 s, IMM offset)) { @@ -874,7 +832,6 @@ LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, RR4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(RR4 d, RR2 s, IMM offset)) { @@ -892,7 +849,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(RR4 d, RR2 s, IMM offset)) //: #endif } -LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(RR4 d, RR2 s, IMM offset)) LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, RR2 s)) { @@ -910,7 +866,6 @@ LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, RR2 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, RR2 s)) LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) { @@ -942,7 +897,6 @@ LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) //: #endif } -LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) { @@ -973,7 +927,6 @@ LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, RR4 s)) { @@ -991,7 +944,6 @@ LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, RR4 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, RR4 s)) LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(RR4 d, IMM i, IMM offset)) { @@ -1016,7 +968,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(RR4 d, IMM i, IMM offset)) //: #endif } -LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(RR4 d, IMM i, IMM offset)) LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) { @@ -1037,7 +988,6 @@ LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) //: #endif } -LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, RR2 s)) { @@ -1045,7 +995,6 @@ LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, RR2 s)) ORR_rrrLSRi(d, REG_WORK1, d, 16); // orr r7, r2, r7, lsr #16 ROR_rri(d, d, 16); // ror r7, r7, #16 } -LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, RR2 s)) LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, RR4 s, IMM offset)) { @@ -1064,7 +1013,6 @@ LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, RR4 s, IMM offset)) ORR_rrr(d, d, REG_WORK1); // orr r7, r7, r2 #endif } -LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, RR4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(RR4 d, RR2 s, IMM offset)) { @@ -1075,7 +1023,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(RR4 d, RR2 s, IMM offset)) else STRH_rRi(s, d, -offset);// strh r6, [r7, #-0x7f] } -LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(RR4 d, RR2 s, IMM offset)) LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) { @@ -1093,7 +1040,6 @@ LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) //: #endif } -LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, MEMR base, RR4 index, IMM factor)) { @@ -1119,7 +1065,6 @@ LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, MEMR base, RR4 index, IMM factor //: #endif } -LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, MEMR base, RR4 index, IMM factor)) LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(RR4 d, IMM i, IMM offset8)) { @@ -1143,7 +1088,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(RR4 d, IMM i, IMM offset8)) //: #endif } -LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(RR4 d, IMM i, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, RR4 s, IMM offset)) { @@ -1154,13 +1098,11 @@ LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, RR4 s, IMM offset)) } else LDR_rRi(d, s, -offset); // ldr r2, [r1, #12] } -LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, RR4 s, IMM offset)) LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, RR4 s)) { MOV_rr(d, s); // mov %[d], %[s] } -LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, RR4 s)) LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(RR4 d, RR4 s, IMM offset)) { @@ -1171,7 +1113,6 @@ LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(RR4 d, RR4 s, IMM offset)) else STR_rRi(s, d, -offset); // str r6, [r7, #-12] } -LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(RR4 d, RR4 s, IMM offset)) LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) { @@ -1179,7 +1120,6 @@ LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) MOV_rr(MUL_NREG1, REG_WORK1); // mov r7,r2 MOV_rr(MUL_NREG2, REG_WORK2); } -LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, RR1 s)) { @@ -1191,7 +1131,6 @@ LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, RR1 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, RR2 s)) { @@ -1208,7 +1147,6 @@ LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, RR2 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, RR4 s)) { @@ -1218,7 +1156,6 @@ LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, RR4 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) { @@ -1242,7 +1179,6 @@ LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) //jp: #endif } -LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) { @@ -1265,7 +1201,6 @@ LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) BIC_rri(r, r, 0xff); // bic r7,r7,#0xff ORR_rrr(r, r, REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, RR1 r)) { @@ -1292,7 +1227,6 @@ LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, RR1 r)) ORR_rrr(d, d, REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) { @@ -1315,7 +1249,6 @@ LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) ORR_rrrLSRi(r, r, REG_WORK1, 16); // orr r7,r7,r2,lsr #16 } -LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, RR1 r)) { @@ -1341,7 +1274,6 @@ LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, RR1 r)) ORR_rrrLSRi(d, d, REG_WORK1, 16); // orr r2,r2,r7,lsr #16 } -LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) { @@ -1356,13 +1288,11 @@ LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG); // bic r3,r3,#0x20000000 MSR_CPSR_r(REG_WORK2); } -LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) { RORS_rri(r, r, i & 0x1F); // RORS r7,r7,#12 } -LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, RR1 r)) { @@ -1380,13 +1310,11 @@ LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, RR1 r)) CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG); // bic r3,r3,#0x20000000 MSR_CPSR_r(REG_WORK2); } -LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, RR1 r)) { RORS_rrr(d, d, r); // RORS r7,r7,r6 } -LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) { @@ -1400,7 +1328,6 @@ LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) BIC_rri(r, r, 0xff); // bic r7,r7,#0xff ORR_rrr(r, r, REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, RR1 r)) { @@ -1414,7 +1341,6 @@ LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, RR1 r)) BIC_rri(d, d, 0xff); // bic r7,r7,#0xff ORR_rrr(d, d, REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) { @@ -1428,7 +1354,6 @@ LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) ORR_rrrLSRi(r, r, REG_WORK1, 16); // orr r7,r7,r2,lsr #16 } -LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, RR1 r)) { @@ -1442,7 +1367,6 @@ LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, RR1 r)) ORR_rrrLSRi(d, d, REG_WORK1, 16); // orr r7,r7,r2,lsr #16 } -LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, RR1 r)) LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, RR1 s)) { @@ -1461,7 +1385,6 @@ LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, RR1 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, RR1 s)) LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, RR4 s)) { @@ -1475,7 +1398,6 @@ LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, RR4 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, RR4 s)) LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, RR2 s)) { @@ -1495,7 +1417,6 @@ LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, RR2 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, RR2 s)) LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) { @@ -1530,7 +1451,6 @@ LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) } //: } -LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) { @@ -1577,7 +1497,6 @@ LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) //: #endif } -LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) { @@ -1588,7 +1507,6 @@ LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) BIC_rri(r, r, 0xff); // BIC r7,r7,0xff ORR_rrrLSRi(r, r, REG_WORK1, 24); // ORR r7,r7,r2,lsr #24 } -LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, RR1 r)) { @@ -1597,19 +1515,16 @@ LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, RR1 r)) BIC_rri(d, d, 0xff); // BIC r7,r7,#0xff ORR_rrrLSRi(d, d, REG_WORK1, 24); // ORR r7,r7,r2,lsr #24 } -LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) { LSLS_rri(r,r, i & 0x1f); // lsls r7,r7,#12 } -LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, RR1 r)) { LSLS_rrr(d, d, r); } -LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) { @@ -1620,7 +1535,6 @@ LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) ROR_rri(r, REG_WORK1, 16); // ROR r7,r2,#16 } -LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, RR1 r)) { @@ -1629,7 +1543,6 @@ LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, RR1 r)) ORR_rrrLSRi(REG_WORK1, REG_WORK1, d, 16); // ORR r2,r2,r7,lsr #16 ROR_rri(d, REG_WORK1, 16); // ROR r7,r2,#16 } -LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) { @@ -1642,7 +1555,6 @@ LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) BIC_rri(r,r, 0xff); // bic r7,r7,#0xff ORR_rrr(r,r,REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, RR1 r)) { @@ -1656,7 +1568,6 @@ LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, RR1 r)) ORR_rrr(d,d,REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) { @@ -1677,7 +1588,6 @@ LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) ORR_rrr(r,r,REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, RR1 r)) { @@ -1698,19 +1608,16 @@ LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, RR1 r)) ORR_rrr(d,d,REG_WORK1); // orr r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) { ASRS_rri(r, r, i & 0x1f); // ASRS r7,r7,#12 } -LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, RR1 r)) { ASRS_rrr(d, d, r); // ASRS r7,r7,r6 } -LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) { @@ -1721,7 +1628,6 @@ LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) BIC_rri(r, r, 0xFF); // BIC r7,r7,#0xff ORR_rrr(r, r, REG_WORK1); // ORR r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, RR1 r)) { @@ -1732,13 +1638,11 @@ LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, RR1 r)) BIC_rri(d, d, 0xFF); // BIC r7,r7,#0xff ORR_rrr(d, d, REG_WORK1); // ORR r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) { LSRS_rri(r, r, i & 0x1f); // LSRS r7,r7,#12 } -LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) { @@ -1755,7 +1659,6 @@ LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) BIC_rri(r, r, 0xFF00); // BIC r7,r7,#0xff00 ORR_rrr(r, r, REG_WORK1); // ORR r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, RR1 r)) { @@ -1772,13 +1675,11 @@ LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, RR1 r)) BIC_rri(d, d, 0xFF00); // BIC r7,r7,#0xff00 ORR_rrr(d, d, REG_WORK1); // ORR r7,r7,r2 } -LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, RR1 r)) { LSRS_rrr(d, d, r); } -LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, RR1 r)) LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, RR1 s)) { @@ -1793,7 +1694,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, RR1 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) { @@ -1807,7 +1707,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, RR4 s)) { @@ -1817,7 +1716,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, RR4 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) { @@ -1841,7 +1739,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, RR2 s)) { @@ -1857,7 +1754,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, RR2 s)) EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG); // eor r2, r2, #0x20000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) { @@ -1890,7 +1786,6 @@ LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(RR1 d, RR1 s)) { @@ -1908,7 +1803,6 @@ LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(RR1 d, RR1 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(RR1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(RR4 d, IMM i)) { @@ -1932,7 +1826,6 @@ LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(RR4 d, IMM i)) //: #endif } -LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(RR4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(RR4 d, RR4 s)) { @@ -1942,7 +1835,6 @@ LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(RR4 d, RR4 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(RR4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(RR2 d, RR2 s)) { @@ -1960,7 +1852,6 @@ LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(RR2 d, RR2 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(RR2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, RR1 s)) { @@ -1972,7 +1863,6 @@ LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, RR1 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, RR2 s)) { @@ -1989,7 +1879,6 @@ LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, RR2 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, RR4 s)) { @@ -1999,7 +1888,6 @@ LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, RR4 s)) BIC_rri(REG_WORK1, REG_WORK1, ARM_CV_FLAGS); // bic r2, r2, #0x30000000 MSR_CPSR_r(REG_WORK1); // msr CPSR_fc, r2 } -LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, RR4 s)) LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, RR2 s)) { @@ -2010,7 +1898,6 @@ LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, RR2 s)) ASR_rri(d, d, 16); // asr r6, r6, #16 #endif } -LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, RR2 s)) LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, RR1 s)) { @@ -2021,7 +1908,6 @@ LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, RR1 s)) ASR_rri(d, d, 24); // asr r6, r6, #24 #endif } -LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, RR1 s)) LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, RR1 s)) { @@ -2032,7 +1918,6 @@ LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, RR1 s)) LSR_rri(d, d, 24); // lsr r2, r2, #24 #endif } -LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, RR1 s)) LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, RR2 s)) { @@ -2043,7 +1928,6 @@ LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, RR2 s)) BIC_rri(d, d, 0x00ff0000); // bic %[d], %[d], #0x00ff0000 #endif } -LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, RR2 s)) static inline void raw_dec_sp(int off) { @@ -2167,29 +2051,25 @@ D(panicbug("raw_fp_cleanup_drop")); raw_fp_init(); } -LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMPTRW m, FR r)) { jit_unimplemented("raw_fmov_mr_drop %x %x", m, r); } -LENDFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r)) -LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMPTRW m, FR r)) { jit_unimplemented("raw_fmov_mr %x %x", m, r); } -LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r)) -LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m)) +LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMPTRR m)) { jit_unimplemented("raw_fmov_rm %x %x", r, m); } -LENDFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m)) LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) { jit_unimplemented("raw_fmov_rr %x %x", d, s); } -LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) static inline void raw_emit_nop_filler(int nbytes) { @@ -2235,19 +2115,16 @@ LOWFUNC(WRITE,NONE,2,raw_ADD_l_rr,(RW4 d, RR4 s)) { ADD_rrr(d, d, s); } -LENDFUNC(WRITE,NONE,2,raw_ADD_l_rr,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_ADD_l_rri,(RW4 d, RR4 s, IMM i)) { ADD_rri(d, s, i); } -LENDFUNC(WRITE,NONE,2,raw_ADD_l_rri,(RW4 d, RR4 s, IMM i)) LOWFUNC(WRITE,NONE,2,raw_SUB_l_rri,(RW4 d, RR4 s, IMM i)) { SUB_rri(d, s, i); } -LENDFUNC(WRITE,NONE,2,raw_SUB_l_rri,(RW4 d, RR4 s, IMM i)) LOWFUNC(WRITE,NONE,2,raw_AND_b_rr,(RW1 d, RR1 s)) { @@ -2255,19 +2132,16 @@ LOWFUNC(WRITE,NONE,2,raw_AND_b_rr,(RW1 d, RR1 s)) MVN_rrLSRi(REG_WORK1, REG_WORK1, 24); // mvn r2, %[s], lsr #24 AND_rrr(d, d, REG_WORK1); // and %[d], %[d], r2 } -LENDFUNC(WRITE,NONE,2,raw_AND_b_rr,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_AND_l_rr,(RW4 d, RR4 s)) { AND_rrr(d, d, s); } -LENDFUNC(WRITE,NONE,2,raw_AND_l_rr,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_AND_l_ri,(RW4 d, IMM i)) { AND_rri(d, d, i); } -LENDFUNC(WRITE,NONE,2,raw_AND_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_AND_w_rr,(RW2 d, RR2 s)) { @@ -2275,7 +2149,6 @@ LOWFUNC(WRITE,NONE,2,raw_AND_w_rr,(RW2 d, RR2 s)) MVN_rrLSRi(REG_WORK1, REG_WORK1, 16); // mvn r2, %[s], lsr #16 AND_rrr(d, d, REG_WORK1); // and %[d], %[d], r2 } -LENDFUNC(WRITE,NONE,2,raw_AND_w_rr,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_EOR_b_rr,(RW1 d, RR1 s)) { @@ -2286,13 +2159,11 @@ LOWFUNC(WRITE,NONE,2,raw_EOR_b_rr,(RW1 d, RR1 s)) #endif EOR_rrr(d, d, REG_WORK1); // eor %[d], %[d], r2 } -LENDFUNC(WRITE,NONE,2,raw_EOR_b_rr,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_EOR_l_rr,(RW4 d, RR4 s)) { EOR_rrr(d, d, s); // eors r7, r7, r6 } -LENDFUNC(WRITE,NONE,2,raw_EOR_l_rr,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_EOR_w_rr,(RW2 d, RR2 s)) { @@ -2304,7 +2175,6 @@ LOWFUNC(WRITE,NONE,2,raw_EOR_w_rr,(RW2 d, RR2 s)) EOR_rrrLSRi(d, d, REG_WORK1, 16); // orr %[d], %[d], r2 #endif } -LENDFUNC(WRITE,NONE,2,raw_EOR_w_rr,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_LDR_l_ri,(RW4 d, IMM i)) { @@ -2317,13 +2187,11 @@ LOWFUNC(WRITE,NONE,2,raw_LDR_l_ri,(RW4 d, IMM i)) emit_long(i); #endif } -LENDFUNC(WRITE,NONE,2,raw_LDR_l_rr,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_MOV_l_ri8,(RW4 d, IMM i)) { MOV_ri(d, i); } -LENDFUNC(WRITE,NONE,2,raw_MOV_l_ri8,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ORR_b_rr,(RW1 d, RR1 s)) { @@ -2334,13 +2202,11 @@ LOWFUNC(WRITE,NONE,2,raw_ORR_b_rr,(RW1 d, RR1 s)) #endif ORR_rrr(d, d, REG_WORK1); // orr %[d], %[d], r2 } -LENDFUNC(WRITE,NONE,2,raw_ORR_b_rr,(RW1 d, RR1 s)) LOWFUNC(WRITE,NONE,2,raw_ORR_l_rr,(RW4 d, RR4 s)) { ORR_rrr(d, d, s); } -LENDFUNC(WRITE,NONE,2,raw_ORR_l_rr,(RW4 d, RR4 s)) LOWFUNC(WRITE,NONE,2,raw_ORR_w_rr,(RW2 d, RR2 s)) { @@ -2352,13 +2218,11 @@ LOWFUNC(WRITE,NONE,2,raw_ORR_w_rr,(RW2 d, RR2 s)) ORR_rrrLSRi(d, d, REG_WORK1, 16); // orr %[d], %[d], r2 #endif } -LENDFUNC(WRITE,NONE,2,raw_ORR_w_rr,(RW2 d, RR2 s)) LOWFUNC(WRITE,NONE,2,raw_ROR_l_ri,(RW4 r, IMM i)) { ROR_rri(r, r, i); } -LENDFUNC(WRITE,NONE,2,raw_ROR_l_ri,(RW4 r, IMM i)) // // compuemu_support used raw calls @@ -2401,7 +2265,6 @@ LOWFUNC(WRITE,RMW,2,compemu_raw_add_l_mi,(IMM d, IMM s)) //: #endif } -LENDFUNC(WRITE,RMW,2,compemu_raw_add_l_mi,(IMM d, IMM s)) LOWFUNC(WRITE,NONE,2,compemu_raw_and_l_ri,(RW4 d, IMM i)) { @@ -2416,7 +2279,6 @@ LOWFUNC(WRITE,NONE,2,compemu_raw_and_l_ri,(RW4 d, IMM i)) emit_long(i); #endif } -LENDFUNC(WRITE,NONE,2,compemu_raw_and_l_ri,(RW4 d, IMM i)) LOWFUNC(NONE,NONE,1,compemu_raw_bswap_32,(RW4 r)) { @@ -2429,7 +2291,6 @@ LOWFUNC(NONE,NONE,1,compemu_raw_bswap_32,(RW4 r)) EOR_rrrLSRi(r, r, REG_WORK1, 8); // eor r6, r6, r2, lsr #8 #endif } -LENDFUNC(NONE,NONE,1,compemu_raw_bswap_32,(RW4 r)) LOWFUNC(WRITE,NONE,2,compemu_raw_bt_l_ri,(RR4 r, IMM i)) { @@ -2441,7 +2302,6 @@ LOWFUNC(WRITE,NONE,2,compemu_raw_bt_l_ri,(RR4 r, IMM i)) CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG); // orr r3, r3, #0x20000000 MSR_CPSR_r(REG_WORK2); // msr CPSR_fc, r3 } -LENDFUNC(WRITE,NONE,2,compemu_raw_bt_l_ri,(RR4 r, IMM i)) LOWFUNC(NONE,READ,5,compemu_raw_cmov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor, IMM cond)) { @@ -2478,7 +2338,6 @@ LOWFUNC(NONE,READ,5,compemu_raw_cmov_l_rm_indexed,(W4 d, IMM base, RR4 index, IM //: #endif } -LENDFUNC(NONE,READ,5,compemu_raw_cmov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor, IMM cond)) LOWFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi,(MEMR d, IMM s)) { @@ -2510,7 +2369,6 @@ LOWFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi,(MEMR d, IMM s)) //: #endif } -LENDFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi,(MEMR d, IMM s)) LOWFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi8,(MEMR d, IMM s)) { @@ -2532,7 +2390,6 @@ LOWFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi8,(MEMR d, IMM s)) //: #endif } -LENDFUNC(WRITE,READ,2,compemu_raw_cmp_l_mi8,(MEMR d, IMM s)) LOWFUNC(NONE,NONE,3,compemu_raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) { @@ -2550,7 +2407,6 @@ LOWFUNC(NONE,NONE,3,compemu_raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) //: #endif } -LENDFUNC(NONE,NONE,3,compemu_raw_lea_l_brr,(W4 d, RR4 s, IMM offset)) LOWFUNC(NONE,NONE,4,compemu_raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) { @@ -2565,7 +2421,6 @@ LOWFUNC(NONE,NONE,4,compemu_raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM fa ADD_rrrLSLi(d, s, index, shft); // ADD R7,R6,R5,LSL #2 } -LENDFUNC(NONE,NONE,4,compemu_raw_lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) LOWFUNC(NONE,WRITE,2,compemu_raw_mov_b_mr,(IMM d, RR1 s)) { @@ -2583,7 +2438,6 @@ LOWFUNC(NONE,WRITE,2,compemu_raw_mov_b_mr,(IMM d, RR1 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,compemu_raw_mov_b_mr,(IMM d, RR1 s)) LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMM s)) { @@ -2608,7 +2462,6 @@ LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMM s)) //: #endif } -LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMM s)) LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(IMM d, RR4 s)) { @@ -2626,7 +2479,6 @@ LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(IMM d, RR4 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(IMM d, RR4 s)) LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IMM s)) { @@ -2642,7 +2494,6 @@ LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IMM s)) //: #endif } -LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IMM s)) LOWFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s)) { @@ -2659,13 +2510,11 @@ LOWFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s)) //: #endif } -LENDFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s)) LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s)) { MOV_rr(d, s); // mov %[d], %[s] } -LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s)) LOWFUNC(NONE,WRITE,2,compemu_raw_mov_w_mr,(IMM d, RR2 s)) { @@ -2683,7 +2532,6 @@ LOWFUNC(NONE,WRITE,2,compemu_raw_mov_w_mr,(IMM d, RR2 s)) //: #endif } -LENDFUNC(NONE,WRITE,2,compemu_raw_mov_w_mr,(IMM d, RR2 s)) LOWFUNC(WRITE,RMW,2,compemu_raw_sub_l_mi,(MEMRW d, IMM s)) { @@ -2722,13 +2570,11 @@ LOWFUNC(WRITE,RMW,2,compemu_raw_sub_l_mi,(MEMRW d, IMM s)) //: #endif } -LENDFUNC(WRITE,RMW,2,compemu_raw_sub_l_mi,(MEMRW d, IMM s)) LOWFUNC(WRITE,NONE,2,compemu_raw_test_l_rr,(RR4 d, RR4 s)) { TST_rr(d, s); // tst r7, r6 } -LENDFUNC(WRITE,NONE,2,compemu_raw_test_l_rr,(RR4 d, RR4 s)) LOWFUNC(NONE,NONE,2,compemu_raw_zero_extend_16_rr,(W4 d, RR2 s)) { @@ -2739,7 +2585,6 @@ LOWFUNC(NONE,NONE,2,compemu_raw_zero_extend_16_rr,(W4 d, RR2 s)) BIC_rri(d, d, 0x00ff0000); // bic %[d], %[d], #0x00ff0000 #endif } -LENDFUNC(NONE,NONE,2,compemu_raw_zero_extend_16_rr,(W4 d, RR2 s)) static inline void compemu_raw_call(uae_u32 t) { diff --git a/BasiliskII/src/uae_cpu/compiler/codegen_arm.h b/BasiliskII/src/uae_cpu/compiler/codegen_arm.h index f92bb1da..e04ab9b8 100644 --- a/BasiliskII/src/uae_cpu/compiler/codegen_arm.h +++ b/BasiliskII/src/uae_cpu/compiler/codegen_arm.h @@ -66,22 +66,22 @@ /* --- ENCODINGS ----------------------------------------------------------- */ /* ========================================================================= */ -#define IMM32(c) ((c & 0xffffff00) == 0 ? c : \ - (c & 0x3fffffc0) == 0 ? (0x100 | ((c >> 30) & 0x3) | ((c << 2) & 0xfc)) : \ - (c & 0x0ffffff0) == 0 ? (0x200 | ((c >> 28) & 0xf) | ((c << 4) & 0xf0)) : \ - (c & 0x03fffffc) == 0 ? (0x300 | ((c >> 26) & 0x3f) | ((c << 6) & 0xc0) ) : \ - (c & 0x00ffffff) == 0 ? (0x400 | ((c >> 24) & 0xff)) : \ - (c & 0xc03fffff) == 0 ? (0x500 | (c >> 22)) : \ - (c & 0xf00fffff) == 0 ? (0x600 | (c >> 20)) : \ - (c & 0xfc03ffff) == 0 ? (0x700 | (c >> 18)) : \ - (c & 0xff00ffff) == 0 ? (0x800 | (c >> 16)) : \ - (c & 0xffc03fff) == 0 ? (0x900 | (c >> 14)) : \ - (c & 0xfff00fff) == 0 ? (0xa00 | (c >> 12)) : \ - (c & 0xfffc03ff) == 0 ? (0xb00 | (c >> 10)) : \ - (c & 0xffff00ff) == 0 ? (0xc00 | (c >> 8)) : \ - (c & 0xffffc03f) == 0 ? (0xd00 | (c >> 6)) : \ - (c & 0xfffff00f) == 0 ? (0xe00 | (c >> 4)) : \ - (c & 0xfffffc03) == 0 ? (0xf00 | (c >> 2)) : \ +#define IMM32(c) (((c) & 0xffffff00) == 0 ? (c) : \ + ((c) & 0x3fffffc0) == 0 ? (0x100 | (((c) >> 30) & 0x3) | ((((c) & 0x0000003f) << 2))) : \ + ((c) & 0x0ffffff0) == 0 ? (0x200 | (((c) >> 28) & 0xf) | ((((c) & 0x0000000f) << 4))) : \ + ((c) & 0x03fffffc) == 0 ? (0x300 | (((c) >> 26) & 0x3f) | ((((c) & 0x00000003) << 6)) ) : \ + ((c) & 0x00ffffff) == 0 ? (0x400 | (((c) >> 24) & 0xff)) : \ + ((c) & 0xc03fffff) == 0 ? (0x500 | ((c) >> 22)) : \ + ((c) & 0xf00fffff) == 0 ? (0x600 | ((c) >> 20)) : \ + ((c) & 0xfc03ffff) == 0 ? (0x700 | ((c) >> 18)) : \ + ((c) & 0xff00ffff) == 0 ? (0x800 | ((c) >> 16)) : \ + ((c) & 0xffc03fff) == 0 ? (0x900 | ((c) >> 14)) : \ + ((c) & 0xfff00fff) == 0 ? (0xa00 | ((c) >> 12)) : \ + ((c) & 0xfffc03ff) == 0 ? (0xb00 | ((c) >> 10)) : \ + ((c) & 0xffff00ff) == 0 ? (0xc00 | ((c) >> 8)) : \ + ((c) & 0xffffc03f) == 0 ? (0xd00 | ((c) >> 6)) : \ + ((c) & 0xfffff00f) == 0 ? (0xe00 | ((c) >> 4)) : \ + ((c) & 0xfffffc03) == 0 ? (0xf00 | ((c) >> 2)) : \ 0\ ) @@ -102,7 +102,7 @@ #define SHIFT_RRX(Rm) ((Rm) | 0x60) #define SHIFT_PK(Rm,s) ((Rm) | ((s) << 7)) -// Load/Store addressings +/* Load/Store addressings */ #define ADR_ADD(v) ((1 << 23) | (v)) #define ADR_SUB(v) (v) @@ -138,16 +138,16 @@ #define ADD2_REG(Rm) ADR_ADD(Rm) #define SUB2_REG(Rm) ADR_SUB(Rm) -// MOV, MVN +/* MOV, MVN */ #define _OP1(cc,op,s,Rd,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rd) << 12) | (shift)) -// CMP, CMN, TST, TEQ +/* CMP, CMN, TST, TEQ */ #define _OP2(cc,op,Rn,shift) _W(((cc) << 28) | ((op) << 21) | (1 << 20) | ((Rn) << 16) | (shift)) -// ADD, SUB, RSB, ADC, SBC, RSC, AND, BIC, EOR, ORR +/* ADD, SUB, RSB, ADC, SBC, RSC, AND, BIC, EOR, ORR */ #define _OP3(cc,op,s,Rd,Rn,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rn) << 16) | ((Rd) << 12) | (shift)) -// LDR, STR +/* LDR, STR */ #define _LS1(cc,l,b,Rd,Rn,a) _W(((cc) << 28) | (0x01 << 26) | ((l) << 20) | ((b) << 22) | ((Rn) << 16) | ((Rd) << 12) | (a)) #define _LS2(cc,p,l,s,h,Rd,Rn,a) _W(((cc) << 28) | ((p) << 24) | ((l) << 20) | ((Rn) << 16) | ((Rd) << 12) | ((s) << 6) | ((h) << 5) | 0x90 | _LS2_ADDR((a))) @@ -211,9 +211,9 @@ enum { /* Data processing instructions */ /* Opcodes Type 1 */ -// MOVcc rd,#i +/* MOVcc rd,#i */ #define CC_MOV_ri8(cc,Rd,i) _OP1(cc,_MOV,0,Rd,UNSHIFTED_IMM8(i)) -// MOVcc Rd,#i ROR #s +/* MOVcc Rd,#i ROR #s */ #define CC_MOV_ri8RORi(cc,Rd,i,s) _OP1(cc,_MOV,0,Rd,SHIFT_IMM8_ROR(i,s)) #define CC_MOV_ri(cc,Rd,i) _OP1(cc,_MOV,0,Rd,SHIFT_IMM(i)) #define CC_MOV_rr(cc,Rd,Rm) _OP1(cc,_MOV,0,Rd,SHIFT_REG(Rm)) @@ -227,9 +227,9 @@ enum { #define CC_MOV_rrRORr(cc,Rd,Rm,Rs) _OP1(cc,_MOV,0,Rd,SHIFT_ROR_r(Rm,Rs)) #define CC_MOV_rrRRX(cc,Rd,Rm) _OP1(cc,_MOV,0,Rd,SHIFT_RRX(Rm)) -// MOV rd,#i +/* MOV rd,#i */ #define MOV_ri8(Rd,i) CC_MOV_ri8(NATIVE_CC_AL,Rd,i) -// MOV Rd,#i ROR #s +/* MOV Rd,#i ROR #s */ #define MOV_ri8RORi(Rd,i,s) CC_MOV_ri8RORi(NATIVE_CC_AL,Rd,i,s) #define MOV_ri(Rd,i) CC_MOV_ri(NATIVE_CC_AL,Rd,i) #define MOV_rr(Rd,Rm) CC_MOV_rr(NATIVE_CC_AL,Rd,Rm) @@ -267,9 +267,9 @@ enum { #define MOVS_rrRORr(Rd,Rm,Rs) CC_MOVS_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs) #define MOVS_rrRRX(Rd,Rm) CC_MOVS_rrRRX(NATIVE_CC_AL,Rd,Rm) -// MVNcc rd,#i +/* MVNcc rd,#i */ #define CC_MVN_ri8(cc,Rd,i) _OP1(cc,_MVN,0,Rd,UNSHIFTED_IMM8(i)) -// MVNcc Rd,#i ROR #s +/* MVNcc Rd,#i ROR #s */ #define CC_MVN_ri8RORi(cc,Rd,i,s) _OP1(cc,_MVN,0,Rd,SHIFT_IMM8_ROR(i,s)) #define CC_MVN_ri(cc,Rd,i) _OP1(cc,_MVN,0,Rd,SHIFT_IMM(i)) #define CC_MVN_rr(cc,Rd,Rm) _OP1(cc,_MVN,0,Rd,SHIFT_REG(Rm)) @@ -283,9 +283,9 @@ enum { #define CC_MVN_rrRORr(cc,Rd,Rm,Rs) _OP1(cc,_MVN,0,Rd,SHIFT_ROR_r(Rm,Rs)) #define CC_MVN_rrRRX(cc,Rd,Rm) _OP1(cc,_MVN,0,Rd,SHIFT_RRX(Rm)) -// MVN rd,#i +/* MVN rd,#i */ #define MVN_ri8(Rd,i) CC_MVN_ri8(NATIVE_CC_AL,Rd,i) -// MVN Rd,#i ROR #s +/* MVN Rd,#i ROR #s */ #define MVN_ri8RORi(Rd,i,s) CC_MVN_ri8RORi(NATIVE_CC_AL,Rd,i,s) #define MVN_ri(Rd,i) CC_MVN_ri(NATIVE_CC_AL,Rd,i) #define MVN_rr(Rd,Rm) CC_MVN_rr(NATIVE_CC_AL,Rd,Rm) @@ -811,9 +811,9 @@ enum { #define RSCS_rrrRORr(Rd,Rn,Rm,Rs) CC_RSCS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs) #define RSCS_rrrRRX(Rd,Rn,Rm) CC_RSCS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm) -// ORRcc Rd,Rn,#i +/* ORRcc Rd,Rn,#i */ #define CC_ORR_rri8(cc,Rd,Rn,i) _OP3(cc,_ORR,0,Rd,Rn,UNSHIFTED_IMM8(i)) -// ORRcc Rd,Rn,#i ROR #s +/* ORRcc Rd,Rn,#i ROR #s */ #define CC_ORR_rri8RORi(cc,Rd,Rn,i,s) _OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM8_ROR(i,s)) #define CC_ORR_rri(cc,Rd,Rn,i) _OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM(i)) @@ -828,9 +828,9 @@ enum { #define CC_ORR_rrrRORr(cc,Rd,Rn,Rm,Rs) _OP3(cc,_ORR,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs)) #define CC_ORR_rrrRRX(cc,Rd,Rn,Rm) _OP3(cc,_ORR,0,Rd,Rn,SHIFT_RRX(Rm)) -// ORR Rd,Rn,#i +/* ORR Rd,Rn,#i */ #define ORR_rri8(Rd,Rn,i) CC_ORR_rri8(NATIVE_CC_AL,Rd,Rn,i) -// ORR Rd,Rn,#i ROR #s +/* ORR Rd,Rn,#i ROR #s */ #define ORR_rri8RORi(Rd,Rn,i,s) CC_ORR_rri8RORi(NATIVE_CC_AL,Rd,Rn,i,s) #define ORR_rri(Rd,Rn,i) CC_ORR_rri(NATIVE_CC_AL,Rd,Rn,i) diff --git a/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp b/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp index 24cfb548..573f2f9a 100644 --- a/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp +++ b/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp @@ -107,6 +107,10 @@ #if defined(CPU_x86_64) #ifdef UAE +/* Register R12 (and ESP) cannot be used with simple [r/m + disp32] addressing, + * since r/m bits 100 implies SIB byte. Simplest fix is to not use these + * registers. Also note that these registers are listed in the freescratch + * function as well. */ uae_s8 always_used[] = { ESP_INDEX, R12_INDEX, -1 }; #else uae_s8 always_used[] = { ESP_INDEX, -1 }; @@ -192,11 +196,6 @@ static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,1,1}; #define CLOBBER_BT clobber_flags() #define CLOBBER_BSF clobber_flags() -/* The older code generator is now deprecated. */ -#define USE_NEW_RTASM 1 - -#if USE_NEW_RTASM - #if defined(CPU_x86_64) #define X86_TARGET_64BIT 1 /* The address override prefix causes a 5 cycles penalty on Intel Core @@ -296,7 +295,6 @@ LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) PUSHLr(r); #endif } -LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) { @@ -306,7 +304,6 @@ LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) POPLr(r); #endif } -LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d)) { @@ -316,307 +313,256 @@ LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d)) POPLm(d, X86_NOREG, X86_NOREG, 1); #endif } -LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d)) LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) { BTLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) { BTLrr(b, r); } -LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) { BTCLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) { BTCLrr(b, r); } -LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) { BTRLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) { BTRLrr(b, r); } -LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) { BTSLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) { BTSLrr(b, r); } -LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) { SUBWir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) { ADDR32 MOVLmr(s, X86_NOREG, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) { ADDR32 MOVLim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) { ADDR32 MOVWim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) { ADDR32 MOVBim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) { ADDR32 ROLBim(i, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) { ROLBir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) { ROLWir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) { ROLLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) { ROLLrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) { ROLWrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) { ROLBrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) { SHLLrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) { SHLWrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) { SHLBrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) { RORBir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) { RORWir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) { ADDR32 ORLmr(s, X86_NOREG, X86_NOREG, 1, d); } -LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) { RORLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) { RORLrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) { RORWrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) { RORBrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) { SHRLrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) { SHRWrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) { SHRBrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) { SARLrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) { SARWrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) { SARBrr(r, d); } -LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) { SHLLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) { SHLWir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) { SHLBir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) { SHRLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) { SHRWir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) { SHRBir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) { SARLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) { SARWir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) { SARBir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) LOWFUNC(WRITE,NONE,1,raw_sahf,(R2)) { SAHF(); } -LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah)) LOWFUNC(NONE,NONE,1,raw_cpuid,(R4)) { CPUID(); } -LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax)) LOWFUNC(READ,NONE,1,raw_lahf,(W2)) { LAHF(); } -LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah)) LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) { SETCCir(cc, d); } -LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) { ADDR32 SETCCim(cc, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) { @@ -629,49 +575,41 @@ LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1); } } -LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) { BSFLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) LOWFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s)) { MOVSLQrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s)) LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) { MOVSWLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) { MOVSBLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) { MOVZWLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) { MOVZBLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) { IMULLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) { @@ -680,7 +618,6 @@ LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) } IMULLr(s); } -LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) { @@ -689,103 +626,86 @@ LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) } MULLr(s); } -LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4, R4)) { - abort(); /* %^$&%^$%#^ x86! */ + x86_emit_failure("raw_mul_32_32"); /* %^$&%^$%#^ x86! */ } -LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s)) LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) { MOVBrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) { MOVWrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) { ADDR32 MOVLmr(0, baser, index, factor, d); } -LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) { ADDR32 MOVWmr(0, baser, index, factor, d); } -LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) { ADDR32 MOVBmr(0, baser, index, factor, d); } -LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) { ADDR32 MOVLrm(s, 0, baser, index, factor); } -LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) { ADDR32 MOVWrm(s, 0, baser, index, factor); } -LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) { ADDR32 MOVBrm(s, 0, baser, index, factor); } -LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) { ADDR32 MOVLrm(s, base, baser, index, factor); } -LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) { ADDR32 MOVWrm(s, base, baser, index, factor); } -LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) { ADDR32 MOVBrm(s, base, baser, index, factor); } -LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) { ADDR32 MOVLmr(base, baser, index, factor, d); } -LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) { ADDR32 MOVWmr(base, baser, index, factor, d); } -LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) { ADDR32 MOVBmr(base, baser, index, factor, d); } -LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) { ADDR32 MOVLmr(base, X86_NOREG, index, factor, d); } -LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) { @@ -798,7 +718,6 @@ LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1); } } -LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) { @@ -811,493 +730,411 @@ LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1); } } -LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) { ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) { ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) { ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) { ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) { ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) { ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) { ADDR32 MOVLim(i, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) { ADDR32 MOVWim(i, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) { ADDR32 MOVBim(i, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) { ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) { ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) { ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) { ADDR32 LEALmr(offset, s, X86_NOREG, 1, d); } -LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) { ADDR32 LEALmr(offset, s, index, factor, d); } -LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) { ADDR32 LEALmr(0, s, index, factor, d); } -LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) LOWFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor)) { ADDR32 LEALmr(0, X86_NOREG, index, factor, d); } -LENDFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor)) LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) { ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) { ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) { ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) { BSWAPLr(r); } -LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) { ROLWir(8, r); } -LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) { MOVLrr(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) { ADDR32 MOVLrm(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) { ADDR32 MOVWrm(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) { ADDR32 MOVWmr(s, X86_NOREG, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) { ADDR32 MOVBrm(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) { ADDR32 MOVBmr(s, X86_NOREG, X86_NOREG, 1, d); } -LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) { MOVLir(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) { MOVWir(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) { MOVBir(s, d); } -LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) { ADDR32 ADCLim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) { ADDR32 ADDLim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) { ADDR32 ADDWim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) { ADDR32 ADDBim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) { TESTLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) { TESTLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) { TESTWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) { TESTBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i)) { XORLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) { ANDLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) { ANDWir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) { ANDLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) { ANDWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) { ANDBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) { ORLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) { ORLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) { ORWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) { ORBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) { ADCLrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) { ADCWrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) { ADCBrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) { ADDLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) { ADDWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) { ADDBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) { SUBLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) { SUBBir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) { ADDLir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) { ADDWir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) { ADDBir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) { SBBLrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) { SBBWrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) { SBBBrr(s, d); } -LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) { SUBLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) { SUBWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) { SUBBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) { CMPLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) { CMPLir(i, r); } -LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) { CMPWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s)) { ADDR32 CMPBim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s)) LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) { CMPBir(i, d); } -LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) { CMPBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) { ADDR32 CMPLmr(offset, X86_NOREG, index, factor, d); } -LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) { XORLrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) { XORWrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) { XORBrr(s, d); } -LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) { ADDR32 SUBLim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) { ADDR32 CMPLim(s, d, X86_NOREG, X86_NOREG, 1); } -LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) { XCHGLrr(r2, r1); } -LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2)) { XCHGBrr(r2, r1); } -LENDFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2)) LOWFUNC(READ,WRITE,0,raw_pushfl,(void)) { PUSHF(); } -LENDFUNC(READ,WRITE,0,raw_pushfl,(void)) LOWFUNC(WRITE,READ,0,raw_popfl,(void)) { POPF(); } -LENDFUNC(WRITE,READ,0,raw_popfl,(void)) /* Generate floating-point instructions */ static inline void x86_fadd_m(MEMR s) @@ -1305,1796 +1142,6 @@ static inline void x86_fadd_m(MEMR s) ADDR32 FADDLm(s,X86_NOREG,X86_NOREG,1); } -#else - -const bool optimize_accum = true; -const bool optimize_imm8 = true; -const bool optimize_shift_once = true; - -/************************************************************************* - * Actual encoding of the instructions on the target CPU * - *************************************************************************/ - -static inline int isaccum(int r) -{ - return (r == EAX_INDEX); -} - -static inline int isbyte(uae_s32 x) -{ - return (x>=-128 && x<=127); -} - -static inline int isword(uae_s32 x) -{ - return (x>=-32768 && x<=32767); -} - -LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) -{ - emit_byte(0x50+r); -} -LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) - -LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) -{ - emit_byte(0x58+r); -} -LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) - -LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d)) -{ - emit_byte(0x8f); - emit_byte(0x05); - emit_long(d); -} -LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d)) - -LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) -{ - emit_byte(0x0f); - emit_byte(0xba); - emit_byte(0xe0+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) -{ - emit_byte(0x0f); - emit_byte(0xa3); - emit_byte(0xc0+8*b+r); -} -LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) - -LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) -{ - emit_byte(0x0f); - emit_byte(0xba); - emit_byte(0xf8+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) -{ - emit_byte(0x0f); - emit_byte(0xbb); - emit_byte(0xc0+8*b+r); -} -LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) - - -LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) -{ - emit_byte(0x0f); - emit_byte(0xba); - emit_byte(0xf0+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) -{ - emit_byte(0x0f); - emit_byte(0xb3); - emit_byte(0xc0+8*b+r); -} -LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) - -LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) -{ - emit_byte(0x0f); - emit_byte(0xba); - emit_byte(0xe8+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) -{ - emit_byte(0x0f); - emit_byte(0xab); - emit_byte(0xc0+8*b+r); -} -LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) - -LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) -{ - emit_byte(0x66); - if (isbyte(i)) { - emit_byte(0x83); - emit_byte(0xe8+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x2d); - else { - emit_byte(0x81); - emit_byte(0xe8+d); - } - emit_word(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) - - -LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) -{ - emit_byte(0x8b); - emit_byte(0x05+8*d); - emit_long(s); -} -LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) -{ - emit_byte(0xc7); - emit_byte(0x05); - emit_long(d); - emit_long(s); -} -LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) -{ - emit_byte(0x66); - emit_byte(0xc7); - emit_byte(0x05); - emit_long(d); - emit_word(s); -} -LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) -{ - emit_byte(0xc6); - emit_byte(0x05); - emit_long(d); - emit_byte(s); -} -LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) - -LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0x05); - emit_long(d); - } - else { - emit_byte(0xc0); - emit_byte(0x05); - emit_long(d); - emit_byte(i); - } -} -LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0xc0+r); - } - else { - emit_byte(0xc0); - emit_byte(0xc0+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xc0+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd1); - emit_byte(0xc0+r); - } - else { - emit_byte(0xc1); - emit_byte(0xc0+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) -{ - emit_byte(0xd3); - emit_byte(0xc0+d); -} -LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) -{ - emit_byte(0x66); - emit_byte(0xd3); - emit_byte(0xc0+d); -} -LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) -{ - emit_byte(0xd2); - emit_byte(0xc0+d); -} -LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) -{ - emit_byte(0xd3); - emit_byte(0xe0+d); -} -LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) -{ - emit_byte(0x66); - emit_byte(0xd3); - emit_byte(0xe0+d); -} -LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) -{ - emit_byte(0xd2); - emit_byte(0xe0+d); -} -LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0xc8+r); - } - else { - emit_byte(0xc0); - emit_byte(0xc8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xc8+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) - -// gb-- used for making an fpcr value in compemu_fpp.cpp -LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) -{ - emit_byte(0x0b); - emit_byte(0x05+8*d); - emit_long(s); -} -LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) - -LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd1); - emit_byte(0xc8+r); - } - else { - emit_byte(0xc1); - emit_byte(0xc8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) -{ - emit_byte(0xd3); - emit_byte(0xc8+d); -} -LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) -{ - emit_byte(0x66); - emit_byte(0xd3); - emit_byte(0xc8+d); -} -LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) -{ - emit_byte(0xd2); - emit_byte(0xc8+d); -} -LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) -{ - emit_byte(0xd3); - emit_byte(0xe8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) -{ - emit_byte(0x66); - emit_byte(0xd3); - emit_byte(0xe8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) -{ - emit_byte(0xd2); - emit_byte(0xe8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) -{ - emit_byte(0xd3); - emit_byte(0xf8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) -{ - emit_byte(0x66); - emit_byte(0xd3); - emit_byte(0xf8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) -{ - emit_byte(0xd2); - emit_byte(0xf8+d); -} -LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) - -LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd1); - emit_byte(0xe0+r); - } - else { - emit_byte(0xc1); - emit_byte(0xe0+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xe0+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0xe0+r); - } - else { - emit_byte(0xc0); - emit_byte(0xe0+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd1); - emit_byte(0xe8+r); - } - else { - emit_byte(0xc1); - emit_byte(0xe8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xe8+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0xe8+r); - } - else { - emit_byte(0xc0); - emit_byte(0xe8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd1); - emit_byte(0xf8+r); - } - else { - emit_byte(0xc1); - emit_byte(0xf8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xf8+r); - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) -{ - if (optimize_shift_once && (i == 1)) { - emit_byte(0xd0); - emit_byte(0xf8+r); - } - else { - emit_byte(0xc0); - emit_byte(0xf8+r); - emit_byte(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) - -LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah)) -{ - emit_byte(0x9e); -} -LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah)) - -LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax)) -{ - emit_byte(0x0f); - emit_byte(0xa2); -} -LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax)) - -LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah)) -{ - emit_byte(0x9f); -} -LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah)) - -LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) -{ - emit_byte(0x0f); - emit_byte(0x90+cc); - emit_byte(0xc0+d); -} -LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) - -LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) -{ - emit_byte(0x0f); - emit_byte(0x90+cc); - emit_byte(0x05); - emit_long(d); -} -LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) - -LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) -{ - if (have_cmov) { - emit_byte(0x0f); - emit_byte(0x40+cc); - emit_byte(0xc0+8*d+s); - } - else { /* replacement using branch and mov */ - int uncc=(cc^1); - emit_byte(0x70+uncc); - emit_byte(2); /* skip next 2 bytes if not cc=true */ - emit_byte(0x89); - emit_byte(0xc0+8*s+d); - } -} -LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) - -LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) -{ - emit_byte(0x0f); - emit_byte(0xbc); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) - -LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) -{ - emit_byte(0x0f); - emit_byte(0xbf); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) - -LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) -{ - emit_byte(0x0f); - emit_byte(0xbe); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) - -LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) -{ - emit_byte(0x0f); - emit_byte(0xb7); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) - -LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) -{ - emit_byte(0x0f); - emit_byte(0xb6); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) - -LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) -{ - emit_byte(0x0f); - emit_byte(0xaf); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) - -LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) -{ - if (d!=MUL_NREG1 || s!=MUL_NREG2) { - jit_abort("Bad register in IMUL: d=%d, s=%d\n",d,s); - } - emit_byte(0xf7); - emit_byte(0xea); -} -LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) - -LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) -{ - if (d!=MUL_NREG1 || s!=MUL_NREG2) { - jit_abort("Bad register in MUL: d=%d, s=%d",d,s); - } - emit_byte(0xf7); - emit_byte(0xe2); -} -LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) - -LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s)) -{ - jit_abort("unsupported MUL"); /* %^$&%^$%#^ x86! */ - emit_byte(0x0f); - emit_byte(0xaf); - emit_byte(0xc0+8*d+s); -} -LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s)) - -LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) -{ - emit_byte(0x88); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) - -LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) - -LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) -{ - int isebp=(baser==5)?0x40:0; - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - - emit_byte(0x8b); - emit_byte(0x04+8*d+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) -{ - int fi; - int isebp; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - isebp=(baser==5)?0x40:0; - - emit_byte(0x66); - emit_byte(0x8b); - emit_byte(0x04+8*d+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) -{ - int fi; - int isebp; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - isebp=(baser==5)?0x40:0; - - emit_byte(0x8a); - emit_byte(0x04+8*d+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) -{ - int fi; - int isebp; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - - isebp=(baser==5)?0x40:0; - - emit_byte(0x89); - emit_byte(0x04+8*s+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) - -LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) -{ - int fi; - int isebp; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - isebp=(baser==5)?0x40:0; - - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0x04+8*s+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) - -LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) -{ - int fi; - int isebp; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - isebp=(baser==5)?0x40:0; - - emit_byte(0x88); - emit_byte(0x04+8*s+isebp); - emit_byte(baser+8*index+0x40*fi); - if (isebp) - emit_byte(0x00); -} -LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) - -LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x89); - emit_byte(0x84+8*s); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) - -LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0x84+8*s); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) - -LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x88); - emit_byte(0x84+8*s); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) - -LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x8b); - emit_byte(0x84+8*d); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x66); - emit_byte(0x8b); - emit_byte(0x84+8*d); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x8a); - emit_byte(0x84+8*d); - emit_byte(baser+8*index+0x40*fi); - emit_long(base); -} -LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) -{ - int fi; - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: - jit_abort("Bad factor %d in mov_l_rm_indexed!",factor); - } - emit_byte(0x8b); - emit_byte(0x04+8*d); - emit_byte(0x05+8*index+64*fi); - emit_long(base); -} -LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) - -LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) -{ - int fi; - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: - jit_abort("Bad factor %d in mov_l_rm_indexed!",factor); - } - if (have_cmov) { - emit_byte(0x0f); - emit_byte(0x40+cond); - emit_byte(0x04+8*d); - emit_byte(0x05+8*index+64*fi); - emit_long(base); - } - else { /* replacement using branch and mov */ - int uncc=(cond^1); - emit_byte(0x70+uncc); - emit_byte(7); /* skip next 7 bytes if not cc=true */ - emit_byte(0x8b); - emit_byte(0x04+8*d); - emit_byte(0x05+8*index+64*fi); - emit_long(base); - } -} -LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) - -LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) -{ - if (have_cmov) { - emit_byte(0x0f); - emit_byte(0x40+cond); - emit_byte(0x05+8*d); - emit_long(mem); - } - else { /* replacement using branch and mov */ - int uncc=(cond^1); - emit_byte(0x70+uncc); - emit_byte(6); /* skip next 6 bytes if not cc=true */ - emit_byte(0x8b); - emit_byte(0x05+8*d); - emit_long(mem); - } -} -LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) - -LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x8b); - emit_byte(0x40+8*d+s); - emit_byte(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) - -LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x66); - emit_byte(0x8b); - emit_byte(0x40+8*d+s); - emit_byte(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) - -LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x8a); - emit_byte(0x40+8*d+s); - emit_byte(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) - -LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) -{ - emit_byte(0x8b); - emit_byte(0x80+8*d+s); - emit_long(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) - -LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) -{ - emit_byte(0x66); - emit_byte(0x8b); - emit_byte(0x80+8*d+s); - emit_long(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) - -LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) -{ - emit_byte(0x8a); - emit_byte(0x80+8*d+s); - emit_long(offset); -} -LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0xc7); - emit_byte(0x40+d); - emit_byte(offset); - emit_long(i); -} -LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x66); - emit_byte(0xc7); - emit_byte(0x40+d); - emit_byte(offset); - emit_word(i); -} -LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0xc6); - emit_byte(0x40+d); - emit_byte(offset); - emit_byte(i); -} -LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x89); - emit_byte(0x40+8*s+d); - emit_byte(offset); -} -LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0x40+8*s+d); - emit_byte(offset); -} -LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) -{ - Dif(!isbyte(offset)) abort(); - emit_byte(0x88); - emit_byte(0x40+8*s+d); - emit_byte(offset); -} -LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) - -LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) -{ - if (optimize_imm8 && isbyte(offset)) { - emit_byte(0x8d); - emit_byte(0x40+8*d+s); - emit_byte(offset); - } - else { - emit_byte(0x8d); - emit_byte(0x80+8*d+s); - emit_long(offset); - } -} -LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) - -LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - if (optimize_imm8 && isbyte(offset)) { - emit_byte(0x8d); - emit_byte(0x44+8*d); - emit_byte(0x40*fi+8*index+s); - emit_byte(offset); - } - else { - emit_byte(0x8d); - emit_byte(0x84+8*d); - emit_byte(0x40*fi+8*index+s); - emit_long(offset); - } -} -LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) - -LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) -{ - int isebp=(s==5)?0x40:0; - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - - emit_byte(0x8d); - emit_byte(0x04+8*d+isebp); - emit_byte(0x40*fi+8*index+s); - if (isebp) - emit_byte(0); -} -LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) - -LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) -{ - if (optimize_imm8 && isbyte(offset)) { - emit_byte(0x89); - emit_byte(0x40+8*s+d); - emit_byte(offset); - } - else { - emit_byte(0x89); - emit_byte(0x80+8*s+d); - emit_long(offset); - } -} -LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) -{ - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0x80+8*s+d); - emit_long(offset); -} -LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) - -LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) -{ - if (optimize_imm8 && isbyte(offset)) { - emit_byte(0x88); - emit_byte(0x40+8*s+d); - emit_byte(offset); - } - else { - emit_byte(0x88); - emit_byte(0x80+8*s+d); - emit_long(offset); - } -} -LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) - -LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) -{ - emit_byte(0x0f); - emit_byte(0xc8+r); -} -LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) - -LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) -{ - emit_byte(0x66); - emit_byte(0xc1); - emit_byte(0xc0+r); - emit_byte(0x08); -} -LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) - -LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) -{ - emit_byte(0x89); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) -{ - emit_byte(0x89); - emit_byte(0x05+8*s); - emit_long(d); -} -LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x89); - emit_byte(0x05+8*s); - emit_long(d); -} -LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) - -LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) -{ - emit_byte(0x66); - emit_byte(0x8b); - emit_byte(0x05+8*d); - emit_long(s); -} -LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) - -LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) -{ - emit_byte(0x88); - emit_byte(0x05+8*(s&0xf)); /* XXX this handles %ah case (defined as 0x10+4) and others */ - emit_long(d); -} -LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) - -LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) -{ - emit_byte(0x8a); - emit_byte(0x05+8*d); - emit_long(s); -} -LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) - -LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) -{ - emit_byte(0xb8+d); - emit_long(s); -} -LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) - -LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) -{ - emit_byte(0x66); - emit_byte(0xb8+d); - emit_word(s); -} -LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) - -LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) -{ - emit_byte(0xb0+d); - emit_byte(s); -} -LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) - -LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) -{ - emit_byte(0x81); - emit_byte(0x15); - emit_long(d); - emit_long(s); -} -LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) - -LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) -{ - if (optimize_imm8 && isbyte(s)) { - emit_byte(0x83); - emit_byte(0x05); - emit_long(d); - emit_byte(s); - } - else { - emit_byte(0x81); - emit_byte(0x05); - emit_long(d); - emit_long(s); - } -} -LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) - -LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) -{ - emit_byte(0x66); - emit_byte(0x81); - emit_byte(0x05); - emit_long(d); - emit_word(s); -} -LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) - -LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) -{ - emit_byte(0x80); - emit_byte(0x05); - emit_long(d); - emit_byte(s); -} -LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) - -LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) -{ - if (optimize_accum && isaccum(d)) - emit_byte(0xa9); - else { - emit_byte(0xf7); - emit_byte(0xc0+d); - } - emit_long(i); -} -LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) -{ - emit_byte(0x85); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x85); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) -{ - emit_byte(0x84); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i)) -{ - emit_byte(0x81); - emit_byte(0xf0+d); - emit_long(i); -} -LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) -{ - if (optimize_imm8 && isbyte(i)) { - emit_byte(0x83); - emit_byte(0xe0+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x25); - else { - emit_byte(0x81); - emit_byte(0xe0+d); - } - emit_long(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) -{ - emit_byte(0x66); - if (optimize_imm8 && isbyte(i)) { - emit_byte(0x83); - emit_byte(0xe0+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x25); - else { - emit_byte(0x81); - emit_byte(0xe0+d); - } - emit_word(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) -{ - emit_byte(0x21); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x21); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) -{ - emit_byte(0x20); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) -{ - if (optimize_imm8 && isbyte(i)) { - emit_byte(0x83); - emit_byte(0xc8+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x0d); - else { - emit_byte(0x81); - emit_byte(0xc8+d); - } - emit_long(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) -{ - emit_byte(0x09); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x09); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) -{ - emit_byte(0x08); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) - -LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) -{ - emit_byte(0x11); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) - -LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x11); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) - -LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) -{ - emit_byte(0x10); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) -{ - emit_byte(0x01); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x01); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) -{ - emit_byte(0x00); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) -{ - if (isbyte(i)) { - emit_byte(0x83); - emit_byte(0xe8+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x2d); - else { - emit_byte(0x81); - emit_byte(0xe8+d); - } - emit_long(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) -{ - if (optimize_accum && isaccum(d)) - emit_byte(0x2c); - else { - emit_byte(0x80); - emit_byte(0xe8+d); - } - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) -{ - if (isbyte(i)) { - emit_byte(0x83); - emit_byte(0xc0+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x05); - else { - emit_byte(0x81); - emit_byte(0xc0+d); - } - emit_long(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) -{ - emit_byte(0x66); - if (isbyte(i)) { - emit_byte(0x83); - emit_byte(0xc0+d); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(d)) - emit_byte(0x05); - else { - emit_byte(0x81); - emit_byte(0xc0+d); - } - emit_word(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) -{ - if (optimize_accum && isaccum(d)) - emit_byte(0x04); - else { - emit_byte(0x80); - emit_byte(0xc0+d); - } - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) - -LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) -{ - emit_byte(0x19); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) - -LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x19); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) - -LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) -{ - emit_byte(0x18); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) -{ - emit_byte(0x29); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x29); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) -{ - emit_byte(0x28); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) -{ - emit_byte(0x39); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) -{ - if (optimize_imm8 && isbyte(i)) { - emit_byte(0x83); - emit_byte(0xf8+r); - emit_byte(i); - } - else { - if (optimize_accum && isaccum(r)) - emit_byte(0x3d); - else { - emit_byte(0x81); - emit_byte(0xf8+r); - } - emit_long(i); - } -} -LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x39); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) - -LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s)) -{ - emit_byte(0x80); - emit_byte(0x3d); - emit_long(d); - emit_byte(s); -} -LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) - -LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) -{ - if (optimize_accum && isaccum(d)) - emit_byte(0x3c); - else { - emit_byte(0x80); - emit_byte(0xf8+d); - } - emit_byte(i); -} -LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) - -LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) -{ - emit_byte(0x38); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) - -LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) -{ - int fi; - - switch(factor) { - case 1: fi=0; break; - case 2: fi=1; break; - case 4: fi=2; break; - case 8: fi=3; break; - default: abort(); - } - emit_byte(0x39); - emit_byte(0x04+8*d); - emit_byte(5+8*index+0x40*fi); - emit_long(offset); -} -LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) - -LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) -{ - emit_byte(0x31); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) - -LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) -{ - emit_byte(0x66); - emit_byte(0x31); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) - -LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) -{ - emit_byte(0x30); - emit_byte(0xc0+8*s+d); -} -LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) - -LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) -{ - if (optimize_imm8 && isbyte(s)) { - emit_byte(0x83); - emit_byte(0x2d); - emit_long(d); - emit_byte(s); - } - else { - emit_byte(0x81); - emit_byte(0x2d); - emit_long(d); - emit_long(s); - } -} -LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) - -LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) -{ - if (optimize_imm8 && isbyte(s)) { - emit_byte(0x83); - emit_byte(0x3d); - emit_long(d); - emit_byte(s); - } - else { - emit_byte(0x81); - emit_byte(0x3d); - emit_long(d); - emit_long(s); - } -} -LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) - -LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) -{ - emit_byte(0x87); - emit_byte(0xc0+8*r1+r2); -} -LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) - -LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2)) -{ - emit_byte(0x86); - emit_byte(0xc0+8*(r1&0xf)+(r2&0xf)); /* XXX this handles upper-halves registers (e.g. %ah defined as 0x10+4) */ -} -LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) - -/************************************************************************* - * FIXME: mem access modes probably wrong * - *************************************************************************/ - -LOWFUNC(READ,WRITE,0,raw_pushfl,(void)) -{ - emit_byte(0x9c); -} -LENDFUNC(READ,WRITE,0,raw_pushfl,(void)) - -LOWFUNC(WRITE,READ,0,raw_popfl,(void)) -{ - emit_byte(0x9d); -} -LENDFUNC(WRITE,READ,0,raw_popfl,(void)) - -/* Generate floating-point instructions */ -static inline void x86_fadd_m(MEMR s) -{ - emit_byte(0xdc); - emit_byte(0x05); - emit_long(s); -} - -#endif /************************************************************************* * Unoptimizable stuff --- jump * @@ -3102,62 +1149,22 @@ static inline void x86_fadd_m(MEMR s) static inline void raw_call_r(R4 r) { -#if USE_NEW_RTASM CALLsr(r); -#else - emit_byte(0xff); - emit_byte(0xd0+r); -#endif } static inline void raw_call_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m) { -#if USE_NEW_RTASM ADDR32 CALLsm(base, X86_NOREG, r, m); -#else - int mu; - switch(m) { - case 1: mu=0; break; - case 2: mu=1; break; - case 4: mu=2; break; - case 8: mu=3; break; - default: abort(); - } - emit_byte(0xff); - emit_byte(0x14); - emit_byte(0x05+8*r+0x40*mu); - emit_long(base); -#endif } static inline void raw_jmp_r(R4 r) { -#if USE_NEW_RTASM JMPsr(r); -#else - emit_byte(0xff); - emit_byte(0xe0+r); -#endif } static inline void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m) { -#if USE_NEW_RTASM ADDR32 JMPsm(base, X86_NOREG, r, m); -#else - int mu; - switch (m) { - case 1: mu=0; break; - case 2: mu=1; break; - case 4: mu=2; break; - case 8: mu=3; break; - default: abort(); - } - emit_byte(0xff); - emit_byte(0x24); - emit_byte(0x05+8*r+0x40*mu); - emit_long(base); -#endif } static inline void raw_jmp_m(uae_u32 base) @@ -3170,22 +1177,12 @@ static inline void raw_jmp_m(uae_u32 base) static inline void raw_call(uae_u32 t) { -#if USE_NEW_RTASM ADDR32 CALLm(t); -#else - emit_byte(0xe8); - emit_long(t-(uintptr)target-4); -#endif } static inline void raw_jmp(uae_u32 t) { -#if USE_NEW_RTASM ADDR32 JMPm(t); -#else - emit_byte(0xe9); - emit_long(t-(uintptr)target-4); -#endif } static inline void raw_jl(uae_u32 t) @@ -3385,10 +1382,12 @@ static __inline__ void raw_flags_set_zero_FLAGREG(int s, int tmp) { raw_mov_l_rr(tmp,s); raw_lahf(s); /* flags into ah */ + SETOr(X86_AL); /* V flag into al */ raw_and_l_ri(s,0xffffbfff); raw_and_l_ri(tmp,0x00004000); raw_xor_l_ri(tmp,0x00004000); raw_or_l(s,tmp); + raw_cmp_b_ri(X86_AL,-127); /* set V */ raw_sahf(s); } @@ -3509,28 +1508,18 @@ static inline void raw_flags_init_FLAGGEN(void) flag reload to avoid the partial memory stall */ static inline void raw_load_flagreg(uae_u32 target, uae_u32 r) { -#if 1 + /* attention: in 64bit mode, relies on LITTE_ENDIANESS of regflags.cznv */ raw_mov_l_rm(target,(uintptr)live.state[r].mem); -#else - raw_mov_b_rm(target,(uintptr)live.state[r].mem); - raw_mov_b_rm(target+4,((uintptr)live.state[r].mem)+1); -#endif } -#ifdef UAE -/* FLAGX is word-sized */ -#else -/* FLAGX is byte sized, and we *do* write it at that size */ -#endif static inline void raw_load_flagx(uae_u32 target, uae_u32 r) { -#ifdef UAE - if (live.nat[target].canword) -#else +#if FLAGBIT_X < 8 if (live.nat[target].canbyte) raw_mov_b_rm(target,(uintptr)live.state[r].mem); - else if (live.nat[target].canword) + else #endif + if (live.nat[target].canword) raw_mov_w_rm(target,(uintptr)live.state[r].mem); else raw_mov_l_rm(target,(uintptr)live.state[r].mem); @@ -3742,8 +1731,7 @@ cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx) cpuid_count(op, 0, eax, ebx, ecx, edx); } -static void -raw_init_cpu(void) +static void raw_init_cpu(void) { struct cpuinfo_x86 *c = &cpuinfo; uae_u32 dummy; @@ -3890,7 +1878,7 @@ raw_init_cpu(void) } #ifndef UAE -static void inline prevent_redzone_use(void) {} +static void __attribute__((noinline)) prevent_redzone_use(void) {} static bool target_check_bsf(void) { @@ -4049,9 +2037,8 @@ static inline void tos_make(int r) } /* FP helper functions */ -#if USE_NEW_RTASM #define DEFINE_OP(NAME, GEN) \ -static inline void raw_##NAME(uint32 m) \ +static inline void raw_##NAME(uintptr m) \ { \ GEN(m, X86_NOREG, X86_NOREG, 1); \ } @@ -4065,35 +2052,15 @@ DEFINE_OP(fsts, FSTSm); DEFINE_OP(fstpt, FSTPTm); DEFINE_OP(fldt, FLDTm); DEFINE_OP(fistpl, FISTPLm); -#else -#define DEFINE_OP(NAME, OP1, OP2) \ -static inline void raw_##NAME(uint32 m) \ -{ \ - emit_byte(OP1); \ - emit_byte(OP2); \ - emit_long(m); \ -} -DEFINE_OP(fstl, 0xdd, 0x15); -DEFINE_OP(fstpl, 0xdd, 0x1d); -DEFINE_OP(fldl, 0xdd, 0x05); -DEFINE_OP(fildl, 0xdb, 0x05); -DEFINE_OP(fistl, 0xdb, 0x15); -DEFINE_OP(flds, 0xd9, 0x05); -DEFINE_OP(fsts, 0xd9, 0x15); -DEFINE_OP(fstpt, 0xdb, 0x3d); -DEFINE_OP(fldt, 0xdb, 0x2d); -DEFINE_OP(fistpl, 0xdb, 0x1d); -#endif #undef DEFINE_OP -LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMPTRW m, FR r)) { make_tos(r); raw_fstl(m); } -LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r)) -LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMPTRW m, FR r)) { make_tos(r); raw_fstpl(m); @@ -4101,30 +2068,26 @@ LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r)) live.tos--; live.spos[r]=-2; } -LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r)) -LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m)) +LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMPTRR m)) { raw_fldl(m); tos_make(r); } -LENDFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m)) -LOWFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m)) +LOWFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMPTRR m)) { raw_fildl(m); tos_make(r); } -LENDFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m)) -LOWFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMPTRW m, FR r)) { make_tos(r); raw_fistl(m); } -LENDFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r)) -LOWFUNC(NONE,WRITE,3,raw_fmovi_mrb,(MEMW m, FR r, double *bounds)) +LOWFUNC(NONE,WRITE,3,raw_fmovi_mrb,(MEMPTRW m, FR r, double *bounds)) { /* Clamp value to the given range and convert to integer. */ @@ -4155,23 +2118,20 @@ LOWFUNC(NONE,WRITE,3,raw_fmovi_mrb,(MEMW m, FR r, double *bounds)) /* Store to destination */ raw_fistpl(m); } -LENDFUNC(NONE,WRITE,3,raw_fmovi_mrb,(MEMW m, FR r, double *bounds)) -LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m)) +LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMPTRR m)) { raw_flds(m); tos_make(r); } -LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m)) -LOWFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMPTRW m, FR r)) { make_tos(r); raw_fsts(m); } -LENDFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r)) -LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMPTRW m, FR r)) { int rs; @@ -4183,9 +2143,8 @@ LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r)) raw_fstpt(m); /* store and pop it */ } -LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r)) -LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr_drop,(MEMW m, FR r)) +LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr_drop,(MEMPTRW m, FR r)) { make_tos(r); raw_fstpt(m); /* store and pop it */ @@ -4193,14 +2152,12 @@ LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr_drop,(MEMW m, FR r)) live.tos--; live.spos[r]=-2; } -LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r)) -LOWFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m)) +LOWFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMPTRR m)) { raw_fldt(m); tos_make(r); } -LENDFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m)) LOWFUNC(NONE,NONE,1,raw_fmov_pi,(FW r)) { @@ -4208,7 +2165,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_pi,(FW r)) emit_byte(0xeb); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_pi,(FW r)) LOWFUNC(NONE,NONE,1,raw_fmov_log10_2,(FW r)) { @@ -4216,7 +2172,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_log10_2,(FW r)) emit_byte(0xec); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_log10_2,(FW r)) LOWFUNC(NONE,NONE,1,raw_fmov_log2_e,(FW r)) { @@ -4224,7 +2179,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_log2_e,(FW r)) emit_byte(0xea); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_log2_e,(FW r)) LOWFUNC(NONE,NONE,1,raw_fmov_loge_2,(FW r)) { @@ -4232,7 +2186,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_loge_2,(FW r)) emit_byte(0xed); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_loge_2,(FW r)) LOWFUNC(NONE,NONE,1,raw_fmov_1,(FW r)) { @@ -4240,7 +2193,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_1,(FW r)) emit_byte(0xe8); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_1,(FW r)) LOWFUNC(NONE,NONE,1,raw_fmov_0,(FW r)) { @@ -4248,7 +2200,6 @@ LOWFUNC(NONE,NONE,1,raw_fmov_0,(FW r)) emit_byte(0xee); tos_make(r); } -LENDFUNC(NONE,NONE,1,raw_fmov_0,(FW r)) LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) { @@ -4268,7 +2219,6 @@ LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) tos_make(d); /* store to destination, pop if necessary */ } } -LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base)) { @@ -4277,7 +2227,6 @@ LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base)) emit_byte(0xa8 + index); emit_long(base); } -LENDFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base)) LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s)) { @@ -4298,7 +2247,6 @@ LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s)) emit_byte(0xfa); /* take square root */ } } -LENDFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s)) { @@ -4319,7 +2267,6 @@ LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s)) emit_byte(0xe1); /* take fabs */ } } -LENDFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s)) { @@ -4340,7 +2287,6 @@ LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s)) emit_byte(0xfc); /* take frndint */ } } -LENDFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s)) { @@ -4361,7 +2307,6 @@ LOWFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s)) emit_byte(0xff); /* take cos */ } } -LENDFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s)) { @@ -4382,7 +2327,6 @@ LOWFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s)) emit_byte(0xfe); /* fsin y=sin(x) */ } } -LENDFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s)) static const double one = 1; @@ -4399,19 +2343,18 @@ LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s)) emit_byte(0xd9); emit_byte(0xfc); /* frndint int(x) */ emit_byte(0xd9); - emit_byte(0xc9); /* swap top two elements */ + emit_byte(0xc9); /* swap top two elements */ emit_byte(0xd8); - emit_byte(0xe1); /* subtract rounded from original */ + emit_byte(0xe1); /* fsub frac(x) = x - int(x) */ emit_byte(0xd9); - emit_byte(0xf0); /* f2xm1 */ - x86_fadd_m((uintptr)&one); /* Add '1' without using extra stack space */ + emit_byte(0xf0); /* f2xm1 (2^frac(x))-1 */ + x86_fadd_m((uintptr) &one); /* Add '1' without using extra stack space */ emit_byte(0xd9); - emit_byte(0xfd); /* and scale it */ + emit_byte(0xfd); /* fscale (2^frac(x))*2^int(x) */ emit_byte(0xdd); - emit_byte(0xd9); /* take he rounded value off */ - tos_make(d); /* store to destination */ + emit_byte(0xd9); /* fstp copy & pop */ + tos_make(d); /* store y=2^x */ } -LENDFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s)) { @@ -4443,7 +2386,6 @@ LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s)) emit_byte(0xd9); /* take he rounded value off */ tos_make(d); /* store to destination */ } -LENDFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s)) { @@ -4461,7 +2403,6 @@ LOWFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s)) emit_byte(0xf1); /* take 1*log2(x) */ tos_make(d); /* store to destination */ } -LENDFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s)) @@ -4483,7 +2424,6 @@ LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s)) emit_byte(0xe0); /* take fchs */ } } -LENDFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s)) { @@ -4506,7 +2446,6 @@ LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s)) emit_byte(0xc0+ds); /* add source to dest*/ } } -LENDFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s)) { @@ -4529,7 +2468,6 @@ LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s)) emit_byte(0xe0+ds); /* sub src from dest */ } } -LENDFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s)) { @@ -4544,7 +2482,6 @@ LOWFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s)) emit_byte(0xdd); emit_byte(0xe0+ds); /* cmp dest with source*/ } -LENDFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s)) LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s)) { @@ -4567,7 +2504,6 @@ LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s)) emit_byte(0xc8+ds); /* mul dest by source*/ } } -LENDFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s)) { @@ -4590,7 +2526,6 @@ LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s)) emit_byte(0xf0+ds); /* div dest by source*/ } } -LENDFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s)) { @@ -4608,7 +2543,6 @@ LOWFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s)) emit_byte(0xd9); emit_byte(0xf8); /* take rem from dest by source */ } -LENDFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s)) { @@ -4626,7 +2560,6 @@ LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s)) emit_byte(0xd9); emit_byte(0xf5); /* take rem1 from dest by source */ } -LENDFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,1,raw_ftst_r,(FR r)) @@ -4635,7 +2568,6 @@ LOWFUNC(NONE,NONE,1,raw_ftst_r,(FR r)) emit_byte(0xd9); /* ftst */ emit_byte(0xe4); } -LENDFUNC(NONE,NONE,1,raw_ftst_r,(FR r)) LOWFUNC(NONE,NONE,2,raw_fetoxM1_rr,(FW d, FR s)) { @@ -4669,7 +2601,6 @@ LOWFUNC(NONE,NONE,2,raw_fetoxM1_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=(e^x)-1 */ } -LENDFUNC(NONE,NONE,2,raw_fetoxM1_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_ftentox_rr,(FW d, FR s)) { @@ -4704,7 +2635,6 @@ LOWFUNC(NONE,NONE,2,raw_ftentox_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=10^x */ } -LENDFUNC(NONE,NONE,2,raw_ftentox_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,3,raw_fsincos_rr,(FW d, FW c, FR s)) { @@ -4749,7 +2679,6 @@ LOWFUNC(NONE,NONE,3,raw_fsincos_rr,(FW d, FW c, FR s)) tos_make(d); /* store sin(x) to destination */ } } -LENDFUNC(NONE,NONE,3,raw_fsincos_rr,(FW d, FW c, FR s)) LOWFUNC(NONE,NONE,2,raw_fscale_rr,(FRW d, FR s)) { @@ -4770,7 +2699,6 @@ LOWFUNC(NONE,NONE,2,raw_fscale_rr,(FRW d, FR s)) tos_make(d); /* store y=y*(2^x) */ } } -LENDFUNC(NONE,NONE,2,raw_fscale_rr,(FRW d, FR s)) LOWFUNC(NONE,NONE,2,raw_ftan_rr,(FW d, FR s)) { @@ -4794,7 +2722,6 @@ LOWFUNC(NONE,NONE,2,raw_ftan_rr,(FW d, FR s)) emit_byte(0xd8); /* fstp pop 1.0 */ } } -LENDFUNC(NONE,NONE,2,raw_ftan_rr,(FW d, FR s)) #ifdef CPU_x86_64 #define REX64() emit_byte(0x48) @@ -4821,7 +2748,6 @@ LOWFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r)) emit_byte(0xc4); emit_byte(0x04); /* add +4 to esp */ } -LENDFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r)) LOWFUNC(NONE,NONE,1,raw_fcut_r,(FRW r)) { @@ -4842,7 +2768,6 @@ LOWFUNC(NONE,NONE,1,raw_fcut_r,(FRW r)) emit_byte(0xc4); emit_byte(0x08); /* add +8 to esp */ } -LENDFUNC(NONE,NONE,1,raw_fcut_r,(FRW r)) LOWFUNC(NONE,NONE,2,raw_fgetexp_rr,(FW d, FR s)) { @@ -4866,7 +2791,6 @@ LOWFUNC(NONE,NONE,2,raw_fgetexp_rr,(FW d, FR s)) emit_byte(0xd8); /* fstp just pop man */ } } -LENDFUNC(NONE,NONE,2,raw_fgetexp_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fgetman_rr,(FW d, FR s)) { @@ -4890,7 +2814,6 @@ LOWFUNC(NONE,NONE,2,raw_fgetman_rr,(FW d, FR s)) emit_byte(0xd9); /* fstp copy man up & pop */ } } -LENDFUNC(NONE,NONE,2,raw_fgetman_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_flogN_rr,(FW d, FR s)) { @@ -4912,7 +2835,6 @@ LOWFUNC(NONE,NONE,2,raw_flogN_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=logN(x) */ } -LENDFUNC(NONE,NONE,2,raw_flogN_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_flogNP1_rr,(FW d, FR s)) { @@ -4934,7 +2856,6 @@ LOWFUNC(NONE,NONE,2,raw_flogNP1_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=logN(x+1) */ } -LENDFUNC(NONE,NONE,2,raw_flogNP1_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_flog10_rr,(FW d, FR s)) { @@ -4956,7 +2877,6 @@ LOWFUNC(NONE,NONE,2,raw_flog10_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=log10(x) */ } -LENDFUNC(NONE,NONE,2,raw_flog10_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fasin_rr,(FW d, FR s)) { @@ -4981,9 +2901,8 @@ LOWFUNC(NONE,NONE,2,raw_fasin_rr,(FW d, FR s)) emit_byte(0xf3); /* fpatan atan(x/sqrt(1-(x^2))) & pop */ tos_make(d); /* store y=asin(x) */ } -LENDFUNC(NONE,NONE,2,raw_fasin_rr,(FW d, FR s)) -static uae_u32 pihalf[] = {0x2168c234, 0xc90fdaa2, 0x3fff}; // LSB=0 to get acos(1)=0 +static uae_u32 const pihalf[] = {0x2168c234, 0xc90fdaa2, 0x3fff}; // LSB=0 to get acos(1)=0 LOWFUNC(NONE,NONE,2,raw_facos_rr,(FW d, FR s)) { @@ -5011,7 +2930,6 @@ LOWFUNC(NONE,NONE,2,raw_facos_rr,(FW d, FR s)) emit_byte(0xe1); /* fsubrp pi/2 - asin(x) & pop */ tos_make(d); /* store y=acos(x) */ } -LENDFUNC(NONE,NONE,2,raw_facos_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fatan_rr,(FW d, FR s)) { @@ -5031,7 +2949,6 @@ LOWFUNC(NONE,NONE,2,raw_fatan_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=atan(x) */ } -LENDFUNC(NONE,NONE,2,raw_fatan_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fatanh_rr,(FW d, FR s)) { @@ -5066,7 +2983,6 @@ LOWFUNC(NONE,NONE,2,raw_fatanh_rr,(FW d, FR s)) emit_byte(0xd9); /* fstp copy & pop */ tos_make(d); /* store y=atanh(x) */ } -LENDFUNC(NONE,NONE,2,raw_fatanh_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fsinh_rr,(FW d, FR s)) { @@ -5159,7 +3075,6 @@ LOWFUNC(NONE,NONE,2,raw_fsinh_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=sinh(x) */ } -LENDFUNC(NONE,NONE,2,raw_fsinh_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_fcosh_rr,(FW d, FR s)) { @@ -5248,7 +3163,6 @@ LOWFUNC(NONE,NONE,2,raw_fcosh_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=cosh(x) */ } -LENDFUNC(NONE,NONE,2,raw_fcosh_rr,(FW d, FR s)) LOWFUNC(NONE,NONE,2,raw_ftanh_rr,(FW d, FR s)) { @@ -5337,7 +3251,6 @@ LOWFUNC(NONE,NONE,2,raw_ftanh_rr,(FW d, FR s)) if (s!=d) tos_make(d); /* store y=tanh(x) */ } -LENDFUNC(NONE,NONE,2,raw_ftanh_rr,(FW d, FR s)) /* %eax register is clobbered if target processor doesn't support fucomi */ #define FFLAG_NREG_CLOBBER_CONDITION !have_cmov diff --git a/BasiliskII/src/uae_cpu/compiler/codegen_x86.h b/BasiliskII/src/uae_cpu/compiler/codegen_x86.h index 6743392d..0eaef50a 100644 --- a/BasiliskII/src/uae_cpu/compiler/codegen_x86.h +++ b/BasiliskII/src/uae_cpu/compiler/codegen_x86.h @@ -402,22 +402,54 @@ typedef unsigned int _ul; /* --- Memory subformats - urgh! ------------------------------------------- */ /* _r_D() is RIP addressing mode if X86_TARGET_64BIT, use _r_DSIB() instead */ -#define _r_D( R, D ) (_Mrm(_b00,_rN(R),_b101 ) ,_L((long)(D))) -#define _r_DSIB(R, D ) (_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(1),_b100 ,_b101 ),_L((long)(D))) +#define _r_D( R, D ) (_Mrm(_b00,_rN(R),_b101 ) ,_L((uae_u32)(D))) +#define _r_DSIB(R, D ) (_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(1),_b100 ,_b101 ),_L((uae_u32)(D))) #define _r_0B( R, B ) (_Mrm(_b00,_rN(R),_rA(B)) ) #define _r_0BIS(R, B,I,S) (_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)) ) -#define _r_1B( R, D,B ) (_Mrm(_b01,_rN(R),_rA(B)) ,_B((long)(D))) -#define _r_1BIS(R, D,B,I,S) (_Mrm(_b01,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_B((long)(D))) -#define _r_4B( R, D,B ) (_Mrm(_b10,_rN(R),_rA(B)) ,_L((long)(D))) -#define _r_4IS( R, D,I,S) (_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_b101 ),_L((long)(D))) -#define _r_4BIS(R, D,B,I,S) (_Mrm(_b10,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_L((long)(D))) +#define _r_1B( R, D,B ) (_Mrm(_b01,_rN(R),_rA(B)) ,_B((uae_u32)(D))) +#define _r_1BIS(R, D,B,I,S) (_Mrm(_b01,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_B((uae_u32)(D))) +#define _r_4B( R, D,B ) (_Mrm(_b10,_rN(R),_rA(B)) ,_L((uae_u32)(D))) +#define _r_4IS( R, D,I,S) (_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_b101 ),_L((uae_u32)(D))) +#define _r_4BIS(R, D,B,I,S) (_Mrm(_b10,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_L((uae_u32)(D))) #define _r_DB( R, D,B ) ((_s0P(D) && (!_rbp13P(B)) ? _r_0B (R, B ) : (_s8P(D) ? _r_1B( R,D,B ) : _r_4B( R,D,B )))) #define _r_DBIS(R, D,B,I,S) ((_s0P(D) && (!_rbp13P(B)) ? _r_0BIS(R, B,I,S) : (_s8P(D) ? _r_1BIS(R,D,B,I,S) : _r_4BIS(R,D,B,I,S)))) /* Use RIP-addressing in 64-bit mode, if possible */ -#define _x86_RIP_addressing_possible(D,O) (X86_RIP_RELATIVE_ADDR && \ - ((uintptr)x86_get_target() + 4 + (O) - (D) <= 0xffffffff)) +#define _x86_RIP_addressing_possible(D,O) (X86_RIP_RELATIVE_ADDR && x86_RIP_addressing_possible(D, O)) + +static inline int x86_RIP_addressing_possible(uintptr addr, uintptr offset) +{ +#if X86_TARGET_64BIT + /* + * address of the next instruction. + * The opcode has already been emmitted, + * so this is the size of an 32bit displacement + + * the size of any immediate value that is part of the instruction (offset), + */ + uintptr dst = (uintptr)get_target() + 4 + offset; + intptr disp = dst - addr; + int ok = disp >= -0x80000000LL && disp <= 0x7fffffffLL; + /* fprintf(stderr, "x86_RIP_addressing_possible: %llx - %llx %16llx = %d\n", (unsigned long long)dst, (unsigned long long)addr, (long long)disp, ok); */ + return ok; +#else + UNUSED(addr); + UNUSED(offset); + return 0; +#endif +} + + +static inline int x86_DISP32_addressing_possible(uintptr addr) +{ +#if X86_TARGET_64BIT + return addr <= 0xFFFFFFFFULL; +#else + UNUSED(addr); + return 1; +#endif +} + #define _r_X( R, D,B,I,S,O) (_r0P(I) ? (_r0P(B) ? (!X86_TARGET_64BIT ? _r_D(R,D) : \ (_x86_RIP_addressing_possible(D, O) ? \ diff --git a/BasiliskII/src/uae_cpu/compiler/compemu.h b/BasiliskII/src/uae_cpu/compiler/compemu.h index 118251c8..10a97d14 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu.h +++ b/BasiliskII/src/uae_cpu/compiler/compemu.h @@ -35,11 +35,6 @@ // #include "sysconfig.h" #include "newcpu.h" -#ifdef __x86_64__ -#define CPU_64_BIT 1 -#define CPU_x86_64 1 -#endif - #ifdef UAE #ifdef CPU_64_BIT typedef uae_u64 uintptr; @@ -135,11 +130,19 @@ union cacheline { for jump targets */ #define INDIVIDUAL_INST 0 +#ifdef WINUAE_ARANYM #define FLAG_X 0x0010 #define FLAG_N 0x0008 #define FLAG_Z 0x0004 #define FLAG_V 0x0002 #define FLAG_C 0x0001 +#else +#define FLAG_C 0x0010 +#define FLAG_V 0x0008 +#define FLAG_Z 0x0004 +#define FLAG_N 0x0002 +#define FLAG_X 0x0001 +#endif #define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V) #define FLAG_ALL (FLAG_C | FLAG_Z | FLAG_N | FLAG_V | FLAG_X) #define FLAG_ZNV (FLAG_Z | FLAG_N | FLAG_V) @@ -165,27 +168,74 @@ extern void compiler_init(void); extern void compiler_exit(void); extern bool compiler_use_jit(void); #endif -extern void init_comp(void); extern void flush(int save_regs); -extern void small_flush(int save_regs); extern void set_target(uae_u8* t); extern uae_u8* get_target(void); -extern void freescratch(void); +#ifdef UAE extern void build_comp(void); +#endif extern void set_cache_state(int enabled); extern int get_cache_state(void); extern uae_u32 get_jitted_size(void); #ifdef JIT -#ifdef WINUAE_ARANYM -extern void (*flush_icache)(int n); -#else -extern void flush_icache(int n); -#endif +extern void (*flush_icache)(void); #endif extern void alloc_cache(void); extern int check_for_cache_miss(void); /* JIT FPU compilation */ +struct jit_disable_opcodes { + bool fbcc; + bool fdbcc; + bool fscc; + bool ftrapcc; + bool fsave; + bool frestore; + bool fmove; + bool fmovem; + bool fmovec; /* for move control register */ + bool fmovecr; /* for move from constant rom */ + bool fint; + bool fsinh; + bool fintrz; + bool fsqrt; + bool flognp1; + bool fetoxm1; + bool ftanh; + bool fatan; + bool fasin; + bool fatanh; + bool fsin; + bool ftan; + bool fetox; + bool ftwotox; + bool ftentox; + bool flogn; + bool flog10; + bool flog2; + bool fabs; + bool fcosh; + bool fneg; + bool facos; + bool fcos; + bool fgetexp; + bool fgetman; + bool fdiv; + bool fmod; + bool fadd; + bool fmul; + bool fsgldiv; + bool frem; + bool fscale; + bool fsglmul; + bool fsub; + bool fsincos; + bool fcmp; + bool ftst; +}; +extern struct jit_disable_opcodes jit_disable; + + extern void comp_fpp_opp (uae_u32 opcode, uae_u16 extra); extern void comp_fbcc_opp (uae_u32 opcode); extern void comp_fscc_opp (uae_u32 opcode, uae_u16 extra); @@ -320,18 +370,20 @@ extern int touchcnt; #define RW4 uae_u32 #define MEMR uae_u32 #define MEMW uae_u32 -#define MEMRW uae_u32 +#define MEMRW uae_u32 +#define MEMPTR uintptr +#define MEMPTRR MEMPTR +#define MEMPTRW MEMPTR +#define MEMPTRRW MEMPTR #define FW uae_u32 #define FR uae_u32 #define FRW uae_u32 #define MIDFUNC(nargs,func,args) void func args -#define MENDFUNC(nargs,func,args) #define COMPCALL(func) func #define LOWFUNC(flags,mem,nargs,func,args) static inline void func args -#define LENDFUNC(flags,mem,nargs,func,args) /* What we expose to the outside */ #define DECLARE_MIDFUNC(func) extern void func @@ -456,8 +508,7 @@ void do_nothing(void); #else -static inline void flush_icache(int) { } -static inline void build_comp() { } +static inline void flush_icache(void) { } #endif /* !USE_JIT */ @@ -520,7 +571,7 @@ void jit_abort(const TCHAR *format, ...); #else #ifdef WINUAE_ARANYM -#define jit_log(format, ...) write_log(format"\n", ##__VA_ARGS__) +#define jit_log(format, ...) D(bug(format, ##__VA_ARGS__)) #define jit_log2(format, ...) D2(bug(format, ##__VA_ARGS__)) void jit_abort(const char *format,...) __attribute__((format(printf, 1, 2))) __attribute__((__noreturn__)); #else diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_fpp.cpp b/BasiliskII/src/uae_cpu/compiler/compemu_fpp.cpp index cef6d43e..5d5de2cd 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_fpp.cpp +++ b/BasiliskII/src/uae_cpu/compiler/compemu_fpp.cpp @@ -29,19 +29,19 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* - * UAE - The Un*x Amiga Emulator - * - * MC68881 emulation - * - * Copyright 1996 Herman ten Brugge - * Adapted for JIT compilation (c) Bernd Meyer, 2000 - */ + * UAE - The Un*x Amiga Emulator + * + * MC68881 emulation + * + * Copyright 1996 Herman ten Brugge + * Adapted for JIT compilation (c) Bernd Meyer, 2000 + */ #include "sysdeps.h" -# include -# include -# include +#include +#include +#include #include "memory.h" #include "readcpu.h" @@ -56,6 +56,14 @@ #define DEBUG 0 #include "debug.h" +struct jit_disable_opcodes jit_disable; + +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) +#define LD(x) x ## L +#else +#define LD(x) x +#endif + // gb-- WARNING: get_fpcr() and set_fpcr() support is experimental #define HANDLE_FPCR 0 @@ -87,6 +95,7 @@ #define delay2 nop() ;nop() #define UNKNOWN_EXTRA 0xFFFFFFFF +#if 0 static void fpuop_illg(uae_u32 opcode, uae_u32 /* extra */) { /* @@ -97,623 +106,715 @@ static void fpuop_illg(uae_u32 opcode, uae_u32 /* extra */) */ op_illg(opcode); } +#endif uae_s32 temp_fp[4]; /* To convert between FP/integer */ /* return register number, or -1 for failure */ -STATIC_INLINE int get_fp_value (uae_u32 opcode, uae_u16 extra) +STATIC_INLINE int get_fp_value(uae_u32 opcode, uae_u16 extra) { - uaecptr tmppc; - uae_u16 tmp; - int size; - int mode; - int reg; - uae_u32 ad = 0; - static int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 }; - static int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 }; + int size; + int mode; + int reg; + uae_u32 ad = 0; + static int const sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 }; + static int const sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 }; - if ((extra & 0x4000) == 0) { - return ((extra >> 10) & 7); - } - - mode = (opcode >> 3) & 7; - reg = opcode & 7; - size = (extra >> 10) & 7; - switch (mode) { - case 0: - switch (size) { - case 6: - sign_extend_8_rr(S1,reg); - mov_l_mr((uintptr)temp_fp,S1); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - return FS1; - case 4: - sign_extend_16_rr(S1,reg); - mov_l_mr((uintptr)temp_fp,S1); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - return FS1; - case 0: - mov_l_mr((uintptr)temp_fp,reg); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - return FS1; - case 1: - mov_l_mr((uintptr)temp_fp,reg); - delay2; - fmovs_rm(FS1,(uintptr)temp_fp); - return FS1; - default: - return -1; + if ((extra & 0x4000) == 0) + { + return ((extra >> 10) & 7); } - return -1; /* Should be unreachable */ - case 1: - return -1; /* Genuine invalid instruction */ - default: - break; - } - /* OK, we *will* have to load something from an address. Let's make - sure we know how to handle that, or quit early --- i.e. *before* - we do any postincrement/predecrement that we may regret */ - switch (size) { - case 3: - return -1; - case 0: - case 1: - case 2: - case 4: - case 5: - case 6: - break; - default: - return -1; - } - - switch (mode) { - case 2: - ad=S1; /* We will change it, anyway ;-) */ - mov_l_rr(ad,reg+8); - break; - case 3: - ad=S1; - mov_l_rr(ad,reg+8); - lea_l_brr(reg+8,reg+8,(reg == 7?sz2[size]:sz1[size])); - break; - case 4: - ad=S1; - - lea_l_brr(reg+8,reg+8,-(reg == 7?sz2[size]:sz1[size])); - mov_l_rr(ad,reg+8); - break; - case 5: - { - uae_u32 off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_rr(ad,reg+8); - lea_l_brr(ad,ad,off); - break; - } - case 6: - { - uae_u32 dp=comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - calc_disp_ea_020(reg+8,dp,ad,S2); - break; - } - case 7: - switch (reg) { - case 0: - { - uae_u32 off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_ri(ad,off); - break; - } - case 1: - { - uae_u32 off=comp_get_ilong((m68k_pc_offset+=4)-4); - ad=S1; - mov_l_ri(ad,off); - break; - } - case 2: - { - uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+ - m68k_pc_offset; - uae_s32 PC16off =(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_ri(ad,address+PC16off); - break; - } - case 3: - return -1; - tmppc = m68k_getpc (); - tmp = next_iword (); - ad = get_disp_ea_020 (tmppc, tmp); - break; - case 4: - { - uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+ m68k_pc_offset; - ad=S1; - // Immediate addressing mode && Operation Length == Byte -> - // Use the low-order byte of the extension word. - if (size == 6) address++; - mov_l_ri(ad,address); - m68k_pc_offset+=sz2[size]; - break; - } - default: - return -1; + mode = (opcode >> 3) & 7; + reg = opcode & 7; + size = (extra >> 10) & 7; + switch (mode) + { + case 0: /* Dn */ + switch (size) + { + case 6: /* byte */ + sign_extend_8_rr(S1, reg); + mov_l_mr((uintptr) temp_fp, S1); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + return FS1; + case 4: /* word */ + sign_extend_16_rr(S1, reg); + mov_l_mr((uintptr) temp_fp, S1); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + return FS1; + case 0: /* long */ + mov_l_mr((uintptr) temp_fp, reg); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + return FS1; + case 1: /* single precision */ + mov_l_mr((uintptr) temp_fp, reg); + delay2; + fmovs_rm(FS1, (uintptr) temp_fp); + return FS1; + default: + return -1; + } + return -1; /* Should be unreachable */ + case 1: /* An */ + return -1; /* Genuine invalid instruction */ + default: + break; } - } - switch (size) { - case 0: - readlong(ad,S2,S3); - mov_l_mr((uintptr)temp_fp,S2); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - break; - case 1: - readlong(ad,S2,S3); - mov_l_mr((uintptr)temp_fp,S2); - delay2; - fmovs_rm(FS1,(uintptr)temp_fp); - break; - case 2: - readword(ad,S2,S3); - mov_w_mr(((uintptr)temp_fp)+8,S2); - add_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp)+4,S2); - add_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp),S2); - delay2; - fmov_ext_rm(FS1,(uintptr)(temp_fp)); - break; - case 3: - return -1; /* Some silly "packed" stuff */ - case 4: - readword(ad,S2,S3); - sign_extend_16_rr(S2,S2); - mov_l_mr((uintptr)temp_fp,S2); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - break; - case 5: - readlong(ad,S2,S3); - mov_l_mr(((uintptr)temp_fp)+4,S2); - add_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp),S2); - delay2; - fmov_rm(FS1,(uintptr)(temp_fp)); - break; - case 6: - readbyte(ad,S2,S3); - sign_extend_8_rr(S2,S2); - mov_l_mr((uintptr)temp_fp,S2); - delay2; - fmovi_rm(FS1,(uintptr)temp_fp); - break; - default: - return -1; - } - return FS1; + /* OK, we *will* have to load something from an address. Let's make + sure we know how to handle that, or quit early --- i.e. *before* + we do any postincrement/predecrement that we may regret */ + switch (size) + { + case 0: /* long */ + case 1: /* single precision */ + case 2: /* extended precision */ + case 4: /* word */ + case 5: /* double precision */ + case 6: /* byte */ + break; + case 3: /* packed decimal static */ + default: + return -1; + } + + switch (mode) + { + case 2: /* (An) */ + ad = S1; /* We will change it, anyway ;-) */ + mov_l_rr(ad, reg + 8); + break; + case 3: /* (An)+ */ + ad = S1; + mov_l_rr(ad, reg + 8); + lea_l_brr(reg + 8, reg + 8, (reg == 7 ? sz2[size] : sz1[size])); + break; + case 4: /* -(An) */ + ad = S1; + lea_l_brr(reg + 8, reg + 8, -(reg == 7 ? sz2[size] : sz1[size])); + mov_l_rr(ad, reg + 8); + break; + case 5: /* d16(An) */ + { + uae_u32 off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_rr(ad, reg + 8); + lea_l_brr(ad, ad, off); + } + break; + case 6: /* d8(An,Xn) */ + { + uae_u32 dp = comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + calc_disp_ea_020(reg + 8, dp, ad, S2); + } + break; + case 7: + switch (reg) + { + case 0: /* abs.w */ + { + uae_u32 off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_ri(ad, off); + } + break; + case 1: /* abs.l */ + { + uae_u32 off = comp_get_ilong((m68k_pc_offset += 4) - 4); + + ad = S1; + mov_l_ri(ad, off); + } + break; + case 2: /* d16(pc) */ + { + uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset; + uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_ri(ad, address + PC16off); + } + break; + case 3: /* d8(pc,Xn) */ + return -1; + case 4: /* #imm */ + { + uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset; + + ad = S1; + // Immediate addressing mode && Operation Length == Byte -> + // Use the low-order byte of the extension word. + if (size == 6) + address++; + mov_l_ri(ad, address); + m68k_pc_offset += sz2[size]; + } + break; + default: + return -1; + } + } + + switch (size) + { + case 0: /* long */ + readlong(ad, S2, S3); + mov_l_mr((uintptr) temp_fp, S2); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + break; + case 1: /* single precision */ + readlong(ad, S2, S3); + mov_l_mr((uintptr) temp_fp, S2); + delay2; + fmovs_rm(FS1, (uintptr) temp_fp); + break; + case 2: /* extended precision */ + readword(ad, S2, S3); + mov_w_mr(((uintptr) temp_fp) + 8, S2); + add_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp) + 4, S2); + add_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp), S2); + delay2; + fmov_ext_rm(FS1, (uintptr) (temp_fp)); + break; + case 3: /* packed decimal static */ + return -1; /* Some silly "packed" stuff */ + case 4: /* word */ + readword(ad, S2, S3); + sign_extend_16_rr(S2, S2); + mov_l_mr((uintptr) temp_fp, S2); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + break; + case 5: /* double precision */ + readlong(ad, S2, S3); + mov_l_mr(((uintptr) temp_fp) + 4, S2); + add_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp), S2); + delay2; + fmov_rm(FS1, (uintptr) (temp_fp)); + break; + case 6: /* byte */ + readbyte(ad, S2, S3); + sign_extend_8_rr(S2, S2); + mov_l_mr((uintptr) temp_fp, S2); + delay2; + fmovi_rm(FS1, (uintptr) temp_fp); + break; + default: + return -1; + } + return FS1; } -/* return of -1 means failure, >=0 means OK */ -STATIC_INLINE int put_fp_value (int val, uae_u32 opcode, uae_u16 extra) -{ - uae_u16 tmp; - uaecptr tmppc; - int size; - int mode; - int reg; - uae_u32 ad; - static int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 }; - static int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 }; - if ((extra & 0x4000) == 0) { +/* return of -1 means failure, >=0 means OK */ +STATIC_INLINE int put_fp_value(int val, uae_u32 opcode, uae_u16 extra) +{ + int size; + int mode; + int reg; + uae_u32 ad; + static int const sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 }; + static int const sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 }; + + if ((extra & 0x4000) == 0) + { const int dest_reg = (extra >> 10) & 7; + fmov_rr(dest_reg, val); // gb-- status register is affected MAKE_FPSR(dest_reg); return 0; - } - - mode = (opcode >> 3) & 7; - reg = opcode & 7; - size = (extra >> 10) & 7; - ad = (uae_u32)-1; - switch (mode) { - case 0: - switch (size) { - case 6: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_b_rm(reg,(uintptr)temp_fp); - return 0; - case 4: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_w_rm(reg,(uintptr)temp_fp); - return 0; - case 0: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(reg,(uintptr)temp_fp); - return 0; - case 1: - fmovs_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(reg,(uintptr)temp_fp); - return 0; - default: - return -1; } - case 1: - return -1; /* genuine invalid instruction */ - default: break; - } - /* Let's make sure we get out *before* doing something silly if - we can't handle the size */ - switch (size) { - case 0: - case 4: - case 5: - case 6: - case 2: - case 1: - break; - case 3: - default: - return -1; - } - - switch (mode) { - case 2: - ad=S1; - mov_l_rr(ad,reg+8); - break; - case 3: - ad=S1; - mov_l_rr(ad,reg+8); - lea_l_brr(reg+8,reg+8,(reg == 7?sz2[size]:sz1[size])); - break; - case 4: - ad=S1; - lea_l_brr(reg+8,reg+8,-(reg == 7?sz2[size]:sz1[size])); - mov_l_rr(ad,reg+8); - break; - case 5: - { - uae_u32 off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_rr(ad,reg+8); - add_l_ri(ad,off); - break; - } - case 6: - { - uae_u32 dp=comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - calc_disp_ea_020(reg+8,dp,ad,S2); - break; - } - case 7: - switch (reg) { - case 0: - { - uae_u32 off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_ri(ad,off); - break; - } - case 1: - { - uae_u32 off=comp_get_ilong((m68k_pc_offset+=4)-4); - ad=S1; - mov_l_ri(ad,off); - break; - } - case 2: - { - uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+ - m68k_pc_offset; - uae_s32 PC16off =(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - ad=S1; - mov_l_ri(ad,address+PC16off); - break; - } - case 3: - return -1; - tmppc = m68k_getpc (); - tmp = next_iword (); - ad = get_disp_ea_020 (tmppc, tmp); - break; - case 4: - { - uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+ - m68k_pc_offset; - ad=S1; - mov_l_ri(ad,address); - m68k_pc_offset+=sz2[size]; - break; - } - default: - return -1; + mode = (opcode >> 3) & 7; + reg = opcode & 7; + size = (extra >> 10) & 7; + ad = (uae_u32) -1; + switch (mode) + { + case 0: /* Dn */ + switch (size) + { + case 6: /* byte */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_b_rm(reg, (uintptr) temp_fp); + return 0; + case 4: /* word */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_w_rm(reg, (uintptr) temp_fp); + return 0; + case 0: /* long */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(reg, (uintptr) temp_fp); + return 0; + case 1: /* single precision */ + fmovs_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(reg, (uintptr) temp_fp); + return 0; + default: + return -1; + } + case 1: /* An */ + return -1; /* genuine invalid instruction */ + default: + break; } - } - switch (size) { - case 0: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - break; - case 1: - fmovs_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - break; - case 2: - fmov_ext_mr((uintptr)temp_fp,val); - delay; - mov_w_rm(S2,(uintptr)temp_fp+8); - writeword_clobber(ad,S2,S3); - add_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp+4); - writelong_clobber(ad,S2,S3); - add_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - break; - case 3: return -1; /* Packed */ - case 4: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(S2,(uintptr)temp_fp); - writeword_clobber(ad,S2,S3); - break; - case 5: - fmov_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(S2,(uintptr)temp_fp+4); - writelong_clobber(ad,S2,S3); - add_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - break; - case 6: - fmovi_mr((uintptr)temp_fp,val); - delay; - mov_l_rm(S2,(uintptr)temp_fp); - writebyte(ad,S2,S3); - break; - default: - return -1; - } - return 0; + /* Let's make sure we get out *before* doing something silly if + we can't handle the size */ + switch (size) + { + case 0: /* long */ + case 1: /* single precision */ + case 2: /* extended precision */ + case 4: /* word */ + case 5: /* double precision */ + case 6: /* byte */ + break; + case 3: /* packed decimal static */ + default: + return -1; + } + + switch (mode) + { + case 2: /* (An) */ + ad = S1; + mov_l_rr(ad, reg + 8); + break; + case 3: /* (An)+ */ + ad = S1; + mov_l_rr(ad, reg + 8); + lea_l_brr(reg + 8, reg + 8, (reg == 7 ? sz2[size] : sz1[size])); + break; + case 4: /* -(An) */ + ad = S1; + lea_l_brr(reg + 8, reg + 8, -(reg == 7 ? sz2[size] : sz1[size])); + mov_l_rr(ad, reg + 8); + break; + case 5: /* d16(An) */ + { + uae_u32 off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_rr(ad, reg + 8); + add_l_ri(ad, off); + } + break; + case 6: /* d8(An,Xn) */ + { + uae_u32 dp = comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + calc_disp_ea_020(reg + 8, dp, ad, S2); + } + break; + case 7: + switch (reg) + { + case 0: /* abs.w */ + { + uae_u32 off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_ri(ad, off); + } + break; + case 1: /* abs.l */ + { + uae_u32 off = comp_get_ilong((m68k_pc_offset += 4) - 4); + + ad = S1; + mov_l_ri(ad, off); + } + break; + case 2: /* d16(pc) */ + { + uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset; + uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + + ad = S1; + mov_l_ri(ad, address + PC16off); + } + break; + case 3: /* d8(pc,Xn) */ + return -1; + case 4: /* #imm */ + { + uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset; + + ad = S1; + mov_l_ri(ad, address); + m68k_pc_offset += sz2[size]; + } + break; + default: + return -1; + } + } + + switch (size) + { + case 0: /* long */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + break; + case 1: /* single precision */ + fmovs_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + break; + case 2: /* extended precision */ + fmov_ext_mr((uintptr) temp_fp, val); + delay; + mov_w_rm(S2, (uintptr) temp_fp + 8); + writeword_clobber(ad, S2, S3); + add_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp + 4); + writelong_clobber(ad, S2, S3); + add_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + break; + case 3: /* packed decimal static */ + return -1; /* Packed */ + case 4: /* word */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(S2, (uintptr) temp_fp); + writeword_clobber(ad, S2, S3); + break; + case 5: /* double precision */ + fmov_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(S2, (uintptr) temp_fp + 4); + writelong_clobber(ad, S2, S3); + add_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + break; + case 6: /* byte */ + fmovi_mr((uintptr) temp_fp, val); + delay; + mov_l_rm(S2, (uintptr) temp_fp); + writebyte(ad, S2, S3); + break; + default: + return -1; + } + return 0; } + /* return -1 for failure, or register number for success */ -STATIC_INLINE int get_fp_ad (uae_u32 opcode, uae_u32 * ad) +STATIC_INLINE int get_fp_ad(uae_u32 opcode) { - uae_u16 tmp; - uaecptr tmppc; - int mode; - int reg; - uae_s32 off; + int mode; + int reg; + uae_s32 off; - mode = (opcode >> 3) & 7; - reg = opcode & 7; - switch (mode) { - case 0: - case 1: - return -1; - case 2: - case 3: - case 4: - mov_l_rr(S1,8+reg); - return S1; - *ad = m68k_areg (regs, reg); - break; - case 5: - off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - - mov_l_rr(S1,8+reg); - add_l_ri(S1,off); - return S1; - case 6: - return -1; - break; - case 7: - switch (reg) { - case 0: - off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - mov_l_ri(S1,off); - return S1; - case 1: - off=comp_get_ilong((m68k_pc_offset+=4)-4); - mov_l_ri(S1,off); - return S1; - case 2: - return -1; -// *ad = m68k_getpc (); -// *ad += (uae_s32) (uae_s16) next_iword (); - off=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset; - off+=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - mov_l_ri(S1,off); - return S1; - case 3: - return -1; - tmppc = m68k_getpc (); - tmp = next_iword (); - *ad = get_disp_ea_020 (tmppc, tmp); - break; - default: - return -1; + mode = (opcode >> 3) & 7; + reg = opcode & 7; + switch (mode) + { + case 0: /* Dn */ + case 1: /* An */ + return -1; + case 2: /* (An) */ + case 3: /* (An)+ */ + case 4: /* -(An) */ + mov_l_rr(S1, 8 + reg); + return S1; + case 5: /* d16(An) */ + off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + mov_l_rr(S1, 8 + reg); + add_l_ri(S1, off); + return S1; + case 6: /* d8(An,Xn) */ + return -1; + break; + case 7: + switch (reg) + { + case 0: /* abs.w */ + off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + mov_l_ri(S1, off); + return S1; + case 1: /* abs.l */ + off = comp_get_ilong((m68k_pc_offset += 4) - 4); + mov_l_ri(S1, off); + return S1; + case 2: /* d16(pc) */ + off = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset; + off += (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + mov_l_ri(S1, off); + return S1; + case 3: /* d8(pc,Xn) */ + return -1; + default: + return -1; + } } - } - abort(); + abort(); } + +/* return -1 for failure, or register number for success */ void comp_fdbcc_opp (uae_u32 /* opcode */, uae_u16 /* extra */) { + if (jit_disable.fdbcc) + { + FAIL(1); + return; + } FAIL(1); return; } -void comp_fscc_opp (uae_u32 opcode, uae_u16 extra) + +void comp_fscc_opp(uae_u32 opcode, uae_u16 extra) { - uae_u32 ad; - int cc; - int reg; + int reg; -#ifdef DEBUG_FPP - printf ("fscc_opp at %08lx\n", m68k_getpc ()); - fflush (stdout); -#endif + if (jit_disable.fscc) + { + FAIL(1); + return; + } + if (extra & 0x20) + { /* only cc from 00 to 1f are defined */ + FAIL(1); + return; + } + if ((opcode & 0x38) != 0) + { /* We can only do to integer register */ + FAIL(1); + return; + } - if (extra&0x20) { /* only cc from 00 to 1f are defined */ - FAIL(1); - return; - } - if ((opcode & 0x38) != 0) { /* We can only do to integer register */ - FAIL(1); - return; - } + fflags_into_flags(S2); + reg = (opcode & 7); - fflags_into_flags(S2); - reg=(opcode&7); - - mov_l_ri(S1,255); - mov_l_ri(S4,0); - switch(extra&0x0f) { /* according to fpp.c, the 0x10 bit is ignored - */ - case 0: break; /* set never */ - case 1: mov_l_rr(S2,S4); - cmov_l_rr(S4,S1,4); - cmov_l_rr(S4,S2,10); break; - case 2: cmov_l_rr(S4,S1,7); break; - case 3: cmov_l_rr(S4,S1,3); break; - case 4: mov_l_rr(S2,S4); - cmov_l_rr(S4,S1,2); - cmov_l_rr(S4,S2,10); break; - case 5: mov_l_rr(S2,S4); - cmov_l_rr(S4,S1,6); - cmov_l_rr(S4,S2,10); break; - case 6: cmov_l_rr(S4,S1,5); break; - case 7: cmov_l_rr(S4,S1,11); break; - case 8: cmov_l_rr(S4,S1,10); break; - case 9: cmov_l_rr(S4,S1,4); break; - case 10: cmov_l_rr(S4,S1,10); cmov_l_rr(S4,S1,7); break; - case 11: cmov_l_rr(S4,S1,4); cmov_l_rr(S4,S1,3); break; - case 12: cmov_l_rr(S4,S1,2); break; - case 13: cmov_l_rr(S4,S1,6); break; - case 14: cmov_l_rr(S4,S1,5); cmov_l_rr(S4,S1,10); break; - case 15: mov_l_rr(S4,S1); break; - } + mov_l_ri(S1, 255); + mov_l_ri(S4, 0); + switch (extra & 0x0f) + { /* according to fpp.c, the 0x10 bit is ignored + */ + case 0: + break; /* set never */ + case 1: + mov_l_rr(S2, S4); + cmov_l_rr(S4, S1, 4); + cmov_l_rr(S4, S2, 10); + break; + case 2: + cmov_l_rr(S4, S1, 7); + break; + case 3: + cmov_l_rr(S4, S1, 3); + break; + case 4: + mov_l_rr(S2, S4); + cmov_l_rr(S4, S1, 2); + cmov_l_rr(S4, S2, 10); + break; + case 5: + mov_l_rr(S2, S4); + cmov_l_rr(S4, S1, 6); + cmov_l_rr(S4, S2, 10); + break; + case 6: + cmov_l_rr(S4, S1, 5); + break; + case 7: + cmov_l_rr(S4, S1, 11); + break; + case 8: + cmov_l_rr(S4, S1, 10); + break; + case 9: + cmov_l_rr(S4, S1, 4); + break; + case 10: + cmov_l_rr(S4, S1, 10); + cmov_l_rr(S4, S1, 7); + break; + case 11: + cmov_l_rr(S4, S1, 4); + cmov_l_rr(S4, S1, 3); + break; + case 12: + cmov_l_rr(S4, S1, 2); + break; + case 13: + cmov_l_rr(S4, S1, 6); + break; + case 14: + cmov_l_rr(S4, S1, 5); + cmov_l_rr(S4, S1, 10); + break; + case 15: + mov_l_rr(S4, S1); + break; + } - if ((opcode & 0x38) == 0) { - mov_b_rr(reg,S4); - } else { - abort(); - if (get_fp_ad (opcode, &ad) == 0) { - m68k_setpc (m68k_getpc () - 4); - fpuop_illg (opcode,extra); + if ((opcode & 0x38) == 0) + { + mov_b_rr(reg, S4); } else - put_byte (ad, cc ? 0xff : 0x00); - } + { + abort(); +#if 0 + int cc; + + if (get_fp_ad(opcode) < 0) + { + FAIL(1); + } else + { + put_byte(ad, cc ? 0xff : 0x00); + } +#endif + } } + void comp_ftrapcc_opp (uae_u32 /* opcode */, uaecptr /* oldpc */) { - FAIL(1); - return; -} - -void comp_fbcc_opp (uae_u32 opcode) -{ - uae_u32 start_68k_offset=m68k_pc_offset; - uae_u32 off; - uae_u32 v1; - uae_u32 v2; - int cc; - - // comp_pc_p is expected to be bound to 32-bit addresses - assert((uintptr)comp_pc_p <= 0xffffffffUL); - - if (opcode&0x20) { /* only cc from 00 to 1f are defined */ FAIL(1); return; - } - if ((opcode&0x40)==0) { - off=(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2); - } - else { - off=comp_get_ilong((m68k_pc_offset+=4)-4); - } - mov_l_ri(S1,(uintptr) - (comp_pc_p+off-(m68k_pc_offset-start_68k_offset))); - mov_l_ri(PC_P,(uintptr)comp_pc_p); - - /* Now they are both constant. Might as well fold in m68k_pc_offset */ - add_l_ri(S1,m68k_pc_offset); - add_l_ri(PC_P,m68k_pc_offset); - m68k_pc_offset=0; - - /* according to fpp.c, the 0x10 bit is ignored - (it handles exception handling, which we don't - do, anyway ;-) */ - cc=opcode&0x0f; - v1=get_const(PC_P); - v2=get_const(S1); - fflags_into_flags(S2); - - switch(cc) { - case 0: break; /* jump never */ - case 1: - mov_l_rr(S2,PC_P); - cmov_l_rr(PC_P,S1,4); - cmov_l_rr(PC_P,S2,10); break; - case 2: register_branch(v1,v2,7); break; - case 3: register_branch(v1,v2,3); break; - case 4: - mov_l_rr(S2,PC_P); - cmov_l_rr(PC_P,S1,2); - cmov_l_rr(PC_P,S2,10); break; - case 5: - mov_l_rr(S2,PC_P); - cmov_l_rr(PC_P,S1,6); - cmov_l_rr(PC_P,S2,10); break; - case 6: register_branch(v1,v2,5); break; - case 7: register_branch(v1,v2,11); break; - case 8: register_branch(v1,v2,10); break; - case 9: register_branch(v1,v2,4); break; - case 10: - cmov_l_rr(PC_P,S1,10); - cmov_l_rr(PC_P,S1,7); break; - case 11: - cmov_l_rr(PC_P,S1,4); - cmov_l_rr(PC_P,S1,3); break; - case 12: register_branch(v1,v2,2); break; - case 13: register_branch(v1,v2,6); break; - case 14: - cmov_l_rr(PC_P,S1,5); - cmov_l_rr(PC_P,S1,10); break; - case 15: mov_l_rr(PC_P,S1); break; - } } + +void comp_fbcc_opp(uae_u32 opcode) +{ + uae_u32 start_68k_offset = m68k_pc_offset; + uae_u32 off; + uae_u32 v1; + uae_u32 v2; + int cc; + + // comp_pc_p is expected to be bound to 32-bit addresses + assert((uintptr) comp_pc_p <= 0xffffffffUL); + + if (jit_disable.fbcc) + { + FAIL(1); + return; + } + if (opcode & 0x20) + { /* only cc from 00 to 1f are defined */ + FAIL(1); + return; + } + if ((opcode & 0x40) == 0) + { + off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2); + } else + { + off = comp_get_ilong((m68k_pc_offset += 4) - 4); + } + mov_l_ri(S1, (uintptr) (comp_pc_p + off - (m68k_pc_offset - start_68k_offset))); + mov_l_ri(PC_P, (uintptr) comp_pc_p); + + /* Now they are both constant. Might as well fold in m68k_pc_offset */ + add_l_ri(S1, m68k_pc_offset); + add_l_ri(PC_P, m68k_pc_offset); + m68k_pc_offset = 0; + + /* according to fpp.c, the 0x10 bit is ignored + (it handles exception handling, which we don't + do, anyway ;-) */ + cc = opcode & 0x0f; + v1 = get_const(PC_P); + v2 = get_const(S1); + fflags_into_flags(S2); + + switch (cc) + { + case 0: + break; /* jump never */ + case 1: + mov_l_rr(S2, PC_P); + cmov_l_rr(PC_P, S1, 4); + cmov_l_rr(PC_P, S2, 10); + break; + case 2: + register_branch(v1, v2, 7); + break; + case 3: + register_branch(v1, v2, 3); + break; + case 4: + mov_l_rr(S2, PC_P); + cmov_l_rr(PC_P, S1, 2); + cmov_l_rr(PC_P, S2, 10); + break; + case 5: + mov_l_rr(S2, PC_P); + cmov_l_rr(PC_P, S1, 6); + cmov_l_rr(PC_P, S2, 10); + break; + case 6: + register_branch(v1, v2, 5); + break; + case 7: + register_branch(v1, v2, 11); + break; + case 8: + register_branch(v1, v2, 10); + break; + case 9: + register_branch(v1, v2, 4); + break; + case 10: + cmov_l_rr(PC_P, S1, 10); + cmov_l_rr(PC_P, S1, 7); + break; + case 11: + cmov_l_rr(PC_P, S1, 4); + cmov_l_rr(PC_P, S1, 3); + break; + case 12: + register_branch(v1, v2, 2); + break; + case 13: + register_branch(v1, v2, 6); + break; + case 14: + cmov_l_rr(PC_P, S1, 5); + cmov_l_rr(PC_P, S1, 10); + break; + case 15: + mov_l_rr(PC_P, S1); + break; + } +} + + /* Floating point conditions The "NotANumber" part could be problematic; Howver, when NaN is encountered, the ftst instruction sets bot N and Z to 1 on the x87, @@ -784,150 +885,179 @@ x86 conditions 0001 : 10 1110 : 11 */ -void comp_fsave_opp (uae_u32 opcode) + +void comp_fsave_opp(uae_u32 opcode) { - uae_u32 ad; - int incr = (opcode & 0x38) == 0x20 ? -1 : 1; - int i; + int incr = (opcode & 0x38) == 0x20 ? -1 : 1; + int i; + int ad; - FAIL(1); - return; - -#ifdef DEBUG_FPP - printf ("fsave_opp at %08lx\n", m68k_getpc ()); - fflush (stdout); -#endif - if (get_fp_ad (opcode, &ad) == 0) { - m68k_setpc (m68k_getpc () - 2); - fpuop_illg (opcode,UNKNOWN_EXTRA); + if (jit_disable.fsave) + { + FAIL(1); + return; + } + FAIL(1); return; - } - if (CPUType == 4) { - /* 4 byte 68040 IDLE frame. */ - if (incr < 0) { - ad -= 4; - put_long (ad, 0x41000000); - } else { - put_long (ad, 0x41000000); - ad += 4; + if ((ad = get_fp_ad(opcode)) < 0) + { + FAIL(1); + return; } - } else { - if (incr < 0) { - ad -= 4; - put_long (ad, 0x70000000); - for (i = 0; i < 5; i++) { - ad -= 4; - put_long (ad, 0x00000000); - } - ad -= 4; - put_long (ad, 0x1f180000); - } else { - put_long (ad, 0x1f180000); - ad += 4; - for (i = 0; i < 5; i++) { - put_long (ad, 0x00000000); - ad += 4; - } - put_long (ad, 0x70000000); - ad += 4; + + if (CPUType == 4) + { + /* 4 byte 68040 IDLE frame. */ + if (incr < 0) + { + ad -= 4; + put_long(ad, 0x41000000); + } else + { + put_long(ad, 0x41000000); + ad += 4; + } + } else + { + if (incr < 0) + { + ad -= 4; + put_long(ad, 0x70000000); + for (i = 0; i < 5; i++) + { + ad -= 4; + put_long(ad, 0x00000000); + } + ad -= 4; + put_long(ad, 0x1f180000); + } else + { + put_long(ad, 0x1f180000); + ad += 4; + for (i = 0; i < 5; i++) + { + put_long(ad, 0x00000000); + ad += 4; + } + put_long(ad, 0x70000000); + ad += 4; + } } - } - if ((opcode & 0x38) == 0x18) - m68k_areg (regs, opcode & 7) = ad; - if ((opcode & 0x38) == 0x20) - m68k_areg (regs, opcode & 7) = ad; + if ((opcode & 0x38) == 0x18) + m68k_areg(regs, opcode & 7) = ad; + if ((opcode & 0x38) == 0x20) + m68k_areg(regs, opcode & 7) = ad; } -void comp_frestore_opp (uae_u32 opcode) + +void comp_frestore_opp(uae_u32 opcode) { - uae_u32 ad; - uae_u32 d; - int incr = (opcode & 0x38) == 0x20 ? -1 : 1; + uae_u32 d; + int incr = (opcode & 0x38) == 0x20 ? -1 : 1; + int ad; - FAIL(1); - return; - -#ifdef DEBUG_FPP - printf ("frestore_opp at %08lx\n", m68k_getpc ()); - fflush (stdout); -#endif - if (get_fp_ad (opcode, &ad) == 0) { - m68k_setpc (m68k_getpc () - 2); - fpuop_illg (opcode,UNKNOWN_EXTRA); + if (jit_disable.frestore) + { + FAIL(1); + return; + } + FAIL(1); return; - } - if (CPUType == 4) { - /* 68040 */ - if (incr < 0) { - /* @@@ This may be wrong. */ - ad -= 4; - d = get_long (ad); - if ((d & 0xff000000) != 0) { /* Not a NULL frame? */ - if ((d & 0x00ff0000) == 0) { /* IDLE */ - } else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */ - ad -= 44; - } else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */ - ad -= 92; - } - } - } else { - d = get_long (ad); - ad += 4; - if ((d & 0xff000000) != 0) { /* Not a NULL frame? */ - if ((d & 0x00ff0000) == 0) { /* IDLE */ - } else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */ - ad += 44; - } else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */ - ad += 92; - } - } + + if ((ad = get_fp_ad(opcode)) < 0) + { + FAIL(1); + return; } - } else { - if (incr < 0) { - ad -= 4; - d = get_long (ad); - if ((d & 0xff000000) != 0) { - if ((d & 0x00ff0000) == 0x00180000) - ad -= 6 * 4; - else if ((d & 0x00ff0000) == 0x00380000) - ad -= 14 * 4; - else if ((d & 0x00ff0000) == 0x00b40000) - ad -= 45 * 4; - } - } else { - d = get_long (ad); - ad += 4; - if ((d & 0xff000000) != 0) { - if ((d & 0x00ff0000) == 0x00180000) - ad += 6 * 4; - else if ((d & 0x00ff0000) == 0x00380000) - ad += 14 * 4; - else if ((d & 0x00ff0000) == 0x00b40000) - ad += 45 * 4; - } + if (CPUType == 4) + { + /* 68040 */ + if (incr < 0) + { + /* @@@ This may be wrong. */ + ad -= 4; + d = get_long(ad); + if ((d & 0xff000000) != 0) + { /* Not a NULL frame? */ + if ((d & 0x00ff0000) == 0) + { /* IDLE */ + } else if ((d & 0x00ff0000) == 0x00300000) + { /* UNIMP */ + ad -= 44; + } else if ((d & 0x00ff0000) == 0x00600000) + { /* BUSY */ + ad -= 92; + } + } + } else + { + d = get_long(ad); + ad += 4; + if ((d & 0xff000000) != 0) + { /* Not a NULL frame? */ + if ((d & 0x00ff0000) == 0) + { /* IDLE */ + } else if ((d & 0x00ff0000) == 0x00300000) + { /* UNIMP */ + ad += 44; + } else if ((d & 0x00ff0000) == 0x00600000) + { /* BUSY */ + ad += 92; + } + } + } + } else + { + if (incr < 0) + { + ad -= 4; + d = get_long(ad); + if ((d & 0xff000000) != 0) + { + if ((d & 0x00ff0000) == 0x00180000) + ad -= 6 * 4; + else if ((d & 0x00ff0000) == 0x00380000) + ad -= 14 * 4; + else if ((d & 0x00ff0000) == 0x00b40000) + ad -= 45 * 4; + } + } else + { + d = get_long(ad); + ad += 4; + if ((d & 0xff000000) != 0) + { + if ((d & 0x00ff0000) == 0x00180000) + ad += 6 * 4; + else if ((d & 0x00ff0000) == 0x00380000) + ad += 14 * 4; + else if ((d & 0x00ff0000) == 0x00b40000) + ad += 45 * 4; + } + } } - } - if ((opcode & 0x38) == 0x18) - m68k_areg (regs, opcode & 7) = ad; - if ((opcode & 0x38) == 0x20) - m68k_areg (regs, opcode & 7) = ad; + if ((opcode & 0x38) == 0x18) + m68k_areg(regs, opcode & 7) = ad; + if ((opcode & 0x38) == 0x20) + m68k_areg(regs, opcode & 7) = ad; } -#if USE_LONG_DOUBLE -static const fpu_register const_e = 2.7182818284590452353602874713526625L; -static const fpu_register const_log10_e = 0.4342944819032518276511289189166051L; -static const fpu_register const_loge_10 = 2.3025850929940456840179914546843642L; + +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) +static const fpu_register const_e = LD(2.7182818284590452353); // LD(2.7182818284590452353602874713526625); +static const fpu_register const_log10_e = LD(0.4342944819032518276511289189166051); +static const fpu_register const_loge_10 = LD(2.3025850929940456840179914546843642); #else -static const fpu_register const_e = 2.7182818284590452354; +static const fpu_register const_e = 2.7182818284590452354; static const fpu_register const_log10_e = 0.43429448190325182765; static const fpu_register const_loge_10 = 2.30258509299404568402; #endif static const fpu_register power10[] = { - 1e0, 1e1, 1e2, 1e4, 1e8, 1e16, 1e32, 1e64, 1e128, 1e256 -#if USE_LONG_DOUBLE -, 1e512L, 1e1024L, 1e2048L, 1e4096L + LD(1e0), LD(1e1), LD(1e2), LD(1e4), LD(1e8), LD(1e16), LD(1e32), LD(1e64), LD(1e128), LD(1e256) +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) +, LD(1e512), LD(1e1024), LD(1e2048), LD(1e4096) #endif }; @@ -958,277 +1088,346 @@ static uae_u16 x86_fpucw[]={ #endif -void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) +void comp_fpp_opp(uae_u32 opcode, uae_u16 extra) { - int reg; - int src; - - switch ((extra >> 13) & 0x7) { - case 3: /* 2nd most common */ - if (put_fp_value ((extra >> 7)&7 , opcode, extra) < 0) { - FAIL(1); - return; + int reg; + int src; - } - return; - case 6: - case 7: + switch ((extra >> 13) & 0x7) { - uae_u32 ad, list = 0; - int incr = 0; - if (extra & 0x2000) { + case 1: /* illegal */ + break; - /* FMOVEM FPP->memory */ - switch ((extra >> 11) & 3) { /* Get out early if failure */ - case 0: - case 2: - break; - case 1: - case 3: - default: - FAIL(1); return; - } - ad=get_fp_ad (opcode, &ad); - if ((uae_s32)ad<0) { - m68k_setpc (m68k_getpc () - 4); - fpuop_illg (opcode,extra); - return; - } - switch ((extra >> 11) & 3) { - case 0: /* static pred */ - list = extra & 0xff; - incr = -1; - break; - case 2: /* static postinc */ - list = extra & 0xff; - incr = 1; - break; - case 1: /* dynamic pred */ - case 3: /* dynamic postinc */ - abort(); - } - if (incr < 0) { /* Predecrement */ - for (reg = 7; reg >= 0; reg--) { - if (list & 0x80) { - fmov_ext_mr((uintptr)temp_fp,reg); - delay; - sub_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - sub_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp+4); - writelong_clobber(ad,S2,S3); - sub_l_ri(ad,4); - mov_w_rm(S2,(uintptr)temp_fp+8); - writeword_clobber(ad,S2,S3); - } - list <<= 1; - } - } - else { /* Postincrement */ - for (reg = 0; reg < 8; reg++) { - if (list & 0x80) { - fmov_ext_mr((uintptr)temp_fp,reg); - delay; - mov_w_rm(S2,(uintptr)temp_fp+8); - writeword_clobber(ad,S2,S3); - add_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp+4); - writelong_clobber(ad,S2,S3); - add_l_ri(ad,4); - mov_l_rm(S2,(uintptr)temp_fp); - writelong_clobber(ad,S2,S3); - add_l_ri(ad,4); - } - list <<= 1; - } - } - if ((opcode & 0x38) == 0x18) - mov_l_rr((opcode & 7)+8,ad); - if ((opcode & 0x38) == 0x20) - mov_l_rr((opcode & 7)+8,ad); - } else { - /* FMOVEM memory->FPP */ - - uae_u32 ad; - switch ((extra >> 11) & 3) { /* Get out early if failure */ - case 0: - case 2: - break; - case 1: - case 3: - default: - FAIL(1); return; - } - ad=get_fp_ad (opcode, &ad); - if ((uae_s32)ad<0) { - m68k_setpc (m68k_getpc () - 4); - D(bug("no ad\n")); - fpuop_illg (opcode,extra); - return; - } - switch ((extra >> 11) & 3) { - case 0: /* static pred */ - list = extra & 0xff; - incr = -1; - break; - case 2: /* static postinc */ - list = extra & 0xff; - incr = 1; - break; - case 1: /* dynamic pred */ - case 3: /* dynamic postinc */ - abort(); - } - - if (incr < 0) { - // not reached - for (reg = 7; reg >= 0; reg--) { - if (list & 0x80) { - sub_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp),S2); - sub_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp)+4,S2); - sub_l_ri(ad,4); - readword(ad,S2,S3); - mov_w_mr(((uintptr)temp_fp)+8,S2); - delay2; - fmov_ext_rm(reg,(uintptr)(temp_fp)); - } - list <<= 1; - } - } - else { - for (reg = 0; reg < 8; reg++) { - if (list & 0x80) { - readword(ad,S2,S3); - mov_w_mr(((uintptr)temp_fp)+8,S2); - add_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp)+4,S2); - add_l_ri(ad,4); - readlong(ad,S2,S3); - mov_l_mr((uintptr)(temp_fp),S2); - add_l_ri(ad,4); - delay2; - fmov_ext_rm(reg,(uintptr)(temp_fp)); - } - list <<= 1; - } - } - if ((opcode & 0x38) == 0x18) - mov_l_rr((opcode & 7)+8,ad); - if ((opcode & 0x38) == 0x20) - mov_l_rr((opcode & 7)+8,ad); - } - } - return; - - case 4: - case 5: /* rare */ - if ((opcode & 0x30) == 0) { - if (extra & 0x2000) { - if (extra & 0x1000) { -#if HANDLE_FPCR - mov_l_rm(opcode & 15, (uintptr)&fpu.fpcr.rounding_mode); - or_l_rm(opcode & 15, (uintptr)&fpu.fpcr.rounding_precision); -#else + case 3: /* FMOVE Fpn, */ + /* 2nd most common */ + if (jit_disable.fmove) + { FAIL(1); return; -#endif } - if (extra & 0x0800) { - FAIL(1); - return; - } - if (extra & 0x0400) { - mov_l_rm(opcode & 15,(uintptr)&fpu.instruction_address); - return; - } - } else { - // gb-- moved here so that we may FAIL() without generating any code - if (extra & 0x0800) { - // set_fpsr(m68k_dreg (regs, opcode & 15)); - FAIL(1); - return; - } - if (extra & 0x1000) { -#if HANDLE_FPCR -#if defined(FPU_USE_X86_ROUNDING_MODE) && defined(FPU_USE_X86_ROUNDING_PRECISION) + + if (put_fp_value((extra >> 7) & 7, opcode, extra) < 0) + { FAIL(1); return; -#endif - mov_l_rr(S1,opcode & 15); - mov_l_rr(S2,opcode & 15); - and_l_ri(S1,FPCR_ROUNDING_PRECISION); - and_l_ri(S2,FPCR_ROUNDING_MODE); - mov_l_mr((uintptr)&fpu.fpcr.rounding_precision,S1); - mov_l_mr((uintptr)&fpu.fpcr.rounding_mode,S2); -#else - FAIL(1); - return; -#endif -// return; gb-- FMOVEM could also operate on fpiar - } - if (extra & 0x0400) { - mov_l_mr((uintptr)&fpu.instruction_address,opcode & 15); -// return; gb-- we have to process all FMOVEM bits before returning } return; - } - } else if ((opcode & 0x3f) == 0x3c) { - if ((extra & 0x2000) == 0) { - // gb-- moved here so that we may FAIL() without generating any code - if (extra & 0x0800) { - FAIL(1); - return; - } - if (extra & 0x1000) { - comp_get_ilong((m68k_pc_offset+=4)-4); -#if HANDLE_FPCR -#if defined(FPU_USE_X86_ROUNDING_MODE) && defined(FPU_USE_X86_ROUNDING_PRECISION) + + case 6: /* FMOVEM , */ + case 7: /* FMOVEM , */ + if (jit_disable.fmovem) + { FAIL(1); return; -#endif -// mov_l_mi((uintptr)®s.fpcr,val); - mov_l_ri(S1,val); - mov_l_ri(S2,val); - and_l_ri(S1,FPCR_ROUNDING_PRECISION); - and_l_ri(S2,FPCR_ROUNDING_MODE); - mov_l_mr((uintptr)&fpu.fpcr.rounding_precision,S1); - mov_l_mr((uintptr)&fpu.fpcr.rounding_mode,S2); -#else - FAIL(1); - return; -#endif -// return; gb-- FMOVEM could also operate on fpiar } - if (extra & 0x0400) { - uae_u32 val=comp_get_ilong((m68k_pc_offset+=4)-4); - mov_l_mi((uintptr)&fpu.instruction_address,val); -// return; gb-- we have to process all FMOVEM bits before returning + + { + int ad; + uae_u32 list = 0; + int incr = 0; + + if (extra & 0x2000) + { + /* FMOVEM FPP->memory */ + switch ((extra >> 11) & 3) + { /* Get out early if failure */ + case 0: /* static pred */ + case 2: /* static postinc */ + break; + case 1: /* dynamic pred */ + case 3: /* dynamic postinc */ + default: + FAIL(1); + return; + } + if ((ad = get_fp_ad(opcode)) < 0) + { + FAIL(1); + return; + } + switch ((extra >> 11) & 3) + { + case 0: /* static pred */ + list = extra & 0xff; + incr = -1; + break; + case 2: /* static postinc */ + list = extra & 0xff; + incr = 1; + break; + case 1: /* dynamic pred */ + case 3: /* dynamic postinc */ + abort(); + } + if (incr < 0) + { /* Predecrement */ + for (reg = 7; reg >= 0; reg--) + { + if (list & 0x80) + { + fmov_ext_mr((uintptr) temp_fp, reg); + delay; + sub_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + sub_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp + 4); + writelong_clobber(ad, S2, S3); + sub_l_ri(ad, 4); + mov_w_rm(S2, (uintptr) temp_fp + 8); + writeword_clobber(ad, S2, S3); + } + list <<= 1; + } + } else + { /* Postincrement */ + for (reg = 0; reg < 8; reg++) + { + if (list & 0x80) + { + fmov_ext_mr((uintptr) temp_fp, reg); + delay; + mov_w_rm(S2, (uintptr) temp_fp + 8); + writeword_clobber(ad, S2, S3); + add_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp + 4); + writelong_clobber(ad, S2, S3); + add_l_ri(ad, 4); + mov_l_rm(S2, (uintptr) temp_fp); + writelong_clobber(ad, S2, S3); + add_l_ri(ad, 4); + } + list <<= 1; + } + } + if ((opcode & 0x38) == 0x18) + mov_l_rr((opcode & 7) + 8, ad); + if ((opcode & 0x38) == 0x20) + mov_l_rr((opcode & 7) + 8, ad); + } else + { + /* FMOVEM memory->FPP */ + + int ad; + + switch ((extra >> 11) & 3) + { /* Get out early if failure */ + case 0: /* static pred */ + case 2: /* static postinc */ + break; + case 1: /* dynamic pred */ + case 3: /* dynamic postinc */ + default: + FAIL(1); + return; + } + ad = get_fp_ad(opcode); + if (ad < 0) + { + D(bug("no ad\n")); + FAIL(1); + return; + } + switch ((extra >> 11) & 3) + { + case 0: /* static pred */ + list = extra & 0xff; + incr = -1; + break; + case 2: /* static postinc */ + list = extra & 0xff; + incr = 1; + break; + case 1: /* dynamic pred */ + case 3: /* dynamic postinc */ + abort(); + } + + if (incr < 0) + { + // not reached + for (reg = 7; reg >= 0; reg--) + { + if (list & 0x80) + { + sub_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp), S2); + sub_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp) + 4, S2); + sub_l_ri(ad, 4); + readword(ad, S2, S3); + mov_w_mr(((uintptr) temp_fp) + 8, S2); + delay2; + fmov_ext_rm(reg, (uintptr) (temp_fp)); + } + list <<= 1; + } + } else + { + for (reg = 0; reg < 8; reg++) + { + if (list & 0x80) + { + readword(ad, S2, S3); + mov_w_mr(((uintptr) temp_fp) + 8, S2); + add_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp) + 4, S2); + add_l_ri(ad, 4); + readlong(ad, S2, S3); + mov_l_mr((uintptr) (temp_fp), S2); + add_l_ri(ad, 4); + delay2; + fmov_ext_rm(reg, (uintptr) (temp_fp)); + } + list <<= 1; + } + } + if ((opcode & 0x38) == 0x18) + mov_l_rr((opcode & 7) + 8, ad); + if ((opcode & 0x38) == 0x20) + mov_l_rr((opcode & 7) + 8, ad); + } } return; - } - FAIL(1); - return; - } else if (extra & 0x2000) { - FAIL(1); - return; - } else { - FAIL(1); - return; - } - FAIL(1); - return; + + case 4: /* FMOVEM , */ + case 5: /* FMOVEM , */ + if (jit_disable.fmovec) + { + FAIL(1); + return; + } + + /* rare */ + if ((opcode & 0x30) == 0) + { + /* = Dn or An */ + if (extra & 0x2000) + { + if (extra & 0x1000) + { +#if HANDLE_FPCR + mov_l_rm(opcode & 15, (uintptr) & fpu.fpcr.rounding_mode); + or_l_rm(opcode & 15, (uintptr) & fpu.fpcr.rounding_precision); +#else + FAIL(1); + return; +#endif + } + if (extra & 0x0800) + { + FAIL(1); + return; + } + if (extra & 0x0400) + { + /* FPIAR: fixme; we cannot correctly return the address from compiled code */ + mov_l_rm(opcode & 15, (uintptr) & fpu.instruction_address); + return; + } + } else + { + // gb-- moved here so that we may FAIL() without generating any code + if (extra & 0x0800) + { + // set_fpsr(m68k_dreg (regs, opcode & 15)); + FAIL(1); + return; + } + if (extra & 0x1000) + { +#if HANDLE_FPCR +#if defined(FPU_USE_X86_ROUNDING_MODE) && defined(FPU_USE_X86_ROUNDING_PRECISION) + FAIL(1); + return; +#endif + mov_l_rr(S1, opcode & 15); + mov_l_rr(S2, opcode & 15); + and_l_ri(S1, FPCR_ROUNDING_PRECISION); + and_l_ri(S2, FPCR_ROUNDING_MODE); + mov_l_mr((uintptr) & fpu.fpcr.rounding_precision, S1); + mov_l_mr((uintptr) & fpu.fpcr.rounding_mode, S2); +#else + FAIL(1); + return; +#endif + } + if (extra & 0x0400) + { + /* FPIAR: does that make sense at all? */ + mov_l_mr((uintptr) & fpu.instruction_address, opcode & 15); + } + return; + } + } else if ((opcode & 0x3f) == 0x3c) + { + /* = #imm */ + if ((extra & 0x2000) == 0) + { + // gb-- moved here so that we may FAIL() without generating any code + if (extra & 0x0800) + { + FAIL(1); + return; + } + if (extra & 0x1000) + { + comp_get_ilong((m68k_pc_offset += 4) - 4); +#if HANDLE_FPCR +#if defined(FPU_USE_X86_ROUNDING_MODE) && defined(FPU_USE_X86_ROUNDING_PRECISION) + FAIL(1); + return; +#endif + // mov_l_mi((uintptr)®s.fpcr,val); + mov_l_ri(S1, val); + mov_l_ri(S2, val); + and_l_ri(S1, FPCR_ROUNDING_PRECISION); + and_l_ri(S2, FPCR_ROUNDING_MODE); + mov_l_mr((uintptr) & fpu.fpcr.rounding_precision, S1); + mov_l_mr((uintptr) & fpu.fpcr.rounding_mode, S2); +#else + FAIL(1); + return; +#endif + } + if (extra & 0x0400) + { + uae_u32 val = comp_get_ilong((m68k_pc_offset += 4) - 4); + + mov_l_mi((uintptr) & fpu.instruction_address, val); + } + return; + } + FAIL(1); + return; + } else if (extra & 0x2000) + { + FAIL(1); + return; + } else + { + FAIL(1); + return; + } + FAIL(1); + return; case 0: - case 2: /* Extremely common */ + case 2: /* Extremely common */ reg = (extra >> 7) & 7; - if ((extra & 0xfc00) == 0x5c00) { - switch (extra & 0x7f) { + if ((extra & 0xfc00) == 0x5c00) + { + if (jit_disable.fmovecr) + { + FAIL(1); + return; + } + + switch (extra & 0x7f) + { case 0x00: fmov_pi(reg); break; @@ -1236,20 +1435,20 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) fmov_log10_2(reg); break; case 0x0c: -#if USE_LONG_DOUBLE - fmov_ext_rm(reg,(uintptr)&const_e); +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) + fmov_ext_rm(reg, (uintptr) & const_e); #else - fmov_rm(reg,(uintptr)&const_e); + fmov_rm(reg, (uintptr) & const_e); #endif break; case 0x0d: fmov_log2_e(reg); break; case 0x0e: -#if USE_LONG_DOUBLE - fmov_ext_rm(reg,(uintptr)&const_log10_e); +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) + fmov_ext_rm(reg, (uintptr) & const_log10_e); #else - fmov_rm(reg,(uintptr)&const_log10_e); + fmov_rm(reg, (uintptr) & const_log10_e); #endif break; case 0x0f: @@ -1259,10 +1458,10 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) fmov_loge_2(reg); break; case 0x31: -#if USE_LONG_DOUBLE - fmov_ext_rm(reg,(uintptr)&const_loge_10); +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) + fmov_ext_rm(reg, (uintptr) & const_loge_10); #else - fmov_rm(reg,(uintptr)&const_loge_10); + fmov_rm(reg, (uintptr) & const_loge_10); #endif break; case 0x32: @@ -1277,14 +1476,14 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) case 0x39: case 0x3a: case 0x3b: -#if USE_LONG_DOUBLE +#if defined(USE_LONG_DOUBLE) || defined(USE_QUAD_DOUBLE) case 0x3c: case 0x3d: case 0x3e: case 0x3f: - fmov_ext_rm(reg,(uintptr)(power10+(extra & 0x7f)-0x32)); + fmov_ext_rm(reg, (uintptr) (power10 + (extra & 0x7f) - 0x32)); #else - fmov_rm(reg,(uintptr)(power10+(extra & 0x7f)-0x32)); + fmov_rm(reg, (uintptr) (power10 + (extra & 0x7f) - 0x32)); #endif break; default: @@ -1294,310 +1493,536 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) } return; } - - switch (extra & 0x7f) { - case 0x00: /* FMOVE */ - case 0x40: /* Explicit rounding. This is just a quick fix. Same - * for all other cases that have three choices */ - case 0x44: - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + + switch (extra & 0x7f) + { + case 0x00: /* FMOVE */ + case 0x40: /* FSMOVE: Explicit rounding. This is just a quick fix. Same + * for all other cases that have three choices */ + case 0x44: /* FDMOVE */ + if (jit_disable.fmove) + { + FAIL(1); return; } - fmov_rr(reg,src); - MAKE_FPSR (src); + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fmov_rr(reg, src); + MAKE_FPSR(src); break; - case 0x01: /* FINT */ - FAIL(1); + case 0x01: /* FINT */ + if (jit_disable.fint) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x02: /* FSINH */ - FAIL(1); + case 0x02: /* FSINH */ + if (jit_disable.fsinh) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x03: /* FINTRZ */ -#ifdef USE_X86_FPUCW + case 0x03: /* FINTRZ */ + if (jit_disable.fintrz) + { + FAIL(1); + return; + } +#ifdef USE_X86_FPUCW /* If we have control over the CW, we can do this */ dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ return; } - mov_l_ri(S1,16); /* Switch to "round to zero" mode */ - fldcw_m_indexed(S1,(uae_u32)x86_fpucw); - - frndint_rr(reg,src); + mov_l_ri(S1, 16); /* Switch to "round to zero" mode */ + fldcw_m_indexed(S1, (uintptr) x86_fpucw); + + frndint_rr(reg, src); /* restore control word */ - mov_l_rm(S1,(uintptr)®s.fpcr); - and_l_ri(S1,0x000000f0); - fldcw_m_indexed(S1,(uintptr)x86_fpucw); + mov_l_rm(S1, (uintptr) & regs.fpcr); + and_l_ri(S1, 0x000000f0); + fldcw_m_indexed(S1, (uintptr) x86_fpucw); - MAKE_FPSR (reg); + MAKE_FPSR(reg); break; -#endif - FAIL(1); +#endif + FAIL(1); return; break; - case 0x04: /* FSQRT */ - case 0x41: - case 0x45: - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x04: /* FSQRT */ + case 0x41: /* FSSQRT */ + case 0x45: /* FDSQRT */ + if (jit_disable.fsqrt) + { + FAIL(1); return; } - fsqrt_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x06: /* FLOGNP1 */ - FAIL(1); - return; + dont_care_fflags(); - break; - case 0x08: /* FETOXM1 */ - FAIL(1); - return; - dont_care_fflags(); - break; - case 0x09: /* FTANH */ - FAIL(1); - return; - dont_care_fflags(); - break; - case 0x0a: /* FATAN */ - FAIL(1); - return; - dont_care_fflags(); - break; - case 0x0c: /* FASIN */ - FAIL(1); - return; - dont_care_fflags(); - break; - case 0x0d: /* FATANH */ - FAIL(1); - return; - dont_care_fflags(); - break; - case 0x0e: /* FSIN */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ return; } - fsin_rr(reg,src); - MAKE_FPSR (reg); + fsqrt_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x0f: /* FTAN */ - FAIL(1); + case 0x06: /* FLOGNP1 */ + if (jit_disable.flognp1) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x10: /* FETOX */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x08: /* FETOXM1 */ + if (jit_disable.fetoxm1) + { + FAIL(1); return; } - fetox_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x11: /* FTWOTOX */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ - return; - } - ftwotox_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x12: /* FTENTOX */ - FAIL(1); + + FAIL(1); return; dont_care_fflags(); break; - case 0x14: /* FLOGN */ - FAIL(1); + case 0x09: /* FTANH */ + if (jit_disable.ftanh) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x15: /* FLOG10 */ - FAIL(1); + case 0x0a: /* FATAN */ + if (jit_disable.fatan) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x16: /* FLOG2 */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x0c: /* FASIN */ + if (jit_disable.fasin) + { + FAIL(1); return; } - flog2_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x18: /* FABS */ - case 0x58: - case 0x5c: - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ - return; - } - fabs_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x19: /* FCOSH */ - FAIL(1); + + FAIL(1); return; dont_care_fflags(); break; - case 0x1a: /* FNEG */ - case 0x5a: - case 0x5e: - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x0d: /* FATANH */ + if (jit_disable.fatanh) + { + FAIL(1); return; } - fneg_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x1c: /* FACOS */ - FAIL(1); + + FAIL(1); return; dont_care_fflags(); break; - case 0x1d: /* FCOS */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x0e: /* FSIN */ + if (jit_disable.fsin) + { + FAIL(1); return; } - fcos_rr(reg,src); - MAKE_FPSR (reg); + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fsin_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x1e: /* FGETEXP */ - FAIL(1); + case 0x0f: /* FTAN */ + if (jit_disable.ftan) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x1f: /* FGETMAN */ - FAIL(1); + case 0x10: /* FETOX */ + if (jit_disable.fetox) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fetox_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x11: /* FTWOTOX */ + if (jit_disable.ftwotox) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + ftwotox_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x12: /* FTENTOX */ + if (jit_disable.ftentox) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x20: /* FDIV */ - case 0x60: - case 0x64: - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x14: /* FLOGN */ + if (jit_disable.flogn) + { + FAIL(1); return; } - fdiv_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x21: /* FMOD */ + + FAIL(1); + return; dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + break; + case 0x15: /* FLOG10 */ + if (jit_disable.flog10) + { + FAIL(1); return; } - frem_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x22: /* FADD */ - case 0x62: - case 0x66: + + FAIL(1); + return; dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + break; + case 0x16: /* FLOG2 */ + if (jit_disable.flog2) + { + FAIL(1); return; } - fadd_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x23: /* FMUL */ - case 0x63: - case 0x67: + dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ return; } - fmul_rr(reg,src); - MAKE_FPSR (reg); + flog2_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x24: /* FSGLDIV */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x18: /* FABS */ + case 0x58: /* FSABS */ + case 0x5c: /* FDABS */ + if (jit_disable.fabs) + { + FAIL(1); return; } - fdiv_rr(reg,src); - MAKE_FPSR (reg); + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fabs_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x25: /* FREM */ + case 0x19: /* FCOSH */ + if (jit_disable.fcosh) + { + FAIL(1); + return; + } + + FAIL(1); + return; + dont_care_fflags(); + break; + case 0x1a: /* FNEG */ + case 0x5a: /* FSNEG */ + case 0x5e: /* FDNEG */ + if (jit_disable.fneg) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fneg_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x1c: /* FACOS */ + if (jit_disable.facos) + { + FAIL(1); + return; + } + + FAIL(1); + return; + dont_care_fflags(); + break; + case 0x1d: /* FCOS */ + if (jit_disable.fcos) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fcos_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x1e: /* FGETEXP */ + if (jit_disable.fgetexp) + { + FAIL(1); + return; + } + + FAIL(1); + return; + dont_care_fflags(); + break; + case 0x1f: /* FGETMAN */ + if (jit_disable.fgetman) + { + FAIL(1); + return; + } + + FAIL(1); + return; + dont_care_fflags(); + break; + case 0x20: /* FDIV */ + case 0x60: /* FSDIV */ + case 0x64: /* FDDIV */ + if (jit_disable.fdiv) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fdiv_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x21: /* FMOD */ + if (jit_disable.fmod) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + frem_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x22: /* FADD */ + case 0x62: /* FSADD */ + case 0x66: /* FDADD */ + if (jit_disable.fadd) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fadd_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x23: /* FMUL */ + case 0x63: /* FSMUL */ + case 0x67: /* FDMUL */ + if (jit_disable.fmul) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fmul_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x24: /* FSGLDIV */ + if (jit_disable.fsgldiv) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fdiv_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x25: /* FREM */ + if (jit_disable.frem) + { + FAIL(1); + return; + } // gb-- disabled because the quotient byte must be computed // otherwise, free rotation in ClarisWorks doesn't work. FAIL(1); return; dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ return; } - frem1_rr(reg,src); - MAKE_FPSR (reg); + frem1_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x26: /* FSCALE */ - dont_care_fflags(); - FAIL(1); + case 0x26: /* FSCALE */ + if (jit_disable.fscale) + { + FAIL(1); + return; + } + + FAIL(1); return; break; - case 0x27: /* FSGLMUL */ - dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x27: /* FSGLMUL */ + if (jit_disable.fsglmul) + { + FAIL(1); return; } - fmul_rr(reg,src); - MAKE_FPSR (reg); - break; - case 0x28: /* FSUB */ - case 0x68: - case 0x6c: + dont_care_fflags(); - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ return; } - fsub_rr(reg,src); - MAKE_FPSR (reg); + fmul_rr(reg, src); + MAKE_FPSR(reg); break; - case 0x30: /* FSINCOS */ + case 0x28: /* FSUB */ + case 0x68: /* FSSUB */ + case 0x6c: /* FDSUB */ + if (jit_disable.fsub) + { + FAIL(1); + return; + } + + dont_care_fflags(); + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fsub_rr(reg, src); + MAKE_FPSR(reg); + break; + case 0x30: /* FSINCOS */ case 0x31: case 0x32: case 0x33: @@ -1605,34 +2030,53 @@ void comp_fpp_opp (uae_u32 opcode, uae_u16 extra) case 0x35: case 0x36: case 0x37: - FAIL(1); + if (jit_disable.fsincos) + { + FAIL(1); + return; + } + + FAIL(1); return; dont_care_fflags(); break; - case 0x38: /* FCMP */ - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x38: /* FCMP */ + if (jit_disable.fcmp) + { + FAIL(1); return; } - fmov_rr(FP_RESULT,reg); - fsub_rr(FP_RESULT,src); /* Right way? */ + + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fmov_rr(FP_RESULT, reg); + fsub_rr(FP_RESULT, src); /* Right way? */ break; - case 0x3a: /* FTST */ - src=get_fp_value (opcode, extra); - if (src < 0) { - FAIL(1); /* Illegal instruction */ + case 0x3a: /* FTST */ + if (jit_disable.ftst) + { + FAIL(1); return; } - fmov_rr(FP_RESULT,src); + + src = get_fp_value(opcode, extra); + if (src < 0) + { + FAIL(1); /* Illegal instruction */ + return; + } + fmov_rr(FP_RESULT, src); break; default: - FAIL(1); + FAIL(1); return; break; } return; - } - m68k_setpc (m68k_getpc () - 4); - fpuop_illg (opcode,extra); + } + FAIL(1); } diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp index 6c1ede09..4fa745b4 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp +++ b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp @@ -61,13 +61,11 @@ MIDFUNC(0,live_flags,(void)) live.flags_in_flags=VALID; live.flags_are_important=1; } -MENDFUNC(0,live_flags,(void)) MIDFUNC(0,dont_care_flags,(void)) { live.flags_are_important=0; } -MENDFUNC(0,dont_care_flags,(void)) MIDFUNC(0,duplicate_carry,(void)) { @@ -76,7 +74,6 @@ MIDFUNC(0,duplicate_carry,(void)) COMPCALL(setcc_m)((uintptr)live.state[FLAGX].mem,NATIVE_CC_CS); log_vwrite(FLAGX); } -MENDFUNC(0,duplicate_carry,(void)) MIDFUNC(0,restore_carry,(void)) { @@ -100,25 +97,21 @@ MIDFUNC(0,restore_carry,(void)) } #endif } -MENDFUNC(0,restore_carry,(void)) MIDFUNC(0,start_needflags,(void)) { needflags=1; } -MENDFUNC(0,start_needflags,(void)) MIDFUNC(0,end_needflags,(void)) { needflags=0; } -MENDFUNC(0,end_needflags,(void)) MIDFUNC(0,make_flags_live,(void)) { make_flags_live_internal(); } -MENDFUNC(0,make_flags_live,(void)) MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ { @@ -130,7 +123,6 @@ MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ raw_bt_l_ri(r,i); unlock2(r); } -MENDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ { @@ -141,7 +133,6 @@ MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ unlock2(r); unlock2(b); } -MENDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) { @@ -152,7 +143,6 @@ MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) { @@ -163,7 +153,6 @@ MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) { @@ -174,7 +163,6 @@ MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,mov_l_rm,(W4 d, IMM s)) { @@ -183,7 +171,6 @@ MIDFUNC(2,mov_l_rm,(W4 d, IMM s)) raw_mov_l_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_l_rm,(W4 d, IMM s)) MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) { @@ -194,28 +181,24 @@ MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) unlock2(index); unlock2(d); } -MENDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) MIDFUNC(2,mov_l_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_l_mi(d,s); } -MENDFUNC(2,mov_l_mi,(IMM d, IMM s)) MIDFUNC(2,mov_w_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_w_mi(d,s); } -MENDFUNC(2,mov_w_mi,(IMM d, IMM s)) MIDFUNC(2,mov_b_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_b_mi(d,s); } -MENDFUNC(2,mov_b_mi,(IMM d, IMM s)) MIDFUNC(2,rol_b_ri,(RW1 r, IMM i)) { @@ -226,7 +209,6 @@ MIDFUNC(2,rol_b_ri,(RW1 r, IMM i)) raw_rol_b_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_b_ri,(RW1 r, IMM i)) MIDFUNC(2,rol_w_ri,(RW2 r, IMM i)) { @@ -237,7 +219,6 @@ MIDFUNC(2,rol_w_ri,(RW2 r, IMM i)) raw_rol_w_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_w_ri,(RW2 r, IMM i)) MIDFUNC(2,rol_l_ri,(RW4 r, IMM i)) { @@ -248,7 +229,6 @@ MIDFUNC(2,rol_l_ri,(RW4 r, IMM i)) raw_rol_l_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_l_ri,(RW4 r, IMM i)) MIDFUNC(2,rol_l_rr,(RW4 d, RR1 r)) { @@ -263,7 +243,6 @@ MIDFUNC(2,rol_l_rr,(RW4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,rol_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,rol_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -279,7 +258,6 @@ MIDFUNC(2,rol_w_rr,(RW2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,rol_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -295,7 +273,6 @@ MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,shll_l_rr,(RW4 d, RR1 r)) { @@ -310,7 +287,6 @@ MIDFUNC(2,shll_l_rr,(RW4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shll_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shll_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -326,7 +302,6 @@ MIDFUNC(2,shll_w_rr,(RW2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shll_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -342,7 +317,6 @@ MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,ror_b_ri,(RR1 r, IMM i)) { @@ -353,7 +327,6 @@ MIDFUNC(2,ror_b_ri,(RR1 r, IMM i)) raw_ror_b_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_b_ri,(RR1 r, IMM i)) MIDFUNC(2,ror_w_ri,(RR2 r, IMM i)) { @@ -364,7 +337,6 @@ MIDFUNC(2,ror_w_ri,(RR2 r, IMM i)) raw_ror_w_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_w_ri,(RR2 r, IMM i)) MIDFUNC(2,ror_l_ri,(RR4 r, IMM i)) { @@ -375,7 +347,6 @@ MIDFUNC(2,ror_l_ri,(RR4 r, IMM i)) raw_ror_l_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_l_ri,(RR4 r, IMM i)) MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) { @@ -390,7 +361,6 @@ MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) { @@ -405,7 +375,6 @@ MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) { @@ -421,7 +390,6 @@ MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) MIDFUNC(2,shrl_l_rr,(RW4 d, RR1 r)) { @@ -436,7 +404,6 @@ MIDFUNC(2,shrl_l_rr,(RW4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shrl_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -452,7 +419,6 @@ MIDFUNC(2,shrl_w_rr,(RW2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -469,7 +435,6 @@ MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,shll_l_ri,(RW4 r, IMM i)) { @@ -484,7 +449,6 @@ MIDFUNC(2,shll_l_ri,(RW4 r, IMM i)) raw_shll_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shll_w_ri,(RW2 r, IMM i)) { @@ -495,7 +459,6 @@ MIDFUNC(2,shll_w_ri,(RW2 r, IMM i)) raw_shll_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shll_b_ri,(RW1 r, IMM i)) { @@ -506,7 +469,6 @@ MIDFUNC(2,shll_b_ri,(RW1 r, IMM i)) raw_shll_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) { @@ -521,7 +483,6 @@ MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) raw_shrl_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) { @@ -532,7 +493,6 @@ MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) raw_shrl_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) { @@ -543,7 +503,6 @@ MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) raw_shrl_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shra_l_ri,(RW4 r, IMM i)) { @@ -554,7 +513,6 @@ MIDFUNC(2,shra_l_ri,(RW4 r, IMM i)) raw_shra_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shra_w_ri,(RW2 r, IMM i)) { @@ -565,7 +523,6 @@ MIDFUNC(2,shra_w_ri,(RW2 r, IMM i)) raw_shra_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shra_b_ri,(RW1 r, IMM i)) { @@ -576,7 +533,6 @@ MIDFUNC(2,shra_b_ri,(RW1 r, IMM i)) raw_shra_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shra_l_rr,(RW4 d, RR1 r)) { @@ -591,7 +547,6 @@ MIDFUNC(2,shra_l_rr,(RW4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shra_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shra_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -607,7 +562,6 @@ MIDFUNC(2,shra_w_rr,(RW2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shra_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ @@ -624,7 +578,6 @@ MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,setcc,(W1 d, IMM cc)) { @@ -633,14 +586,12 @@ MIDFUNC(2,setcc,(W1 d, IMM cc)) raw_setcc(d,cc); unlock2(d); } -MENDFUNC(2,setcc,(W1 d, IMM cc)) MIDFUNC(2,setcc_m,(IMM d, IMM cc)) { CLOBBER_SETCC; raw_setcc_m(d,cc); } -MENDFUNC(2,setcc_m,(IMM d, IMM cc)) MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) { @@ -653,7 +604,6 @@ MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) unlock2(s); unlock2(d); } -MENDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) MIDFUNC(2,bsf_l_rr,(W4 d, W4 s)) { @@ -664,7 +614,6 @@ MIDFUNC(2,bsf_l_rr,(W4 d, W4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,bsf_l_rr,(W4 d, W4 s)) /* Set the Z flag depending on the value in s. Note that the value has to be 0 or -1 (or, more precisely, for non-zero @@ -678,7 +627,6 @@ MIDFUNC(2,simulate_bsf,(W4 tmp, RW4 s)) unlock2(tmp); unlock2(s); } -MENDFUNC(2,simulate_bsf,(W4 tmp, RW4 s)) MIDFUNC(2,imul_32_32,(RW4 d, RR4 s)) { @@ -689,7 +637,6 @@ MIDFUNC(2,imul_32_32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,imul_32_32,(RW4 d, RR4 s)) MIDFUNC(2,imul_64_32,(RW4 d, RW4 s)) { @@ -700,7 +647,6 @@ MIDFUNC(2,imul_64_32,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,imul_64_32,(RW4 d, RW4 s)) MIDFUNC(2,mul_64_32,(RW4 d, RW4 s)) { @@ -711,7 +657,6 @@ MIDFUNC(2,mul_64_32,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,mul_64_32,(RW4 d, RW4 s)) MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) { @@ -741,7 +686,6 @@ MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) unlock2(s); } } -MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) { @@ -773,7 +717,6 @@ MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) unlock2(s); } } -MENDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) { @@ -803,7 +746,6 @@ MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) unlock2(s); } } -MENDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) { @@ -834,7 +776,6 @@ MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) unlock2(s); } } -MENDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) MIDFUNC(2,mov_b_rr,(W1 d, RR1 s)) { @@ -852,7 +793,6 @@ MIDFUNC(2,mov_b_rr,(W1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,mov_b_rr,(W1 d, RR1 s)) MIDFUNC(2,mov_w_rr,(W2 d, RR2 s)) { @@ -870,7 +810,6 @@ MIDFUNC(2,mov_w_rr,(W2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,mov_w_rr,(W2 d, RR2 s)) /* read the long at the address contained in s+offset and store in d */ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) @@ -887,7 +826,6 @@ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) @@ -904,7 +842,6 @@ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) /* read the long at the address contained in s+offset and store in d */ MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) @@ -923,7 +860,6 @@ MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) @@ -943,7 +879,6 @@ MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) @@ -963,7 +898,6 @@ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) { @@ -979,7 +913,6 @@ MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) raw_mov_l_Ri(d,i,offset); unlock2(d); } -MENDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) { @@ -995,7 +928,6 @@ MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) raw_mov_w_Ri(d,i,offset); unlock2(d); } -MENDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) /* Warning! OFFSET is byte sized only! */ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) @@ -1017,7 +949,6 @@ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) { @@ -1037,7 +968,6 @@ MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) { @@ -1058,7 +988,6 @@ MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) { @@ -1076,7 +1005,6 @@ MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) unlock2(index); unlock2(s); } -MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) { @@ -1090,7 +1018,6 @@ MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) unlock2(index); unlock2(s); } -MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) /* write d to the long at the address contained in s+offset */ MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) @@ -1110,7 +1037,6 @@ MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) /* write the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) @@ -1130,7 +1056,6 @@ MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) { @@ -1148,7 +1073,6 @@ MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) MIDFUNC(1,mid_bswap_32,(RW4 r)) { @@ -1164,7 +1088,6 @@ MIDFUNC(1,mid_bswap_32,(RW4 r)) raw_bswap_32(r); unlock2(r); } -MENDFUNC(1,mid_bswap_32,(RW4 r)) MIDFUNC(1,mid_bswap_16,(RW2 r)) { @@ -1181,7 +1104,6 @@ MIDFUNC(1,mid_bswap_16,(RW2 r)) raw_bswap_16(r); unlock2(r); } -MENDFUNC(1,mid_bswap_16,(RW2 r)) MIDFUNC(2,mov_l_rr,(W4 d, RR4 s)) { @@ -1210,7 +1132,6 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s)) D2(panicbug("Added %d to nreg %d(%d), now holds %d regs", d,s,live.state[d].realind,live.nat[s].nholds)); unlock2(s); } -MENDFUNC(2,mov_l_rr,(W4 d, RR4 s)) MIDFUNC(2,mov_l_mr,(IMM d, RR4 s)) { @@ -1224,7 +1145,6 @@ MIDFUNC(2,mov_l_mr,(IMM d, RR4 s)) raw_mov_l_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_l_mr,(IMM d, RR4 s)) MIDFUNC(2,mov_w_mr,(IMM d, RR2 s)) { @@ -1238,7 +1158,6 @@ MIDFUNC(2,mov_w_mr,(IMM d, RR2 s)) raw_mov_w_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_w_mr,(IMM d, RR2 s)) MIDFUNC(2,mov_w_rm,(W2 d, IMM s)) { @@ -1248,7 +1167,6 @@ MIDFUNC(2,mov_w_rm,(W2 d, IMM s)) raw_mov_w_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_w_rm,(W2 d, IMM s)) MIDFUNC(2,mov_b_mr,(IMM d, RR1 s)) { @@ -1263,7 +1181,6 @@ MIDFUNC(2,mov_b_mr,(IMM d, RR1 s)) raw_mov_b_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_b_mr,(IMM d, RR1 s)) MIDFUNC(2,mov_b_rm,(W1 d, IMM s)) { @@ -1273,14 +1190,12 @@ MIDFUNC(2,mov_b_rm,(W1 d, IMM s)) raw_mov_b_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_b_rm,(W1 d, IMM s)) MIDFUNC(2,mov_l_ri,(W4 d, IMM s)) { set_const(d,s); return; } -MENDFUNC(2,mov_l_ri,(W4 d, IMM s)) MIDFUNC(2,mov_w_ri,(W2 d, IMM s)) { @@ -1290,7 +1205,6 @@ MIDFUNC(2,mov_w_ri,(W2 d, IMM s)) raw_mov_w_ri(d,s); unlock2(d); } -MENDFUNC(2,mov_w_ri,(W2 d, IMM s)) MIDFUNC(2,mov_b_ri,(W1 d, IMM s)) { @@ -1300,7 +1214,6 @@ MIDFUNC(2,mov_b_ri,(W1 d, IMM s)) raw_mov_b_ri(d,s); unlock2(d); } -MENDFUNC(2,mov_b_ri,(W1 d, IMM s)) MIDFUNC(2,test_l_ri,(RR4 d, IMM i)) { @@ -1310,7 +1223,6 @@ MIDFUNC(2,test_l_ri,(RR4 d, IMM i)) raw_test_l_ri(d,i); unlock2(d); } -MENDFUNC(2,test_l_ri,(RR4 d, IMM i)) MIDFUNC(2,test_l_rr,(RR4 d, RR4 s)) { @@ -1322,7 +1234,6 @@ MIDFUNC(2,test_l_rr,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_l_rr,(RR4 d, RR4 s)) MIDFUNC(2,test_w_rr,(RR2 d, RR2 s)) { @@ -1334,7 +1245,6 @@ MIDFUNC(2,test_w_rr,(RR2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_w_rr,(RR2 d, RR2 s)) MIDFUNC(2,test_b_rr,(RR1 d, RR1 s)) { @@ -1346,7 +1256,6 @@ MIDFUNC(2,test_b_rr,(RR1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_b_rr,(RR1 d, RR1 s)) MIDFUNC(2,and_l_ri,(RW4 d, IMM i)) { @@ -1361,7 +1270,6 @@ MIDFUNC(2,and_l_ri,(RW4 d, IMM i)) raw_and_l_ri(d,i); unlock2(d); } -MENDFUNC(2,and_l_ri,(RW4 d, IMM i)) MIDFUNC(2,and_l,(RW4 d, RR4 s)) { @@ -1373,7 +1281,6 @@ MIDFUNC(2,and_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_l,(RW4 d, RR4 s)) MIDFUNC(2,and_w,(RW2 d, RR2 s)) { @@ -1385,7 +1292,6 @@ MIDFUNC(2,and_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_w,(RW2 d, RR2 s)) MIDFUNC(2,and_b,(RW1 d, RR1 s)) { @@ -1397,7 +1303,6 @@ MIDFUNC(2,and_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_b,(RW1 d, RR1 s)) MIDFUNC(2,or_l_ri,(RW4 d, IMM i)) { @@ -1411,7 +1316,6 @@ MIDFUNC(2,or_l_ri,(RW4 d, IMM i)) raw_or_l_ri(d,i); unlock2(d); } -MENDFUNC(2,or_l_ri,(RW4 d, IMM i)) MIDFUNC(2,or_l,(RW4 d, RR4 s)) { @@ -1427,7 +1331,6 @@ MIDFUNC(2,or_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_l,(RW4 d, RR4 s)) MIDFUNC(2,or_w,(RW2 d, RR2 s)) { @@ -1439,7 +1342,6 @@ MIDFUNC(2,or_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_w,(RW2 d, RR2 s)) MIDFUNC(2,or_b,(RW1 d, RR1 s)) { @@ -1451,7 +1353,6 @@ MIDFUNC(2,or_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_b,(RW1 d, RR1 s)) MIDFUNC(2,adc_l,(RW4 d, RR4 s)) { @@ -1464,7 +1365,6 @@ MIDFUNC(2,adc_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_l,(RW4 d, RR4 s)) MIDFUNC(2,adc_w,(RW2 d, RR2 s)) { @@ -1476,7 +1376,6 @@ MIDFUNC(2,adc_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_w,(RW2 d, RR2 s)) MIDFUNC(2,adc_b,(RW1 d, RR1 s)) { @@ -1488,7 +1387,6 @@ MIDFUNC(2,adc_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_b,(RW1 d, RR1 s)) MIDFUNC(2,add_l,(RW4 d, RR4 s)) { @@ -1506,7 +1404,6 @@ MIDFUNC(2,add_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_l,(RW4 d, RR4 s)) MIDFUNC(2,add_w,(RW2 d, RR2 s)) { @@ -1523,7 +1420,6 @@ MIDFUNC(2,add_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_w,(RW2 d, RR2 s)) MIDFUNC(2,add_b,(RW1 d, RR1 s)) { @@ -1540,7 +1436,6 @@ MIDFUNC(2,add_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_b,(RW1 d, RR1 s)) MIDFUNC(2,sub_l_ri,(RW4 d, IMM i)) { @@ -1563,7 +1458,6 @@ MIDFUNC(2,sub_l_ri,(RW4 d, IMM i)) raw_sub_l_ri(d,i); unlock2(d); } -MENDFUNC(2,sub_l_ri,(RW4 d, IMM i)) MIDFUNC(2,sub_w_ri,(RW2 d, IMM i)) { @@ -1576,7 +1470,6 @@ MIDFUNC(2,sub_w_ri,(RW2 d, IMM i)) raw_sub_w_ri(d,i); unlock2(d); } -MENDFUNC(2,sub_w_ri,(RW2 d, IMM i)) MIDFUNC(2,sub_b_ri,(RW1 d, IMM i)) { @@ -1590,7 +1483,6 @@ MIDFUNC(2,sub_b_ri,(RW1 d, IMM i)) unlock2(d); } -MENDFUNC(2,sub_b_ri,(RW1 d, IMM i)) MIDFUNC(2,add_l_ri,(RW4 d, IMM i)) { @@ -1611,7 +1503,6 @@ MIDFUNC(2,add_l_ri,(RW4 d, IMM i)) raw_add_l_ri(d,i); unlock2(d); } -MENDFUNC(2,add_l_ri,(RW4 d, IMM i)) MIDFUNC(2,add_w_ri,(RW2 d, IMM i)) { @@ -1624,7 +1515,6 @@ MIDFUNC(2,add_w_ri,(RW2 d, IMM i)) raw_add_w_ri(d,i); unlock2(d); } -MENDFUNC(2,add_w_ri,(RW2 d, IMM i)) MIDFUNC(2,add_b_ri,(RW1 d, IMM i)) { @@ -1638,7 +1528,6 @@ MIDFUNC(2,add_b_ri,(RW1 d, IMM i)) unlock2(d); } -MENDFUNC(2,add_b_ri,(RW1 d, IMM i)) MIDFUNC(2,sbb_l,(RW4 d, RR4 s)) { @@ -1650,7 +1539,6 @@ MIDFUNC(2,sbb_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_l,(RW4 d, RR4 s)) MIDFUNC(2,sbb_w,(RW2 d, RR2 s)) { @@ -1662,7 +1550,6 @@ MIDFUNC(2,sbb_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_w,(RW2 d, RR2 s)) MIDFUNC(2,sbb_b,(RW1 d, RR1 s)) { @@ -1674,7 +1561,6 @@ MIDFUNC(2,sbb_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_b,(RW1 d, RR1 s)) MIDFUNC(2,sub_l,(RW4 d, RR4 s)) { @@ -1691,7 +1577,6 @@ MIDFUNC(2,sub_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_l,(RW4 d, RR4 s)) MIDFUNC(2,sub_w,(RW2 d, RR2 s)) { @@ -1708,7 +1593,6 @@ MIDFUNC(2,sub_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_w,(RW2 d, RR2 s)) MIDFUNC(2,sub_b,(RW1 d, RR1 s)) { @@ -1725,7 +1609,6 @@ MIDFUNC(2,sub_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_b,(RW1 d, RR1 s)) MIDFUNC(2,cmp_l,(RR4 d, RR4 s)) { @@ -1737,7 +1620,6 @@ MIDFUNC(2,cmp_l,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_l,(RR4 d, RR4 s)) MIDFUNC(2,cmp_w,(RR2 d, RR2 s)) { @@ -1749,7 +1631,6 @@ MIDFUNC(2,cmp_w,(RR2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_w,(RR2 d, RR2 s)) MIDFUNC(2,cmp_b,(RR1 d, RR1 s)) { @@ -1761,7 +1642,6 @@ MIDFUNC(2,cmp_b,(RR1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_b,(RR1 d, RR1 s)) MIDFUNC(2,xor_l,(RW4 d, RR4 s)) { @@ -1773,7 +1653,6 @@ MIDFUNC(2,xor_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_l,(RW4 d, RR4 s)) MIDFUNC(2,xor_w,(RW2 d, RR2 s)) { @@ -1785,7 +1664,6 @@ MIDFUNC(2,xor_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_w,(RW2 d, RR2 s)) MIDFUNC(2,xor_b,(RW1 d, RR1 s)) { @@ -1797,7 +1675,6 @@ MIDFUNC(2,xor_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_b,(RW1 d, RR1 s)) MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) { @@ -1812,7 +1689,6 @@ MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) prepare_for_call_2(); compemu_raw_call_r(r); } -MENDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) { @@ -1849,13 +1725,11 @@ MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) live.state[out1].dirtysize=osize; set_status(out1,DIRTY); } -MENDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) MIDFUNC(0,nop,(void)) { raw_emit_nop(); } -MENDFUNC(0,nop,(void)) /* forget_about() takes a mid-layer register */ MIDFUNC(1,forget_about,(W4 r)) @@ -1865,7 +1739,6 @@ MIDFUNC(1,forget_about,(W4 r)) live.state[r].val=0; set_status(r,UNDEF); } -MENDFUNC(1,forget_about,(W4 r)) MIDFUNC(1,f_forget_about,(FW r)) { @@ -1873,7 +1746,6 @@ MIDFUNC(1,f_forget_about,(FW r)) f_disassociate(r); live.fate[r].status=UNDEF; } -MENDFUNC(1,f_forget_about,(FW r)) // ARM optimized functions @@ -1892,7 +1764,6 @@ MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s)) MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i)) { @@ -1911,7 +1782,6 @@ MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i)) raw_ADD_l_rr(d,REG_WORK1); unlock2(d); } -MENDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i)) MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i)) { @@ -1929,7 +1799,6 @@ MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i)) raw_ADD_l_rri(d,d,i); unlock2(d); } -MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i)) MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i)) { @@ -1947,7 +1816,6 @@ MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i)) raw_SUB_l_rri(d,d,i); unlock2(d); } -MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i)) MIDFUNC(2,arm_AND_l,(RW4 d, RR4 s)) { @@ -1958,7 +1826,6 @@ MIDFUNC(2,arm_AND_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_AND_l,(RW4 d, RR4 s)) MIDFUNC(2,arm_AND_w,(RW2 d, RR2 s)) { @@ -1969,7 +1836,6 @@ MIDFUNC(2,arm_AND_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_AND_w,(RW2 d, RR2 s)) MIDFUNC(2,arm_AND_b,(RW1 d, RR1 s)) { @@ -1980,7 +1846,6 @@ MIDFUNC(2,arm_AND_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_AND_b,(RW1 d, RR1 s)) MIDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i)) { @@ -1994,7 +1859,6 @@ MIDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i)) raw_AND_l_ri(d,i); unlock2(d); } -MENDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i)) MIDFUNC(2,arm_EOR_b,(RW1 d, RR1 s)) { @@ -2005,7 +1869,6 @@ MIDFUNC(2,arm_EOR_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_EOR_b,(RW1 d, RR1 s)) MIDFUNC(2,arm_EOR_l,(RW4 d, RR4 s)) { @@ -2016,7 +1879,6 @@ MIDFUNC(2,arm_EOR_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_EOR_l,(RW4 d, RR4 s)) MIDFUNC(2,arm_EOR_w,(RW2 d, RR2 s)) { @@ -2027,7 +1889,6 @@ MIDFUNC(2,arm_EOR_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_EOR_w,(RW2 d, RR2 s)) MIDFUNC(2,arm_ORR_b,(RW1 d, RR1 s)) { @@ -2038,7 +1899,6 @@ MIDFUNC(2,arm_ORR_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_ORR_b,(RW1 d, RR1 s)) MIDFUNC(2,arm_ORR_l,(RW4 d, RR4 s)) { @@ -2053,7 +1913,6 @@ MIDFUNC(2,arm_ORR_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_ORR_l,(RW4 d, RR4 s)) MIDFUNC(2,arm_ORR_w,(RW2 d, RR2 s)) { @@ -2064,7 +1923,6 @@ MIDFUNC(2,arm_ORR_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,arm_ORR_w,(RW2 d, RR2 s)) MIDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i)) { @@ -2075,7 +1933,6 @@ MIDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i)) raw_ROR_l_ri(r,i); unlock2(r); } -MENDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i)) // Other static inline void flush_cpu_icache(void *start, void *stop) diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h index 52541326..baedb153 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h +++ b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h @@ -64,6 +64,7 @@ DECLARE_MIDFUNC(rol_w_ri(RW2 r, IMM i)); DECLARE_MIDFUNC(rol_l_rr(RW4 d, RR1 r)); DECLARE_MIDFUNC(rol_w_rr(RW2 d, RR1 r)); DECLARE_MIDFUNC(rol_b_rr(RW1 d, RR1 r)); +DECLARE_MIDFUNC(rol_l_ri(RW4 r, IMM i)); DECLARE_MIDFUNC(shll_l_rr(RW4 d, RR1 r)); DECLARE_MIDFUNC(shll_w_rr(RW2 d, RR1 r)); DECLARE_MIDFUNC(shll_b_rr(RW1 d, RR1 r)); @@ -98,6 +99,7 @@ DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s)); DECLARE_MIDFUNC(sign_extend_8_rr(W4 d, RR1 s)); DECLARE_MIDFUNC(zero_extend_16_rr(W4 d, RR2 s)); DECLARE_MIDFUNC(zero_extend_8_rr(W4 d, RR1 s)); +DECLARE_MIDFUNC(simulate_bsf(W4 tmp, RW4 s)); DECLARE_MIDFUNC(imul_64_32(RW4 d, RW4 s)); DECLARE_MIDFUNC(mul_64_32(RW4 d, RW4 s)); DECLARE_MIDFUNC(imul_32_32(RW4 d, RR4 s)); diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.cpp b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.cpp index 9da2c058..5f55d1bf 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.cpp +++ b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm2.cpp @@ -129,7 +129,6 @@ MIDFUNC(0,restore_inverted_carry,(void)) MSR_CPSRf_r(REG_WORK1); unlock2(r); } -MENDFUNC(0,restore_inverted_carry,(void)) /* * ADD @@ -161,7 +160,6 @@ MIDFUNC(3,jnf_ADD_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ADD_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jnf_ADD,(W4 d, RR4 s, RR4 v)) { @@ -180,7 +178,6 @@ MIDFUNC(3,jnf_ADD,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_ADD,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_ADD_b_imm,(W4 d, RR1 s, IMM v)) { @@ -194,7 +191,6 @@ MIDFUNC(3,jff_ADD_b_imm,(W4 d, RR1 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ADD_b_imm,(W4 d, RR1 s, IMM v)) MIDFUNC(3,jff_ADD_b,(W4 d, RR1 s, RR1 v)) { @@ -215,7 +211,6 @@ MIDFUNC(3,jff_ADD_b,(W4 d, RR1 s, RR1 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADD_b,(W4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_ADD_w_imm,(W4 d, RR2 s, IMM v)) { @@ -229,7 +224,6 @@ MIDFUNC(3,jff_ADD_w_imm,(W4 d, RR2 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ADD_w_imm,(W4 d, RR2 s, IMM v)) MIDFUNC(3,jff_ADD_w,(W4 d, RR2 s, RR2 v)) { @@ -249,7 +243,6 @@ MIDFUNC(3,jff_ADD_w,(W4 d, RR2 s, RR2 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADD_w,(W4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_ADD_l_imm,(W4 d, RR4 s, IMM v)) { @@ -262,7 +255,6 @@ MIDFUNC(3,jff_ADD_l_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ADD_l_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jff_ADD_l,(W4 d, RR4 s, RR4 v)) { @@ -281,7 +273,6 @@ MIDFUNC(3,jff_ADD_l,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADD_l,(W4 d, RR4 s, RR4 v)) /* * ADDA @@ -303,7 +294,6 @@ MIDFUNC(2,jnf_ADDA_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ADDA_b,(W4 d, RR1 s)) MIDFUNC(2,jnf_ADDA_w,(W4 d, RR2 s)) { @@ -316,7 +306,6 @@ MIDFUNC(2,jnf_ADDA_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ADDA_w,(W4 d, RR2 s)) MIDFUNC(2,jnf_ADDA_l,(W4 d, RR4 s)) { @@ -328,7 +317,6 @@ MIDFUNC(2,jnf_ADDA_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ADDA_l,(W4 d, RR4 s)) /* * ADDX @@ -358,7 +346,6 @@ MIDFUNC(3,jnf_ADDX,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_ADDX,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_ADDX_b,(W4 d, RR1 s, RR1 v)) { @@ -383,7 +370,6 @@ MIDFUNC(3,jff_ADDX_b,(W4 d, RR1 s, RR1 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADDX_b,(W4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_ADDX_w,(W4 d, RR2 s, RR2 v)) { @@ -408,7 +394,6 @@ MIDFUNC(3,jff_ADDX_w,(W4 d, RR2 s, RR2 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADDX_w,(W4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_ADDX_l,(W4 d, RR4 s, RR4 v)) { @@ -431,7 +416,6 @@ MIDFUNC(3,jff_ADDX_l,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_ADDX_l,(W4 d, RR4 s, RR4 v)) /* * ANDI @@ -458,7 +442,6 @@ MIDFUNC(1,jff_ANDSR,(IMM s, IMM x)) STRB_rR(REG_WORK2, REG_WORK1); } } -MENDFUNC(1,jff_ANDSR,(IMM s)) /* * AND @@ -493,7 +476,6 @@ MIDFUNC(3,jnf_AND,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_AND,(RW4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_AND_b,(W4 d, RR1 s, RR1 v)) { @@ -510,7 +492,6 @@ MIDFUNC(3,jff_AND_b,(W4 d, RR1 s, RR1 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_AND_b,(RW4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_AND_w,(W4 d, RR2 s, RR2 v)) { @@ -527,7 +508,6 @@ MIDFUNC(3,jff_AND_w,(W4 d, RR2 s, RR2 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_AND_w,(RW4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_AND_l,(W4 d, RR4 s, RR4 v)) { @@ -542,7 +522,6 @@ MIDFUNC(3,jff_AND_l,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_AND_l,(RW4 d, RR4 s, RR4 v)) /* * ASL @@ -592,7 +571,6 @@ MIDFUNC(3,jff_ASL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -627,7 +605,6 @@ MIDFUNC(3,jff_ASL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -660,7 +637,6 @@ MIDFUNC(3,jff_ASL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASL_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -695,7 +671,6 @@ MIDFUNC(3,jff_ASL_b_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASL_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ASL_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -730,7 +705,6 @@ MIDFUNC(3,jff_ASL_w_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASL_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ASL_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -763,7 +737,6 @@ MIDFUNC(3,jff_ASL_l_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASL_l_reg,(W4 d, RR4 s, RR4 i)) /* * ASLW @@ -788,7 +761,6 @@ MIDFUNC(2,jnf_ASLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ASLW,(W4 d, RR4 s)) MIDFUNC(2,jff_ASLW,(W4 d, RR4 s)) { @@ -806,7 +778,6 @@ MIDFUNC(2,jff_ASLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_ASLW,(W4 d, RR4 s)) /* * ASR @@ -836,7 +807,6 @@ MIDFUNC(3,jnf_ASR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ASR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ASR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -851,7 +821,6 @@ MIDFUNC(3,jnf_ASR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ASR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ASR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -865,7 +834,6 @@ MIDFUNC(3,jnf_ASR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ASR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASR_b_imm,(W4 d, RR4 s, IMM i)) { @@ -885,7 +853,6 @@ MIDFUNC(3,jff_ASR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -905,7 +872,6 @@ MIDFUNC(3,jff_ASR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ASR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -924,7 +890,6 @@ MIDFUNC(3,jff_ASR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ASR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ASR_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -940,7 +905,6 @@ MIDFUNC(3,jnf_ASR_b_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ASR_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ASR_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -956,7 +920,6 @@ MIDFUNC(3,jnf_ASR_w_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ASR_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ASR_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -971,7 +934,6 @@ MIDFUNC(3,jnf_ASR_l_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ASR_l_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ASR_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -989,7 +951,6 @@ MIDFUNC(3,jff_ASR_b_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASR_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ASR_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -1007,7 +968,6 @@ MIDFUNC(3,jff_ASR_w_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASR_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ASR_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -1024,7 +984,6 @@ MIDFUNC(3,jff_ASR_l_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ASR_l_reg,(W4 d, RR4 s, RR4 i)) /* * ASRW @@ -1050,7 +1009,6 @@ MIDFUNC(2,jnf_ASRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ASRW,(W4 d, RR4 s)) MIDFUNC(2,jff_ASRW,(W4 d, RR4 s)) { @@ -1064,7 +1022,6 @@ MIDFUNC(2,jff_ASRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_ASRW,(W4 d, RR4 s)) /* * BCHG @@ -1086,7 +1043,6 @@ MIDFUNC(2,jnf_BCHG_b_imm,(RW4 d, IMM s)) EOR_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BCHG_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IMM s)) { @@ -1094,7 +1050,6 @@ MIDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IMM s)) EOR_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BCHG_b,(RW4 d, RR4 s)) { @@ -1114,7 +1069,6 @@ MIDFUNC(2,jnf_BCHG_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BCHG_b,(RW4 d, RR4 s)) MIDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s)) { @@ -1135,7 +1089,6 @@ MIDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s)) MIDFUNC(2,jff_BCHG_b_imm,(RW4 d, IMM s)) { @@ -1151,7 +1104,6 @@ MIDFUNC(2,jff_BCHG_b_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BCHG_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IMM s)) { @@ -1167,7 +1119,6 @@ MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BCHG_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BCHG_b,(RW4 d, RR4 s)) { @@ -1192,7 +1143,6 @@ MIDFUNC(2,jff_BCHG_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BCHG_b,(RW4 d, RR4 s)) MIDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s)) { @@ -1218,7 +1168,6 @@ MIDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s)) /* * BCLR @@ -1240,7 +1189,6 @@ MIDFUNC(2,jnf_BCLR_b_imm,(RW4 d, IMM s)) BIC_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BCLR_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IMM s)) { @@ -1248,7 +1196,6 @@ MIDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IMM s)) BIC_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BCLR_b,(RW4 d, RR4 s)) { @@ -1268,7 +1215,6 @@ MIDFUNC(2,jnf_BCLR_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BCLR_b,(RW4 d, RR4 s)) MIDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s)) { @@ -1289,7 +1235,6 @@ MIDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s)) MIDFUNC(2,jff_BCLR_b_imm,(RW4 d, IMM s)) { @@ -1305,7 +1250,6 @@ MIDFUNC(2,jff_BCLR_b_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BCLR_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BCLR_l_imm,(RW4 d, IMM s)) { @@ -1321,7 +1265,6 @@ MIDFUNC(2,jff_BCLR_l_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BCLR_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BCLR_b,(RW4 d, RR4 s)) { @@ -1346,7 +1289,6 @@ MIDFUNC(2,jff_BCLR_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BCLR_b,(RW4 d, RR4 s)) MIDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s)) { @@ -1372,7 +1314,6 @@ MIDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s)) /* * BSET @@ -1394,7 +1335,6 @@ MIDFUNC(2,jnf_BSET_b_imm,(RW4 d, IMM s)) ORR_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BSET_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BSET_l_imm,(RW4 d, IMM s)) { @@ -1402,7 +1342,6 @@ MIDFUNC(2,jnf_BSET_l_imm,(RW4 d, IMM s)) ORR_rri(d,d,(1 << s)); unlock2(d); } -MENDFUNC(2,jnf_BSET_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jnf_BSET_b,(RW4 d, RR4 s)) { @@ -1422,7 +1361,6 @@ MIDFUNC(2,jnf_BSET_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BSET_b,(RW4 d, RR4 s)) MIDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s)) { @@ -1443,7 +1381,6 @@ MIDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s)) MIDFUNC(2,jff_BSET_b_imm,(RW4 d, IMM s)) { @@ -1459,7 +1396,6 @@ MIDFUNC(2,jff_BSET_b_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BSET_b_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BSET_l_imm,(RW4 d, IMM s)) { @@ -1475,7 +1411,6 @@ MIDFUNC(2,jff_BSET_l_imm,(RW4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BSET_l_imm,(RW4 d, IMM s)) MIDFUNC(2,jff_BSET_b,(RW4 d, RR4 s)) { @@ -1500,7 +1435,6 @@ MIDFUNC(2,jff_BSET_b,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BSET_b,(RW4 d, RR4 s)) MIDFUNC(2,jff_BSET_l,(RW4 d, RR4 s)) { @@ -1526,7 +1460,6 @@ MIDFUNC(2,jff_BSET_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BSET_l,(RW4 d, RR4 s)) /* * BTST @@ -1554,7 +1487,6 @@ MIDFUNC(2,jff_BTST_b_imm,(RR4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BTST_b_imm,(RR4 d, IMM s)) MIDFUNC(2,jff_BTST_l_imm,(RR4 d, IMM s)) { @@ -1568,7 +1500,6 @@ MIDFUNC(2,jff_BTST_l_imm,(RR4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_BTST_l_imm,(RR4 d, IMM s)) MIDFUNC(2,jff_BTST_b,(RR4 d, RR4 s)) { @@ -1592,7 +1523,6 @@ MIDFUNC(2,jff_BTST_b,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BTST_b,(RR4 d, RR4 s)) MIDFUNC(2,jff_BTST_l,(RR4 d, RR4 s)) { @@ -1617,7 +1547,6 @@ MIDFUNC(2,jff_BTST_l,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_BTST_l,(RR4 d, RR4 s)) /* * CLR @@ -1638,7 +1567,6 @@ MIDFUNC(1,jnf_CLR,(W4 d)) MOV_ri(d,0); unlock2(d); } -MENDFUNC(1,jnf_CLR,(W4 d)) MIDFUNC(1,jff_CLR,(W4 d)) { @@ -1647,7 +1575,6 @@ MIDFUNC(1,jff_CLR,(W4 d)) MSR_CPSR_i(ARM_Z_FLAG); unlock2(d); } -MENDFUNC(1,jff_CLR,(W4 d)) /* * CMP @@ -1679,7 +1606,6 @@ MIDFUNC(2,jff_CMP_b,(RR1 d, RR1 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMP_b,(RR1 d, RR1 s)) MIDFUNC(2,jff_CMP_w,(RR2 d, RR2 s)) { @@ -1698,7 +1624,6 @@ MIDFUNC(2,jff_CMP_w,(RR2 d, RR2 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMP_w,(RR2 d, RR2 s)) MIDFUNC(2,jff_CMP_l,(RR4 d, RR4 s)) { @@ -1715,7 +1640,6 @@ MIDFUNC(2,jff_CMP_l,(RR4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMP_l,(RR4 d, RR4 s)) /* * CMPA @@ -1746,7 +1670,6 @@ MIDFUNC(2,jff_CMPA_b,(RR1 d, RR1 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMPA_b,(RR1 d, RR1 s)) MIDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s)) { @@ -1764,7 +1687,6 @@ MIDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s)) MIDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s)) { @@ -1781,7 +1703,6 @@ MIDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s)) /* * EOR @@ -1815,7 +1736,6 @@ MIDFUNC(3,jnf_EOR,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_EOR,(RW4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_EOR_b,(W4 d, RR1 s, RR1 v)) { @@ -1832,7 +1752,6 @@ MIDFUNC(3,jff_EOR_b,(W4 d, RR1 s, RR1 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_EOR_b,(RW4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_EOR_w,(W4 d, RR2 s, RR2 v)) { @@ -1849,7 +1768,6 @@ MIDFUNC(3,jff_EOR_w,(W4 d, RR2 s, RR2 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_EOR_w,(RW4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_EOR_l,(W4 d, RR4 s, RR4 v)) { @@ -1864,7 +1782,6 @@ MIDFUNC(3,jff_EOR_l,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_EOR_l,(RW4 d, RR4 s, RR4 v)) /* * EORI @@ -1892,7 +1809,6 @@ MIDFUNC(1,jff_EORSR,(IMM s, IMM x)) STRB_rR(REG_WORK2, REG_WORK1); } } -MENDFUNC(1,jff_EORSR,(IMM s)) /* * EXT @@ -1922,7 +1838,6 @@ MIDFUNC(2,jnf_EXT_b,(W4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_EXT_b,(W4 d, RR4 s)) MIDFUNC(2,jnf_EXT_w,(W4 d, RR4 s)) { @@ -1939,7 +1854,6 @@ MIDFUNC(2,jnf_EXT_w,(W4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_EXT_w,(W4 d, RR4 s)) MIDFUNC(2,jnf_EXT_l,(W4 d, RR4 s)) { @@ -1956,7 +1870,6 @@ MIDFUNC(2,jnf_EXT_l,(W4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_EXT_l,(W4 d, RR4 s)) MIDFUNC(2,jff_EXT_b,(W4 d, RR4 s)) { @@ -1975,7 +1888,6 @@ MIDFUNC(2,jff_EXT_b,(W4 d, RR4 s)) unlock2(d); } -MENDFUNC(2,jff_EXT_b,(W4 d, RR4 s)) MIDFUNC(2,jff_EXT_w,(W4 d, RR4 s)) { @@ -1994,7 +1906,6 @@ MIDFUNC(2,jff_EXT_w,(W4 d, RR4 s)) unlock2(d); } -MENDFUNC(2,jff_EXT_w,(W4 d, RR4 s)) MIDFUNC(2,jff_EXT_l,(W4 d, RR4 s)) { @@ -2012,7 +1923,6 @@ MIDFUNC(2,jff_EXT_l,(W4 d, RR4 s)) unlock2(d); } -MENDFUNC(2,jff_EXT_l,(W4 d, RR4 s)) /* * LSL @@ -2041,7 +1951,6 @@ MIDFUNC(3,jnf_LSL_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_LSL_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_LSL_reg,(W4 d, RR4 s, RR4 i)) { @@ -2056,7 +1965,6 @@ MIDFUNC(3,jnf_LSL_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_LSL_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSL_b_imm,(W4 d, RR4 s, IMM i)) { @@ -2077,7 +1985,6 @@ MIDFUNC(3,jff_LSL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_LSL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -2097,7 +2004,6 @@ MIDFUNC(3,jff_LSL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_LSL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -2115,7 +2021,6 @@ MIDFUNC(3,jff_LSL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_LSL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSL_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -2135,7 +2040,6 @@ MIDFUNC(3,jff_LSL_b_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_LSL_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSL_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -2154,7 +2058,6 @@ MIDFUNC(3,jff_LSL_w_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_LSL_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSL_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -2171,7 +2074,6 @@ MIDFUNC(3,jff_LSL_l_reg,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_LSL_l_reg,(W4 d, RR4 s, RR4 i)) /* * LSLW @@ -2196,7 +2098,6 @@ MIDFUNC(2,jnf_LSLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_LSLW,(W4 d, RR4 s)) MIDFUNC(2,jff_LSLW,(W4 d, RR4 s)) { @@ -2210,7 +2111,6 @@ MIDFUNC(2,jff_LSLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_LSLW,(W4 d, RR4 s)) /* * LSR @@ -2256,7 +2156,6 @@ MIDFUNC(3,jnf_LSR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jnf_LSR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_LSR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -2285,7 +2184,6 @@ MIDFUNC(3,jnf_LSR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jnf_LSR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_LSR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -2313,7 +2211,6 @@ MIDFUNC(3,jnf_LSR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jnf_LSR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSR_b_imm,(W4 d, RR4 s, IMM i)) { @@ -2343,7 +2240,6 @@ MIDFUNC(3,jff_LSR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jff_LSR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -2373,7 +2269,6 @@ MIDFUNC(3,jff_LSR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jff_LSR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_LSR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -2402,7 +2297,6 @@ MIDFUNC(3,jff_LSR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(s); } } -MENDFUNC(3,jff_LSR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_LSR_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -2431,7 +2325,6 @@ MIDFUNC(3,jnf_LSR_b_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jnf_LSR_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_LSR_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -2460,7 +2353,6 @@ MIDFUNC(3,jnf_LSR_w_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jnf_LSR_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_LSR_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -2488,7 +2380,6 @@ MIDFUNC(3,jnf_LSR_l_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jnf_LSR_l_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSR_b_reg,(W4 d, RR4 s, RR4 i)) { @@ -2519,7 +2410,6 @@ MIDFUNC(3,jff_LSR_b_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jff_LSR_b_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSR_w_reg,(W4 d, RR4 s, RR4 i)) { @@ -2550,7 +2440,6 @@ MIDFUNC(3,jff_LSR_w_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jff_LSR_w_reg,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_LSR_l_reg,(W4 d, RR4 s, RR4 i)) { @@ -2580,7 +2469,6 @@ MIDFUNC(3,jff_LSR_l_reg,(W4 d, RR4 s, RR4 i)) } unlock2(i); } -MENDFUNC(3,jff_LSR_l_reg,(W4 d, RR4 s, RR4 i)) /* * LSRW @@ -2606,7 +2494,6 @@ MIDFUNC(2,jnf_LSRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_LSRW,(W4 d, RR4 s)) MIDFUNC(2,jff_LSRW,(W4 d, RR4 s)) { @@ -2620,7 +2507,6 @@ MIDFUNC(2,jff_LSRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_LSRW,(W4 d, RR4 s)) /* * MOVE @@ -2649,7 +2535,6 @@ MIDFUNC(2,jnf_MOVE,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_MOVE,(W4 d, RR4 s)) MIDFUNC(2,jff_MOVE_b_imm,(W4 d, IMM s)) { @@ -2661,7 +2546,6 @@ MIDFUNC(2,jff_MOVE_b_imm,(W4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_MOVE_b_imm,(W4 d, IMM s)) MIDFUNC(2,jff_MOVE_w_imm,(W4 d, IMM s)) { @@ -2673,7 +2557,6 @@ MIDFUNC(2,jff_MOVE_w_imm,(W4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_MOVE_w_imm,(W4 d, IMM s)) MIDFUNC(2,jff_MOVE_l_imm,(W4 d, IMM s)) { @@ -2685,7 +2568,6 @@ MIDFUNC(2,jff_MOVE_l_imm,(W4 d, IMM s)) unlock2(d); } -MENDFUNC(2,jff_MOVE_l_imm,(W4 d, IMM s)) MIDFUNC(2,jff_MOVE_b,(W4 d, RR1 s)) { @@ -2704,7 +2586,6 @@ MIDFUNC(2,jff_MOVE_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_MOVE_b,(W4 d, RR1 s)) MIDFUNC(2,jff_MOVE_w,(W4 d, RR2 s)) { @@ -2723,7 +2604,6 @@ MIDFUNC(2,jff_MOVE_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_MOVE_w,(W4 d, RR2 s)) MIDFUNC(2,jff_MOVE_l,(W4 d, RR4 s)) { @@ -2741,7 +2621,6 @@ MIDFUNC(2,jff_MOVE_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_MOVE_l,(W4 d, RR4 s)) /* * MOVE16 @@ -2776,7 +2655,6 @@ MIDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s)) /* * MOVEA @@ -2797,7 +2675,6 @@ MIDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s)) MIDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s)) { @@ -2809,7 +2686,6 @@ MIDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s)) /* * MULS @@ -2836,7 +2712,6 @@ MIDFUNC(2,jnf_MULS,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULS,(RW4 d, RR4 s)) MIDFUNC(2,jff_MULS,(RW4 d, RR4 s)) { @@ -2852,7 +2727,6 @@ MIDFUNC(2,jff_MULS,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULS,(RW4 d, RR4 s)) MIDFUNC(2,jnf_MULS32,(RW4 d, RR4 s)) { @@ -2864,7 +2738,6 @@ MIDFUNC(2,jnf_MULS32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULS32,(RW4 d, RR4 s)) MIDFUNC(2,jff_MULS32,(RW4 d, RR4 s)) { @@ -2882,7 +2755,6 @@ MIDFUNC(2,jff_MULS32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULS32,(RW4 d, RR4 s)) MIDFUNC(2,jnf_MULS64,(RW4 d, RW4 s)) { @@ -2895,7 +2767,6 @@ MIDFUNC(2,jnf_MULS64,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULS64,(RW4 d, RW4 s)) MIDFUNC(2,jff_MULS64,(RW4 d, RW4 s)) { @@ -2913,7 +2784,6 @@ MIDFUNC(2,jff_MULS64,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULS64,(RW4 d, RW4 s)) /* * MULU @@ -2941,7 +2811,6 @@ MIDFUNC(2,jnf_MULU,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULU,(RW4 d, RR4 s)) MIDFUNC(2,jff_MULU,(RW4 d, RR4 s)) { @@ -2957,7 +2826,6 @@ MIDFUNC(2,jff_MULU,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULU,(RW4 d, RR4 s)) MIDFUNC(2,jnf_MULU32,(RW4 d, RR4 s)) { @@ -2969,7 +2837,6 @@ MIDFUNC(2,jnf_MULU32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULU32,(RW4 d, RR4 s)) MIDFUNC(2,jff_MULU32,(RW4 d, RR4 s)) { @@ -2987,7 +2854,6 @@ MIDFUNC(2,jff_MULU32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULU32,(RW4 d, RR4 s)) MIDFUNC(2,jnf_MULU64,(RW4 d, RW4 s)) { @@ -3000,7 +2866,6 @@ MIDFUNC(2,jnf_MULU64,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jnf_MULU64,(RW4 d, RW4 s)) MIDFUNC(2,jff_MULU64,(RW4 d, RW4 s)) { @@ -3018,7 +2883,6 @@ MIDFUNC(2,jff_MULU64,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,jff_MULU64,(RW4 d, RW4 s)) /* * NEG @@ -3043,7 +2907,6 @@ MIDFUNC(2,jnf_NEG,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_NEG,(W4 d, RR4 s)) MIDFUNC(2,jff_NEG_b,(W4 d, RR1 s)) { @@ -3061,7 +2924,6 @@ MIDFUNC(2,jff_NEG_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEG_b,(W4 d, RR1 s)) MIDFUNC(2,jff_NEG_w,(W4 d, RR2 s)) { @@ -3079,7 +2941,6 @@ MIDFUNC(2,jff_NEG_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEG_w,(W4 d, RR2 s)) MIDFUNC(2,jff_NEG_l,(W4 d, RR4 s)) { @@ -3096,7 +2957,6 @@ MIDFUNC(2,jff_NEG_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEG_l,(W4 d, RR4 s)) /* * NEGX @@ -3123,7 +2983,6 @@ MIDFUNC(2,jnf_NEGX,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_NEGX,(W4 d, RR4 s)) MIDFUNC(2,jff_NEGX_b,(W4 d, RR1 s)) { @@ -3145,7 +3004,6 @@ MIDFUNC(2,jff_NEGX_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEGX_b,(W4 d, RR1 s)) MIDFUNC(2,jff_NEGX_w,(W4 d, RR2 s)) { @@ -3167,7 +3025,6 @@ MIDFUNC(2,jff_NEGX_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEGX_w,(W4 d, RR2 s)) MIDFUNC(2,jff_NEGX_l,(W4 d, RR4 s)) { @@ -3188,7 +3045,6 @@ MIDFUNC(2,jff_NEGX_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NEGX_l,(W4 d, RR4 s)) /* * NOT @@ -3213,7 +3069,6 @@ MIDFUNC(2,jnf_NOT,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_NOT,(W4 d, RR4 s)) MIDFUNC(2,jff_NOT_b,(W4 d, RR1 s)) { @@ -3227,7 +3082,6 @@ MIDFUNC(2,jff_NOT_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NOT_b,(W4 d, RR1 s)) MIDFUNC(2,jff_NOT_w,(W4 d, RR2 s)) { @@ -3241,7 +3095,6 @@ MIDFUNC(2,jff_NOT_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NOT_w,(W4 d, RR2 s)) MIDFUNC(2,jff_NOT_l,(W4 d, RR4 s)) { @@ -3254,7 +3107,6 @@ MIDFUNC(2,jff_NOT_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_NOT_l,(W4 d, RR4 s)) /* * OR @@ -3288,7 +3140,6 @@ MIDFUNC(3,jnf_OR,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_OR,(RW4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_OR_b,(W4 d, RR1 s, RR1 v)) { @@ -3305,7 +3156,6 @@ MIDFUNC(3,jff_OR_b,(W4 d, RR1 s, RR1 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_OR_b,(RW4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_OR_w,(W4 d, RR2 s, RR2 v)) { @@ -3322,7 +3172,6 @@ MIDFUNC(3,jff_OR_w,(W4 d, RR2 s, RR2 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_OR_w,(RW4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_OR_l,(W4 d, RR4 s, RR4 v)) { @@ -3337,7 +3186,6 @@ MIDFUNC(3,jff_OR_l,(W4 d, RR4 s, RR4 v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_OR_l,(RW4 d, RR4 s, RR4 v)) /* * ORI @@ -3364,7 +3212,6 @@ MIDFUNC(1,jff_ORSR,(IMM s, IMM x)) STRB_rR(REG_WORK2, REG_WORK1); } } -MENDFUNC(1,jff_ORSR,(IMM s)) /* * ROL @@ -3394,7 +3241,6 @@ MIDFUNC(3,jnf_ROL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -3408,7 +3254,6 @@ MIDFUNC(3,jnf_ROL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -3420,7 +3265,6 @@ MIDFUNC(3,jnf_ROL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROL_b_imm,(W4 d, RR4 s, IMM i)) { @@ -3447,7 +3291,6 @@ MIDFUNC(3,jff_ROL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -3473,7 +3316,6 @@ MIDFUNC(3,jff_ROL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -3497,7 +3339,6 @@ MIDFUNC(3,jff_ROL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROL_b,(W4 d, RR4 s, RR4 i)) { @@ -3521,7 +3362,6 @@ MIDFUNC(3,jnf_ROL_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROL_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROL_w,(W4 d, RR4 s, RR4 i)) { @@ -3544,7 +3384,6 @@ MIDFUNC(3,jnf_ROL_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROL_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROL_l,(W4 d, RR4 s, RR4 i)) { @@ -3565,7 +3404,6 @@ MIDFUNC(3,jnf_ROL_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROL_l,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROL_b,(W4 d, RR4 s, RR4 i)) { @@ -3597,7 +3435,6 @@ MIDFUNC(3,jff_ROL_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROL_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROL_w,(W4 d, RR4 s, RR4 i)) { @@ -3628,7 +3465,6 @@ MIDFUNC(3,jff_ROL_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROL_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROL_l,(W4 d, RR4 s, RR4 i)) { @@ -3657,7 +3493,6 @@ MIDFUNC(3,jff_ROL_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROL_l,(W4 d, RR4 s, RR4 i)) /* * ROLW @@ -3684,7 +3519,6 @@ MIDFUNC(2,jnf_ROLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ROLW,(W4 d, RR4 s)) MIDFUNC(2,jff_ROLW,(W4 d, RR4 s)) { @@ -3705,7 +3539,6 @@ MIDFUNC(2,jff_ROLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_ROLW,(W4 d, RR4 s)) /* * RORW @@ -3732,7 +3565,6 @@ MIDFUNC(2,jnf_RORW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_RORW,(W4 d, RR4 s)) MIDFUNC(2,jff_RORW,(W4 d, RR4 s)) { @@ -3747,7 +3579,6 @@ MIDFUNC(2,jff_RORW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_RORW,(W4 d, RR4 s)) /* * ROXL @@ -3780,7 +3611,6 @@ MIDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -3799,7 +3629,6 @@ MIDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -3817,7 +3646,6 @@ MIDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i)) { @@ -3843,7 +3671,6 @@ MIDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i)) { @@ -3869,7 +3696,6 @@ MIDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i)) { @@ -3893,7 +3719,6 @@ MIDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i)) { @@ -3940,7 +3765,6 @@ MIDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i)) { @@ -3984,7 +3808,6 @@ MIDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i)) { @@ -4016,7 +3839,6 @@ MIDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i)) { @@ -4082,7 +3904,6 @@ MIDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i)) { @@ -4147,7 +3968,6 @@ MIDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i)) { @@ -4196,7 +4016,6 @@ MIDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i)) /* * ROXLW @@ -4222,7 +4041,6 @@ MIDFUNC(2,jnf_ROXLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ROXLW,(W4 d, RR4 s)) MIDFUNC(2,jff_ROXLW,(W4 d, RR4 s)) { @@ -4238,7 +4056,6 @@ MIDFUNC(2,jff_ROXLW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_ROXLW,(W4 d, RR4 s)) /* * ROR @@ -4268,7 +4085,6 @@ MIDFUNC(3,jnf_ROR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -4282,7 +4098,6 @@ MIDFUNC(3,jnf_ROR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -4294,7 +4109,6 @@ MIDFUNC(3,jnf_ROR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROR_b_imm,(W4 d, RR4 s, IMM i)) { @@ -4310,7 +4124,6 @@ MIDFUNC(3,jff_ROR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -4325,7 +4138,6 @@ MIDFUNC(3,jff_ROR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -4338,7 +4150,6 @@ MIDFUNC(3,jff_ROR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROR_b,(W4 d, RR4 s, RR4 i)) { @@ -4359,7 +4170,6 @@ MIDFUNC(3,jnf_ROR_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROR_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROR_w,(W4 d, RR4 s, RR4 i)) { @@ -4379,7 +4189,6 @@ MIDFUNC(3,jnf_ROR_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROR_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROR_l,(W4 d, RR4 s, RR4 i)) { @@ -4397,7 +4206,6 @@ MIDFUNC(3,jnf_ROR_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROR_l,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROR_b,(W4 d, RR4 s, RR4 i)) { @@ -4421,7 +4229,6 @@ MIDFUNC(3,jff_ROR_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROR_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROR_w,(W4 d, RR4 s, RR4 i)) { @@ -4444,7 +4251,6 @@ MIDFUNC(3,jff_ROR_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROR_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROR_l,(W4 d, RR4 s, RR4 i)) { @@ -4465,7 +4271,6 @@ MIDFUNC(3,jff_ROR_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROR_l,(W4 d, RR4 s, RR4 i)) /* * ROXR @@ -4497,7 +4302,6 @@ MIDFUNC(3,jnf_ROXR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -4515,7 +4319,6 @@ MIDFUNC(3,jnf_ROXR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -4533,7 +4336,6 @@ MIDFUNC(3,jnf_ROXR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_ROXR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXR_b_imm,(W4 d, RR4 s, IMM i)) { @@ -4559,7 +4361,6 @@ MIDFUNC(3,jff_ROXR_b_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXR_b_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXR_w_imm,(W4 d, RR4 s, IMM i)) { @@ -4585,7 +4386,6 @@ MIDFUNC(3,jff_ROXR_w_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXR_w_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jff_ROXR_l_imm,(W4 d, RR4 s, IMM i)) { @@ -4609,7 +4409,6 @@ MIDFUNC(3,jff_ROXR_l_imm,(W4 d, RR4 s, IMM i)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_ROXR_l_imm,(W4 d, RR4 s, IMM i)) MIDFUNC(3,jnf_ROXR_b,(W4 d, RR4 s, RR4 i)) { @@ -4647,7 +4446,6 @@ MIDFUNC(3,jnf_ROXR_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXR_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROXR_w,(W4 d, RR4 s, RR4 i)) { @@ -4682,7 +4480,6 @@ MIDFUNC(3,jnf_ROXR_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXR_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jnf_ROXR_l,(W4 d, RR4 s, RR4 i)) { @@ -4715,7 +4512,6 @@ MIDFUNC(3,jnf_ROXR_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jnf_ROXR_l,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXR_b,(W4 d, RR4 s, RR4 i)) { @@ -4769,7 +4565,6 @@ MIDFUNC(3,jff_ROXR_b,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXR_b,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXR_w,(W4 d, RR4 s, RR4 i)) { @@ -4821,7 +4616,6 @@ MIDFUNC(3,jff_ROXR_w,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXR_w,(W4 d, RR4 s, RR4 i)) MIDFUNC(3,jff_ROXR_l,(W4 d, RR4 s, RR4 i)) { @@ -4870,7 +4664,6 @@ MIDFUNC(3,jff_ROXR_l,(W4 d, RR4 s, RR4 i)) unlock2(s); unlock2(i); } -MENDFUNC(3,jff_ROXR_l,(W4 d, RR4 s, RR4 i)) /* * ROXRW @@ -4897,7 +4690,6 @@ MIDFUNC(2,jnf_ROXRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_ROXRW,(W4 d, RR4 s)) MIDFUNC(2,jff_ROXRW,(W4 d, RR4 s)) { @@ -4912,7 +4704,6 @@ MIDFUNC(2,jff_ROXRW,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jff_ROXRW,(W4 d, RR4 s)) /* * SUB @@ -4944,7 +4735,6 @@ MIDFUNC(3,jnf_SUB_b_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_SUB_b_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jnf_SUB_b,(W4 d, RR4 s, RR4 v)) { @@ -4964,7 +4754,6 @@ MIDFUNC(3,jnf_SUB_b,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_SUB_b,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jnf_SUB_w_imm,(W4 d, RR4 s, IMM v)) { @@ -4982,7 +4771,6 @@ MIDFUNC(3,jnf_SUB_w_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_SUB_w_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jnf_SUB_w,(W4 d, RR4 s, RR4 v)) { @@ -5002,7 +4790,6 @@ MIDFUNC(3,jnf_SUB_w,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_SUB_w,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jnf_SUB_l_imm,(W4 d, RR4 s, IMM v)) { @@ -5020,7 +4807,6 @@ MIDFUNC(3,jnf_SUB_l_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jnf_SUB_l_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jnf_SUB_l,(W4 d, RR4 s, RR4 v)) { @@ -5040,7 +4826,6 @@ MIDFUNC(3,jnf_SUB_l,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_SUB_l,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_SUB_b_imm,(W4 d, RR1 s, IMM v)) { @@ -5060,7 +4845,6 @@ MIDFUNC(3,jff_SUB_b_imm,(W4 d, RR1 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_SUB_b_imm,(W4 d, RR1 s, IMM v)) MIDFUNC(3,jff_SUB_b,(W4 d, RR1 s, RR1 v)) { @@ -5087,7 +4871,6 @@ MIDFUNC(3,jff_SUB_b,(W4 d, RR1 s, RR1 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUB_b,(W4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_SUB_w_imm,(W4 d, RR2 s, IMM v)) { @@ -5107,7 +4890,6 @@ MIDFUNC(3,jff_SUB_w_imm,(W4 d, RR2 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jitc_SUB_ff_w2l_rri,(W4 d, RR2 s, IMM v)) MIDFUNC(3,jff_SUB_w,(W4 d, RR2 s, RR2 v)) { @@ -5134,7 +4916,6 @@ MIDFUNC(3,jff_SUB_w,(W4 d, RR2 s, RR2 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUB_w,(W4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_SUB_l_imm,(W4 d, RR4 s, IMM v)) { @@ -5153,7 +4934,6 @@ MIDFUNC(3,jff_SUB_l_imm,(W4 d, RR4 s, IMM v)) unlock2(d); unlock2(s); } -MENDFUNC(3,jff_SUB_l_imm,(W4 d, RR4 s, IMM v)) MIDFUNC(3,jff_SUB_l,(W4 d, RR4 s, RR4 v)) { @@ -5178,7 +4958,6 @@ MIDFUNC(3,jff_SUB_l,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUB_l,(W4 d, RR4 s, RR4 v)) /* * SUBA @@ -5201,7 +4980,6 @@ MIDFUNC(2,jnf_SUBA_b,(W4 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_SUBA_b,(W4 d, RR1 s)) MIDFUNC(2,jnf_SUBA_w,(W4 d, RR2 s)) { @@ -5214,7 +4992,6 @@ MIDFUNC(2,jnf_SUBA_w,(W4 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_SUBA_w,(W4 d, RR2 s)) MIDFUNC(2,jnf_SUBA_l,(W4 d, RR4 s)) { @@ -5226,7 +5003,6 @@ MIDFUNC(2,jnf_SUBA_l,(W4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,jnf_SUBA_l,(W4 d, RR4 s)) /* * SUBX @@ -5256,7 +5032,6 @@ MIDFUNC(3,jnf_SUBX,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jnf_SUBX,(W4 d, RR4 s, RR4 v)) MIDFUNC(3,jff_SUBX_b,(W4 d, RR1 s, RR1 v)) { @@ -5283,7 +5058,6 @@ MIDFUNC(3,jff_SUBX_b,(W4 d, RR1 s, RR1 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUBX_b,(W4 d, RR1 s, RR1 v)) MIDFUNC(3,jff_SUBX_w,(W4 d, RR2 s, RR2 v)) { @@ -5310,7 +5084,6 @@ MIDFUNC(3,jff_SUBX_w,(W4 d, RR2 s, RR2 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUBX_w,(W4 d, RR2 s, RR2 v)) MIDFUNC(3,jff_SUBX_l,(W4 d, RR4 s, RR4 v)) { @@ -5333,7 +5106,6 @@ MIDFUNC(3,jff_SUBX_l,(W4 d, RR4 s, RR4 v)) unlock2(s); unlock2(v); } -MENDFUNC(3,jff_SUBX_l,(W4 d, RR4 s, RR4 v)) /* * SWAP @@ -5356,7 +5128,6 @@ MIDFUNC(1,jnf_SWAP,(RW4 d)) unlock2(d); } -MENDFUNC(1,jnf_SWAP,(RW4 d)) MIDFUNC(1,jff_SWAP,(RW4 d)) { @@ -5368,7 +5139,6 @@ MIDFUNC(1,jff_SWAP,(RW4 d)) unlock2(d); } -MENDFUNC(1,jff_SWAP,(RW4 d)) /* * TST @@ -5395,7 +5165,6 @@ MIDFUNC(1,jff_TST_b,(RR1 s)) MSR_CPSRf_i(0); TST_rr(REG_WORK1,REG_WORK1); } -MENDFUNC(1,jff_TST_b,(RR1 s)) MIDFUNC(1,jff_TST_w,(RR2 s)) { @@ -5409,7 +5178,6 @@ MIDFUNC(1,jff_TST_w,(RR2 s)) MSR_CPSRf_i(0); TST_rr(REG_WORK1,REG_WORK1); } -MENDFUNC(1,jff_TST_w,(RR2 s)) MIDFUNC(1,jff_TST_l,(RR4 s)) { @@ -5425,4 +5193,3 @@ MIDFUNC(1,jff_TST_l,(RR4 s)) unlock2(s); } } -MENDFUNC(1,jff_TST_l,(RR4 s)) diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.cpp b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.cpp index d5e2e053..c322e590 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.cpp +++ b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.cpp @@ -98,14 +98,16 @@ MIDFUNC(0,live_flags,(void)) live.flags_in_flags=VALID; live.flags_are_important=1; } -MENDFUNC(0,live_flags,(void)) MIDFUNC(0,dont_care_flags,(void)) { live.flags_are_important=0; } -MENDFUNC(0,dont_care_flags,(void)) +/* + * store the state of the x86 carry bit into regflags.x, + * into the position denoted by FLAGBIT_X + */ MIDFUNC(0,duplicate_carry,(void)) { evict(FLAGX); @@ -117,54 +119,96 @@ MIDFUNC(0,duplicate_carry,(void)) #endif log_vwrite(FLAGX); } -MENDFUNC(0,duplicate_carry,(void)) +MIDFUNC(3,setcc_for_cntzero,(RR4 /* cnt */, RR4 data, int size)) +{ + uae_u8 *branchadd; + uae_u8 *branchadd2; + + evict(FLAGX); + make_flags_live_internal(); + + raw_pushfl(); + /* + * shift count can only be in CL register; see shrl_b_rr + */ + raw_test_b_rr(X86_CL, X86_CL); + /* if zero, leave X unaffected; carry flag will already be cleared */ + raw_jz_b_oponly(); + branchadd = get_target(); + skip_byte(); + + /* shift count was non-zero; update also x-flag */ + raw_popfl(); +#ifdef UAE + COMPCALL(setcc_m)((uintptr)live.state[FLAGX].mem + 1, NATIVE_CC_CS); +#else + COMPCALL(setcc_m)((uintptr)live.state[FLAGX].mem, NATIVE_CC_CS); +#endif + log_vwrite(FLAGX); + raw_jmp_b_oponly(); + branchadd2 = get_target(); + skip_byte(); + *branchadd = (uintptr)get_target() - ((uintptr)branchadd + 1); + + /* shift count was zero; need to set Z & N flags since the native flags were unaffected */ + raw_popfl(); + data = readreg(data, size); + switch (size) + { + case 1: raw_test_b_rr(data, data); break; + case 2: raw_test_w_rr(data, data); break; + case 4: raw_test_l_rr(data, data); break; + } + unlock2(data); + *branchadd2 = (uintptr)get_target() - ((uintptr)branchadd2 + 1); +} + +/* + * Set the x86 carry flag from regflags.x, from the position + * denoted by FLAGBIT_X + */ MIDFUNC(0,restore_carry,(void)) { if (!have_rat_stall) { /* Not a P6 core, i.e. no partial stalls */ #ifdef UAE - bt_l_ri_noclobber(FLAGX, 8); + bt_l_ri_noclobber(FLAGX, FLAGBIT_X+8); #else - bt_l_ri_noclobber(FLAGX, 0); + bt_l_ri_noclobber(FLAGX, FLAGBIT_X); #endif } else { /* Avoid the stall the above creates. This is slow on non-P6, though. */ -#ifdef UAE - COMPCALL(rol_w_ri(FLAGX, 8)); +#if defined(UAE) || FLAGBIT_X >= 8 + COMPCALL(rol_w_ri(FLAGX, 16 - FLAGBIT_X)); #else - COMPCALL(rol_b_ri(FLAGX, 8)); + COMPCALL(rol_b_ri(FLAGX, 8 - FLAGBIT_X)); #endif isclean(FLAGX); } } -MENDFUNC(0,restore_carry,(void)) MIDFUNC(0,start_needflags,(void)) { needflags=1; } -MENDFUNC(0,start_needflags,(void)) MIDFUNC(0,end_needflags,(void)) { needflags=0; } -MENDFUNC(0,end_needflags,(void)) MIDFUNC(0,make_flags_live,(void)) { make_flags_live_internal(); } -MENDFUNC(0,make_flags_live,(void)) MIDFUNC(1,fflags_into_flags,(W2 tmp)) { clobber_flags(); fflags_into_flags_internal(tmp); } -MENDFUNC(1,fflags_into_flags,(W2 tmp)) MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ { @@ -176,7 +220,6 @@ MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ raw_bt_l_ri(r,i); unlock2(r); } -MENDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */ MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ { @@ -187,7 +230,6 @@ MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ unlock2(r); unlock2(b); } -MENDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */ MIDFUNC(2,btc_l_ri,(RW4 r, IMM i)) { @@ -199,7 +241,6 @@ MIDFUNC(2,btc_l_ri,(RW4 r, IMM i)) raw_btc_l_ri(r,i); unlock2(r); } -MENDFUNC(2,btc_l_ri,(RW4 r, IMM i)) MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) { @@ -210,7 +251,6 @@ MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,btc_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,btr_l_ri,(RW4 r, IMM i)) { @@ -222,7 +262,6 @@ MIDFUNC(2,btr_l_ri,(RW4 r, IMM i)) raw_btr_l_ri(r,i); unlock2(r); } -MENDFUNC(2,btr_l_ri,(RW4 r, IMM i)) MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) { @@ -233,7 +272,6 @@ MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,btr_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,bts_l_ri,(RW4 r, IMM i)) { @@ -245,7 +283,6 @@ MIDFUNC(2,bts_l_ri,(RW4 r, IMM i)) raw_bts_l_ri(r,i); unlock2(r); } -MENDFUNC(2,bts_l_ri,(RW4 r, IMM i)) MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) { @@ -256,7 +293,6 @@ MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) unlock2(r); unlock2(b); } -MENDFUNC(2,bts_l_rr,(RW4 r, RR4 b)) MIDFUNC(2,mov_l_rm,(W4 d, IMM s)) { @@ -265,7 +301,6 @@ MIDFUNC(2,mov_l_rm,(W4 d, IMM s)) raw_mov_l_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_l_rm,(W4 d, IMM s)) MIDFUNC(1,call_r,(RR4 r)) /* Clobbering is implicit */ { @@ -275,35 +310,30 @@ MIDFUNC(1,call_r,(RR4 r)) /* Clobbering is implicit */ raw_inc_sp(STACK_SHADOW_SPACE); unlock2(r); } -MENDFUNC(1,call_r,(RR4 r)) /* Clobbering is implicit */ MIDFUNC(2,sub_l_mi,(IMM d, IMM s)) { CLOBBER_SUB; raw_sub_l_mi(d,s) ; } -MENDFUNC(2,sub_l_mi,(IMM d, IMM s)) MIDFUNC(2,mov_l_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_l_mi(d,s) ; } -MENDFUNC(2,mov_l_mi,(IMM d, IMM s)) MIDFUNC(2,mov_w_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_w_mi(d,s) ; } -MENDFUNC(2,mov_w_mi,(IMM d, IMM s)) MIDFUNC(2,mov_b_mi,(IMM d, IMM s)) { CLOBBER_MOV; raw_mov_b_mi(d,s) ; } -MENDFUNC(2,mov_b_mi,(IMM d, IMM s)) MIDFUNC(2,rol_b_ri,(RW1 r, IMM i)) { @@ -314,7 +344,6 @@ MIDFUNC(2,rol_b_ri,(RW1 r, IMM i)) raw_rol_b_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_b_ri,(RW1 r, IMM i)) MIDFUNC(2,rol_w_ri,(RW2 r, IMM i)) { @@ -325,7 +354,6 @@ MIDFUNC(2,rol_w_ri,(RW2 r, IMM i)) raw_rol_w_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_w_ri,(RW2 r, IMM i)) MIDFUNC(2,rol_l_ri,(RW4 r, IMM i)) { @@ -336,49 +364,46 @@ MIDFUNC(2,rol_l_ri,(RW4 r, IMM i)) raw_rol_l_ri(r,i); unlock2(r); } -MENDFUNC(2,rol_l_ri,(RW4 r, IMM i)) MIDFUNC(2,rol_l_rr,(RW4 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(rol_l_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_ROL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,4,4); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in rol_l_rr",r); } raw_rol_l_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,rol_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,rol_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(rol_w_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_ROL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,2,2); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in rol_w_rr",r); } raw_rol_w_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,rol_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(rol_b_ri)(d,(uae_u8)live.state[r].val); return; } @@ -386,57 +411,54 @@ MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) CLOBBER_ROL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,1,1); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in rol_b_rr",r); } raw_rol_b_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,rol_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,shll_l_rr,(RW4 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shll_l_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHLL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,4,4); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shll_l_rr",r); } raw_shll_l_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shll_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shll_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shll_w_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHLL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,2,2); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shll_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shll_w_rr",r); } raw_shll_w_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shll_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shll_b_ri)(d,(uae_u8)live.state[r].val); return; } @@ -444,14 +466,13 @@ MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) CLOBBER_SHLL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,1,1); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shll_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shll_b_rr",r); } raw_shll_b_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shll_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,ror_b_ri,(RR1 r, IMM i)) @@ -463,7 +484,6 @@ MIDFUNC(2,ror_b_ri,(RR1 r, IMM i)) raw_ror_b_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_b_ri,(RR1 r, IMM i)) MIDFUNC(2,ror_w_ri,(RR2 r, IMM i)) { @@ -474,7 +494,6 @@ MIDFUNC(2,ror_w_ri,(RR2 r, IMM i)) raw_ror_w_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_w_ri,(RR2 r, IMM i)) MIDFUNC(2,ror_l_ri,(RR4 r, IMM i)) { @@ -485,11 +504,10 @@ MIDFUNC(2,ror_l_ri,(RR4 r, IMM i)) raw_ror_l_ri(r,i); unlock2(r); } -MENDFUNC(2,ror_l_ri,(RR4 r, IMM i)) MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(ror_l_ri)(d,(uae_u8)live.state[r].val); return; } @@ -500,11 +518,10 @@ MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_l_rr,(RR4 d, RR1 r)) MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(ror_w_ri)(d,(uae_u8)live.state[r].val); return; } @@ -515,11 +532,10 @@ MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_w_rr,(RR2 d, RR1 r)) MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(ror_b_ri)(d,(uae_u8)live.state[r].val); return; } @@ -531,49 +547,46 @@ MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) unlock2(r); unlock2(d); } -MENDFUNC(2,ror_b_rr,(RR1 d, RR1 r)) MIDFUNC(2,shrl_l_rr,(RW4 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shrl_l_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHRL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,4,4); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shrl_l_rr",r); } raw_shrl_l_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shrl_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shrl_w_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHRL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,2,2); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shrl_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shrl_w_rr",r); } raw_shrl_w_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shrl_b_ri)(d,(uae_u8)live.state[r].val); return; } @@ -581,14 +594,13 @@ MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) CLOBBER_SHRL; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,1,1); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shrl_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shrl_b_rr",r); } raw_shrl_b_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shrl_b_rr,(RW1 d, RR1 r)) @@ -605,7 +617,6 @@ MIDFUNC(2,shll_l_ri,(RW4 r, IMM i)) raw_shll_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shll_w_ri,(RW2 r, IMM i)) { @@ -616,7 +627,6 @@ MIDFUNC(2,shll_w_ri,(RW2 r, IMM i)) raw_shll_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shll_b_ri,(RW1 r, IMM i)) { @@ -627,7 +637,6 @@ MIDFUNC(2,shll_b_ri,(RW1 r, IMM i)) raw_shll_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shll_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) { @@ -642,7 +651,6 @@ MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) raw_shrl_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) { @@ -653,7 +661,6 @@ MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) raw_shrl_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) { @@ -664,7 +671,6 @@ MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) raw_shrl_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shrl_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shra_l_ri,(RW4 r, IMM i)) { @@ -675,7 +681,6 @@ MIDFUNC(2,shra_l_ri,(RW4 r, IMM i)) raw_shra_l_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_l_ri,(RW4 r, IMM i)) MIDFUNC(2,shra_w_ri,(RW2 r, IMM i)) { @@ -686,7 +691,6 @@ MIDFUNC(2,shra_w_ri,(RW2 r, IMM i)) raw_shra_w_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_w_ri,(RW2 r, IMM i)) MIDFUNC(2,shra_b_ri,(RW1 r, IMM i)) { @@ -697,49 +701,46 @@ MIDFUNC(2,shra_b_ri,(RW1 r, IMM i)) raw_shra_b_ri(r,i); unlock2(r); } -MENDFUNC(2,shra_b_ri,(RW1 r, IMM i)) MIDFUNC(2,shra_l_rr,(RW4 d, RR1 r)) { - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shra_l_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHRA; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,4,4); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_rol_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shra_l_rr",r); } raw_shra_l_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shra_l_rr,(RW4 d, RR1 r)) MIDFUNC(2,shra_w_rr,(RW2 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shra_w_ri)(d,(uae_u8)live.state[r].val); return; } CLOBBER_SHRA; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,2,2); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shra_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shra_w_rr",r); } raw_shra_w_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shra_w_rr,(RW2 d, RR1 r)) MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) { /* Can only do this with r==1, i.e. cl */ - if (isconst(r)) { + if (isconst(r) && (uae_u8)live.state[r].val != 0) { COMPCALL(shra_b_ri)(d,(uae_u8)live.state[r].val); return; } @@ -747,14 +748,13 @@ MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) CLOBBER_SHRA; r=readreg_specific(r,1,SHIFTCOUNT_NREG); d=rmw(d,1,1); - Dif (r!=1) { - jit_abort("Illegal register %d in raw_shra_b",r); + Dif (r!=X86_CL) { + jit_abort("Illegal register %d in shra_b_rr",r); } raw_shra_b_rr(d,r) ; unlock2(r); unlock2(d); } -MENDFUNC(2,shra_b_rr,(RW1 d, RR1 r)) MIDFUNC(2,setcc,(W1 d, IMM cc)) @@ -764,14 +764,12 @@ MIDFUNC(2,setcc,(W1 d, IMM cc)) raw_setcc(d,cc); unlock2(d); } -MENDFUNC(2,setcc,(W1 d, IMM cc)) MIDFUNC(2,setcc_m,(IMM d, IMM cc)) { CLOBBER_SETCC; raw_setcc_m(d,cc); } -MENDFUNC(2,setcc_m,(IMM d, IMM cc)) MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) { @@ -784,7 +782,6 @@ MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) unlock2(s); unlock2(d); } -MENDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc)) MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc)) { @@ -793,7 +790,6 @@ MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc)) raw_cmov_l_rm(d,s,cc); unlock2(d); } -MENDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc)) MIDFUNC(2,bsf_l_rr,(W4 d, RR4 s)) { @@ -804,7 +800,6 @@ MIDFUNC(2,bsf_l_rr,(W4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,bsf_l_rr,(W4 d, RR4 s)) /* Set the Z flag depending on the value in s. Note that the value has to be 0 or -1 (or, more precisely, for non-zero @@ -818,7 +813,6 @@ MIDFUNC(2,simulate_bsf,(W4 tmp, RW4 s)) unlock2(tmp); unlock2(s); } -MENDFUNC(2,simulate_bsf,(W4 tmp, RW4 s)) MIDFUNC(2,imul_32_32,(RW4 d, RR4 s)) { @@ -829,7 +823,6 @@ MIDFUNC(2,imul_32_32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,imul_32_32,(RW4 d, RR4 s)) MIDFUNC(2,imul_64_32,(RW4 d, RW4 s)) { @@ -840,7 +833,6 @@ MIDFUNC(2,imul_64_32,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,imul_64_32,(RW4 d, RW4 s)) MIDFUNC(2,mul_64_32,(RW4 d, RW4 s)) { @@ -851,7 +843,6 @@ MIDFUNC(2,mul_64_32,(RW4 d, RW4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,mul_64_32,(RW4 d, RW4 s)) MIDFUNC(2,mul_32_32,(RW4 d, RR4 s)) { @@ -862,7 +853,6 @@ MIDFUNC(2,mul_32_32,(RW4 d, RR4 s)) unlock2(s); unlock2(d); } -MENDFUNC(2,mul_32_32,(RW4 d, RR4 s)) #if SIZEOF_VOID_P == 8 MIDFUNC(2,sign_extend_32_rr,(W4 d, RR2 s)) @@ -893,7 +883,6 @@ MIDFUNC(2,sign_extend_32_rr,(W4 d, RR2 s)) unlock2(s); } } -MENDFUNC(2,sign_extend_32_rr,(W4 d, RR2 s)) #endif MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) @@ -924,7 +913,6 @@ MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) unlock2(s); } } -MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s)) MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) { @@ -956,7 +944,6 @@ MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) unlock2(s); } } -MENDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s)) MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) @@ -987,7 +974,6 @@ MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) unlock2(s); } } -MENDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s)) MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) { @@ -1018,7 +1004,6 @@ MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) unlock2(s); } } -MENDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s)) MIDFUNC(2,mov_b_rr,(W1 d, RR1 s)) { @@ -1036,7 +1021,6 @@ MIDFUNC(2,mov_b_rr,(W1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,mov_b_rr,(W1 d, RR1 s)) MIDFUNC(2,mov_w_rr,(W2 d, RR2 s)) { @@ -1054,7 +1038,6 @@ MIDFUNC(2,mov_w_rr,(W2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,mov_w_rr,(W2 d, RR2 s)) MIDFUNC(4,mov_l_rrm_indexed,(W4 d,RR4 baser, RR4 index, IMM factor)) { @@ -1068,7 +1051,6 @@ MIDFUNC(4,mov_l_rrm_indexed,(W4 d,RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_l_rrm_indexed,(W4 d,RR4 baser, RR4 index, IMM factor)) MIDFUNC(4,mov_w_rrm_indexed,(W2 d, RR4 baser, RR4 index, IMM factor)) { @@ -1082,7 +1064,6 @@ MIDFUNC(4,mov_w_rrm_indexed,(W2 d, RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_w_rrm_indexed,(W2 d, RR4 baser, RR4 index, IMM factor)) MIDFUNC(4,mov_b_rrm_indexed,(W1 d, RR4 baser, RR4 index, IMM factor)) { @@ -1097,7 +1078,6 @@ MIDFUNC(4,mov_b_rrm_indexed,(W1 d, RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_b_rrm_indexed,(W1 d, RR4 baser, RR4 index, IMM factor)) MIDFUNC(4,mov_l_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR4 s)) @@ -1116,7 +1096,6 @@ MIDFUNC(4,mov_l_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR4 s)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_l_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR4 s)) MIDFUNC(4,mov_w_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR2 s)) { @@ -1130,7 +1109,6 @@ MIDFUNC(4,mov_w_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR2 s)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_w_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR2 s)) MIDFUNC(4,mov_b_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR1 s)) { @@ -1144,7 +1122,6 @@ MIDFUNC(4,mov_b_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR1 s)) unlock2(baser); unlock2(index); } -MENDFUNC(4,mov_b_mrr_indexed,(RR4 baser, RR4 index, IMM factor, RR1 s)) MIDFUNC(5,mov_l_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR4 s)) @@ -1165,7 +1142,6 @@ MIDFUNC(5,mov_l_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR4 s) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_l_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR4 s)) MIDFUNC(5,mov_w_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR2 s)) { @@ -1185,7 +1161,6 @@ MIDFUNC(5,mov_w_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR2 s) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_w_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR2 s)) MIDFUNC(5,mov_b_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR1 s)) { @@ -1205,7 +1180,6 @@ MIDFUNC(5,mov_b_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR1 s) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_b_bmrr_indexed,(IMM base, RR4 baser, RR4 index, IMM factor, RR1 s)) @@ -1226,7 +1200,6 @@ MIDFUNC(5,mov_l_brrm_indexed,(W4 d, IMM base, RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_l_brrm_indexed,(W4 d, IMM base, RR4 baser, RR4 index, IMM factor)) MIDFUNC(5,mov_w_brrm_indexed,(W2 d, IMM base, RR4 baser, RR4 index, IMM factor)) @@ -1246,7 +1219,6 @@ MIDFUNC(5,mov_w_brrm_indexed,(W2 d, IMM base, RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_w_brrm_indexed,(W2 d, IMM base, RR4 baser, RR4 index, IMM factor)) MIDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, RR4 baser, RR4 index, IMM factor)) @@ -1266,7 +1238,6 @@ MIDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, RR4 baser, RR4 index, IMM factor)) unlock2(baser); unlock2(index); } -MENDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, RR4 baser, RR4 index, IMM factor)) /* Read a long from base+factor*index */ MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) @@ -1287,7 +1258,6 @@ MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) unlock2(index); unlock2(d); } -MENDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor)) /* read the long at the address contained in s+offset and store in d */ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) @@ -1304,7 +1274,6 @@ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) @@ -1321,7 +1290,6 @@ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_b_rR,(W1 d, RR4 s, IMM offset)) @@ -1338,7 +1306,6 @@ MIDFUNC(3,mov_b_rR,(W1 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_rR,(W1 d, RR4 s, IMM offset)) /* read the long at the address contained in s+offset and store in d */ MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) @@ -1357,7 +1324,6 @@ MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) @@ -1377,7 +1343,6 @@ MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset)) /* read the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) @@ -1397,7 +1362,6 @@ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset)) MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) { @@ -1413,7 +1377,6 @@ MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) raw_mov_l_Ri(d,i,offset); unlock2(d); } -MENDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset)) MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) { @@ -1429,7 +1392,6 @@ MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) raw_mov_w_Ri(d,i,offset); unlock2(d); } -MENDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset)) MIDFUNC(3,mov_b_Ri,(RR4 d, IMM i, IMM offset)) { @@ -1445,7 +1407,6 @@ MIDFUNC(3,mov_b_Ri,(RR4 d, IMM i, IMM offset)) raw_mov_b_Ri(d,i,offset); unlock2(d); } -MENDFUNC(3,mov_b_Ri,(RR4 d, IMM i, IMM offset)) /* Warning! OFFSET is byte sized only! */ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) @@ -1467,7 +1428,6 @@ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset)) MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) { @@ -1487,7 +1447,6 @@ MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset)) MIDFUNC(3,mov_b_Rr,(RR4 d, RR1 s, IMM offset)) { @@ -1507,7 +1466,6 @@ MIDFUNC(3,mov_b_Rr,(RR4 d, RR1 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_Rr,(RR4 d, RR1 s, IMM offset)) MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) { @@ -1528,7 +1486,6 @@ MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset)) MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) { @@ -1546,7 +1503,6 @@ MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) unlock2(index); unlock2(s); } -MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset)) MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) { @@ -1560,7 +1516,6 @@ MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) unlock2(index); unlock2(s); } -MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor)) /* write d to the long at the address contained in s+offset */ MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) @@ -1580,7 +1535,6 @@ MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset)) /* write the word at the address contained in s+offset and store in d */ MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) @@ -1600,7 +1554,6 @@ MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset)) MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) { @@ -1618,7 +1571,6 @@ MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) unlock2(d); unlock2(s); } -MENDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset)) MIDFUNC(1,mid_bswap_32,(RW4 r)) { @@ -1634,7 +1586,6 @@ MIDFUNC(1,mid_bswap_32,(RW4 r)) raw_bswap_32(r); unlock2(r); } -MENDFUNC(1,mid_bswap_32,(RW4 r)) MIDFUNC(1,mid_bswap_16,(RW2 r)) { @@ -1650,7 +1601,6 @@ MIDFUNC(1,mid_bswap_16,(RW2 r)) raw_bswap_16(r); unlock2(r); } -MENDFUNC(1,mid_bswap_16,(RW2 r)) @@ -1681,7 +1631,6 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s)) jit_log2("Added %d to nreg %d(%d), now holds %d regs", d,s,live.state[d].realind,live.nat[s].nholds); unlock2(s); } -MENDFUNC(2,mov_l_rr,(W4 d, RR4 s)) MIDFUNC(2,mov_l_mr,(IMM d, RR4 s)) { @@ -1695,7 +1644,6 @@ MIDFUNC(2,mov_l_mr,(IMM d, RR4 s)) raw_mov_l_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_l_mr,(IMM d, RR4 s)) MIDFUNC(2,mov_w_mr,(IMM d, RR2 s)) @@ -1710,7 +1658,6 @@ MIDFUNC(2,mov_w_mr,(IMM d, RR2 s)) raw_mov_w_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_w_mr,(IMM d, RR2 s)) MIDFUNC(2,mov_w_rm,(W2 d, IMM s)) { @@ -1720,7 +1667,6 @@ MIDFUNC(2,mov_w_rm,(W2 d, IMM s)) raw_mov_w_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_w_rm,(W2 d, IMM s)) MIDFUNC(2,mov_b_mr,(IMM d, RR1 s)) { @@ -1735,7 +1681,6 @@ MIDFUNC(2,mov_b_mr,(IMM d, RR1 s)) raw_mov_b_mr(d,s); unlock2(s); } -MENDFUNC(2,mov_b_mr,(IMM d, RR1 s)) MIDFUNC(2,mov_b_rm,(W1 d, IMM s)) { @@ -1745,14 +1690,12 @@ MIDFUNC(2,mov_b_rm,(W1 d, IMM s)) raw_mov_b_rm(d,s); unlock2(d); } -MENDFUNC(2,mov_b_rm,(W1 d, IMM s)) MIDFUNC(2,mov_l_ri,(W4 d, IMM s)) { set_const(d,s); return; } -MENDFUNC(2,mov_l_ri,(W4 d, IMM s)) MIDFUNC(2,mov_w_ri,(W2 d, IMM s)) { @@ -1762,7 +1705,6 @@ MIDFUNC(2,mov_w_ri,(W2 d, IMM s)) raw_mov_w_ri(d,s); unlock2(d); } -MENDFUNC(2,mov_w_ri,(W2 d, IMM s)) MIDFUNC(2,mov_b_ri,(W1 d, IMM s)) { @@ -1772,28 +1714,24 @@ MIDFUNC(2,mov_b_ri,(W1 d, IMM s)) raw_mov_b_ri(d,s); unlock2(d); } -MENDFUNC(2,mov_b_ri,(W1 d, IMM s)) MIDFUNC(2,add_l_mi,(IMM d, IMM s)) { CLOBBER_ADD; raw_add_l_mi(d,s) ; } -MENDFUNC(2,add_l_mi,(IMM d, IMM s)) MIDFUNC(2,add_w_mi,(IMM d, IMM s)) { CLOBBER_ADD; raw_add_w_mi(d,s) ; } -MENDFUNC(2,add_w_mi,(IMM d, IMM s)) MIDFUNC(2,add_b_mi,(IMM d, IMM s)) { CLOBBER_ADD; raw_add_b_mi(d,s) ; } -MENDFUNC(2,add_b_mi,(IMM d, IMM s)) MIDFUNC(2,test_l_ri,(RR4 d, IMM i)) { @@ -1803,7 +1741,6 @@ MIDFUNC(2,test_l_ri,(RR4 d, IMM i)) raw_test_l_ri(d,i); unlock2(d); } -MENDFUNC(2,test_l_ri,(RR4 d, IMM i)) MIDFUNC(2,test_l_rr,(RR4 d, RR4 s)) { @@ -1815,7 +1752,6 @@ MIDFUNC(2,test_l_rr,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_l_rr,(RR4 d, RR4 s)) MIDFUNC(2,test_w_rr,(RR2 d, RR2 s)) { @@ -1827,7 +1763,6 @@ MIDFUNC(2,test_w_rr,(RR2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_w_rr,(RR2 d, RR2 s)) MIDFUNC(2,test_b_rr,(RR1 d, RR1 s)) { @@ -1839,7 +1774,6 @@ MIDFUNC(2,test_b_rr,(RR1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,test_b_rr,(RR1 d, RR1 s)) MIDFUNC(2,and_l_ri,(RW4 d, IMM i)) @@ -1855,7 +1789,6 @@ MIDFUNC(2,and_l_ri,(RW4 d, IMM i)) raw_and_l_ri(d,i); unlock2(d); } -MENDFUNC(2,and_l_ri,(RW4 d, IMM i)) MIDFUNC(2,and_l,(RW4 d, RR4 s)) { @@ -1867,7 +1800,6 @@ MIDFUNC(2,and_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_l,(RW4 d, RR4 s)) MIDFUNC(2,and_w,(RW2 d, RR2 s)) { @@ -1879,7 +1811,6 @@ MIDFUNC(2,and_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_w,(RW2 d, RR2 s)) MIDFUNC(2,and_b,(RW1 d, RR1 s)) { @@ -1891,7 +1822,6 @@ MIDFUNC(2,and_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,and_b,(RW1 d, RR1 s)) // gb-- used for making an fpcr value in compemu_fpp.cpp MIDFUNC(2,or_l_rm,(RW4 d, IMM s)) @@ -1902,7 +1832,6 @@ MIDFUNC(2,or_l_rm,(RW4 d, IMM s)) raw_or_l_rm(d,s); unlock2(d); } -MENDFUNC(2,or_l_rm,(RW4 d, IMM s)) MIDFUNC(2,or_l_ri,(RW4 d, IMM i)) { @@ -1916,7 +1845,6 @@ MIDFUNC(2,or_l_ri,(RW4 d, IMM i)) raw_or_l_ri(d,i); unlock2(d); } -MENDFUNC(2,or_l_ri,(RW4 d, IMM i)) MIDFUNC(2,or_l,(RW4 d, RR4 s)) { @@ -1932,7 +1860,6 @@ MIDFUNC(2,or_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_l,(RW4 d, RR4 s)) MIDFUNC(2,or_w,(RW2 d, RR2 s)) { @@ -1944,7 +1871,6 @@ MIDFUNC(2,or_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_w,(RW2 d, RR2 s)) MIDFUNC(2,or_b,(RW1 d, RR1 s)) { @@ -1956,7 +1882,6 @@ MIDFUNC(2,or_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,or_b,(RW1 d, RR1 s)) MIDFUNC(2,adc_l,(RW4 d, RR4 s)) { @@ -1969,7 +1894,6 @@ MIDFUNC(2,adc_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_l,(RW4 d, RR4 s)) MIDFUNC(2,adc_w,(RW2 d, RR2 s)) { @@ -1981,7 +1905,6 @@ MIDFUNC(2,adc_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_w,(RW2 d, RR2 s)) MIDFUNC(2,adc_b,(RW1 d, RR1 s)) { @@ -1993,7 +1916,6 @@ MIDFUNC(2,adc_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,adc_b,(RW1 d, RR1 s)) MIDFUNC(2,add_l,(RW4 d, RR4 s)) { @@ -2011,7 +1933,6 @@ MIDFUNC(2,add_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_l,(RW4 d, RR4 s)) MIDFUNC(2,add_w,(RW2 d, RR2 s)) { @@ -2028,7 +1949,6 @@ MIDFUNC(2,add_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_w,(RW2 d, RR2 s)) MIDFUNC(2,add_b,(RW1 d, RR1 s)) { @@ -2045,7 +1965,6 @@ MIDFUNC(2,add_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,add_b,(RW1 d, RR1 s)) MIDFUNC(2,sub_l_ri,(RW4 d, IMM i)) { @@ -2068,7 +1987,6 @@ MIDFUNC(2,sub_l_ri,(RW4 d, IMM i)) raw_sub_l_ri(d,i); unlock2(d); } -MENDFUNC(2,sub_l_ri,(RW4 d, IMM i)) MIDFUNC(2,sub_w_ri,(RW2 d, IMM i)) { @@ -2081,7 +1999,6 @@ MIDFUNC(2,sub_w_ri,(RW2 d, IMM i)) raw_sub_w_ri(d,i); unlock2(d); } -MENDFUNC(2,sub_w_ri,(RW2 d, IMM i)) MIDFUNC(2,sub_b_ri,(RW1 d, IMM i)) { @@ -2095,7 +2012,6 @@ MIDFUNC(2,sub_b_ri,(RW1 d, IMM i)) unlock2(d); } -MENDFUNC(2,sub_b_ri,(RW1 d, IMM i)) MIDFUNC(2,add_l_ri,(RW4 d, IMM i)) { @@ -2116,7 +2032,6 @@ MIDFUNC(2,add_l_ri,(RW4 d, IMM i)) raw_add_l_ri(d,i); unlock2(d); } -MENDFUNC(2,add_l_ri,(RW4 d, IMM i)) MIDFUNC(2,add_w_ri,(RW2 d, IMM i)) { @@ -2129,7 +2044,6 @@ MIDFUNC(2,add_w_ri,(RW2 d, IMM i)) raw_add_w_ri(d,i); unlock2(d); } -MENDFUNC(2,add_w_ri,(RW2 d, IMM i)) MIDFUNC(2,add_b_ri,(RW1 d, IMM i)) { @@ -2143,7 +2057,6 @@ MIDFUNC(2,add_b_ri,(RW1 d, IMM i)) unlock2(d); } -MENDFUNC(2,add_b_ri,(RW1 d, IMM i)) MIDFUNC(2,sbb_l,(RW4 d, RR4 s)) { @@ -2155,7 +2068,6 @@ MIDFUNC(2,sbb_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_l,(RW4 d, RR4 s)) MIDFUNC(2,sbb_w,(RW2 d, RR2 s)) { @@ -2167,7 +2079,6 @@ MIDFUNC(2,sbb_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_w,(RW2 d, RR2 s)) MIDFUNC(2,sbb_b,(RW1 d, RR1 s)) { @@ -2179,7 +2090,6 @@ MIDFUNC(2,sbb_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sbb_b,(RW1 d, RR1 s)) MIDFUNC(2,sub_l,(RW4 d, RR4 s)) { @@ -2196,7 +2106,6 @@ MIDFUNC(2,sub_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_l,(RW4 d, RR4 s)) MIDFUNC(2,sub_w,(RW2 d, RR2 s)) { @@ -2213,7 +2122,6 @@ MIDFUNC(2,sub_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_w,(RW2 d, RR2 s)) MIDFUNC(2,sub_b,(RW1 d, RR1 s)) { @@ -2230,7 +2138,6 @@ MIDFUNC(2,sub_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,sub_b,(RW1 d, RR1 s)) MIDFUNC(2,cmp_l,(RR4 d, RR4 s)) { @@ -2242,7 +2149,6 @@ MIDFUNC(2,cmp_l,(RR4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_l,(RR4 d, RR4 s)) MIDFUNC(2,cmp_l_ri,(RR4 r, IMM i)) { @@ -2252,7 +2158,6 @@ MIDFUNC(2,cmp_l_ri,(RR4 r, IMM i)) raw_cmp_l_ri(r,i); unlock2(r); } -MENDFUNC(2,cmp_l_ri,(RR4 r, IMM i)) MIDFUNC(2,cmp_w,(RR2 d, RR2 s)) { @@ -2264,7 +2169,6 @@ MIDFUNC(2,cmp_w,(RR2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_w,(RR2 d, RR2 s)) MIDFUNC(2,cmp_b,(RR1 d, RR1 s)) { @@ -2276,7 +2180,6 @@ MIDFUNC(2,cmp_b,(RR1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,cmp_b,(RR1 d, RR1 s)) MIDFUNC(2,xor_l,(RW4 d, RR4 s)) @@ -2289,7 +2192,6 @@ MIDFUNC(2,xor_l,(RW4 d, RR4 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_l,(RW4 d, RR4 s)) MIDFUNC(2,xor_w,(RW2 d, RR2 s)) { @@ -2301,7 +2203,6 @@ MIDFUNC(2,xor_w,(RW2 d, RR2 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_w,(RW2 d, RR2 s)) MIDFUNC(2,xor_b,(RW1 d, RR1 s)) { @@ -2313,7 +2214,6 @@ MIDFUNC(2,xor_b,(RW1 d, RR1 s)) unlock2(d); unlock2(s); } -MENDFUNC(2,xor_b,(RW1 d, RR1 s)) MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) { @@ -2360,7 +2260,6 @@ MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) live.state[out1].dirtysize=osize; set_status(out1,DIRTY); } -MENDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize)) MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) { @@ -2387,7 +2286,6 @@ MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) raw_inc_sp(8); #endif } -MENDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2)) /* forget_about() takes a mid-layer register */ MIDFUNC(1,forget_about,(W4 r)) @@ -2397,13 +2295,11 @@ MIDFUNC(1,forget_about,(W4 r)) live.state[r].val=0; set_status(r,UNDEF); } -MENDFUNC(1,forget_about,(W4 r)) MIDFUNC(0,nop,(void)) { raw_emit_nop(); } -MENDFUNC(0,nop,(void)) MIDFUNC(1,f_forget_about,(FW r)) { @@ -2411,7 +2307,6 @@ MIDFUNC(1,f_forget_about,(FW r)) f_disassociate(r); live.fate[r].status=UNDEF; } -MENDFUNC(1,f_forget_about,(FW r)) MIDFUNC(1,fmov_pi,(FW r)) { @@ -2419,7 +2314,6 @@ MIDFUNC(1,fmov_pi,(FW r)) raw_fmov_pi(r); f_unlock(r); } -MENDFUNC(1,fmov_pi,(FW r)) MIDFUNC(1,fmov_log10_2,(FW r)) { @@ -2427,7 +2321,6 @@ MIDFUNC(1,fmov_log10_2,(FW r)) raw_fmov_log10_2(r); f_unlock(r); } -MENDFUNC(1,fmov_log10_2,(FW r)) MIDFUNC(1,fmov_log2_e,(FW r)) { @@ -2435,7 +2328,6 @@ MIDFUNC(1,fmov_log2_e,(FW r)) raw_fmov_log2_e(r); f_unlock(r); } -MENDFUNC(1,fmov_log2_e,(FW r)) MIDFUNC(1,fmov_loge_2,(FW r)) { @@ -2443,7 +2335,6 @@ MIDFUNC(1,fmov_loge_2,(FW r)) raw_fmov_loge_2(r); f_unlock(r); } -MENDFUNC(1,fmov_loge_2,(FW r)) MIDFUNC(1,fmov_1,(FW r)) { @@ -2451,7 +2342,6 @@ MIDFUNC(1,fmov_1,(FW r)) raw_fmov_1(r); f_unlock(r); } -MENDFUNC(1,fmov_1,(FW r)) MIDFUNC(1,fmov_0,(FW r)) { @@ -2459,55 +2349,48 @@ MIDFUNC(1,fmov_0,(FW r)) raw_fmov_0(r); f_unlock(r); } -MENDFUNC(1,fmov_0,(FW r)) -MIDFUNC(2,fmov_rm,(FW r, MEMR m)) +MIDFUNC(2,fmov_rm,(FW r, MEMPTRR m)) { r=f_writereg(r); raw_fmov_rm(r,m); f_unlock(r); } -MENDFUNC(2,fmov_rm,(FW r, MEMR m)) -MIDFUNC(2,fmovi_rm,(FW r, MEMR m)) +MIDFUNC(2,fmovi_rm,(FW r, MEMPTRR m)) { r=f_writereg(r); raw_fmovi_rm(r,m); f_unlock(r); } -MENDFUNC(2,fmovi_rm,(FW r, MEMR m)) -MIDFUNC(2,fmovi_mr,(MEMW m, FR r)) +MIDFUNC(2,fmovi_mr,(MEMPTRW m, FR r)) { r=f_readreg(r); raw_fmovi_mr(m,r); f_unlock(r); } -MENDFUNC(2,fmovi_mr,(MEMW m, FR r)) -MIDFUNC(3,fmovi_mrb,(MEMW m, FR r, double *bounds)) +MIDFUNC(3,fmovi_mrb,(MEMPTRW m, FR r, double *bounds)) { r=f_readreg(r); raw_fmovi_mrb(m,r,bounds); f_unlock(r); } -MENDFUNC(3,fmovi_mrb,(MEMW m, FR r, double *bounds)) -MIDFUNC(2,fmovs_rm,(FW r, MEMR m)) +MIDFUNC(2,fmovs_rm,(FW r, MEMPTRR m)) { r=f_writereg(r); raw_fmovs_rm(r,m); f_unlock(r); } -MENDFUNC(2,fmovs_rm,(FW r, MEMR m)) -MIDFUNC(2,fmovs_mr,(MEMW m, FR r)) +MIDFUNC(2,fmovs_mr,(MEMPTRW m, FR r)) { r=f_readreg(r); raw_fmovs_mr(m,r); f_unlock(r); } -MENDFUNC(2,fmovs_mr,(MEMW m, FR r)) MIDFUNC(1,fcuts_r,(FRW r)) { @@ -2515,7 +2398,6 @@ MIDFUNC(1,fcuts_r,(FRW r)) raw_fcuts_r(r); f_unlock(r); } -MENDFUNC(1,fcuts_r,(FRW r)) MIDFUNC(1,fcut_r,(FRW r)) { @@ -2523,31 +2405,27 @@ MIDFUNC(1,fcut_r,(FRW r)) raw_fcut_r(r); f_unlock(r); } -MENDFUNC(1,fcut_r,(FRW r)) -MIDFUNC(2,fmov_ext_mr,(MEMW m, FR r)) +MIDFUNC(2,fmov_ext_mr,(MEMPTRW m, FR r)) { r=f_readreg(r); raw_fmov_ext_mr(m,r); f_unlock(r); } -MENDFUNC(2,fmov_ext_mr,(MEMW m, FR r)) -MIDFUNC(2,fmov_mr,(MEMW m, FR r)) +MIDFUNC(2,fmov_mr,(MEMPTRW m, FR r)) { r=f_readreg(r); raw_fmov_mr(m,r); f_unlock(r); } -MENDFUNC(2,fmov_mr,(MEMW m, FR r)) -MIDFUNC(2,fmov_ext_rm,(FW r, MEMR m)) +MIDFUNC(2,fmov_ext_rm,(FW r, MEMPTRR m)) { r=f_writereg(r); raw_fmov_ext_rm(r,m); f_unlock(r); } -MENDFUNC(2,fmov_ext_rm,(FW r, MEMR m)) MIDFUNC(2,fmov_rr,(FW d, FR s)) { @@ -2571,7 +2449,6 @@ MIDFUNC(2,fmov_rr,(FW d, FR s)) f_unlock(d); #endif } -MENDFUNC(2,fmov_rr,(FW d, FR s)) MIDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base)) { @@ -2580,7 +2457,6 @@ MIDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base)) raw_fldcw_m_indexed(index,base); unlock2(index); } -MENDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base)) MIDFUNC(1,ftst_r,(FR r)) { @@ -2588,13 +2464,11 @@ MIDFUNC(1,ftst_r,(FR r)) raw_ftst_r(r); f_unlock(r); } -MENDFUNC(1,ftst_r,(FR r)) MIDFUNC(0,dont_care_fflags,(void)) { f_disassociate(FP_RESULT); } -MENDFUNC(0,dont_care_fflags,(void)) MIDFUNC(2,fsqrt_rr,(FW d, FR s)) { @@ -2604,7 +2478,6 @@ MIDFUNC(2,fsqrt_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fsqrt_rr,(FW d, FR s)) MIDFUNC(2,fabs_rr,(FW d, FR s)) { @@ -2614,7 +2487,6 @@ MIDFUNC(2,fabs_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fabs_rr,(FW d, FR s)) MIDFUNC(2,fgetexp_rr,(FW d, FR s)) { @@ -2624,7 +2496,6 @@ MIDFUNC(2,fgetexp_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fgetexp_rr,(FW d, FR s)) MIDFUNC(2,fgetman_rr,(FW d, FR s)) { @@ -2634,7 +2505,6 @@ MIDFUNC(2,fgetman_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fgetman_rr,(FW d, FR s)) MIDFUNC(2,fsin_rr,(FW d, FR s)) { @@ -2644,7 +2514,6 @@ MIDFUNC(2,fsin_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fsin_rr,(FW d, FR s)) MIDFUNC(2,fcos_rr,(FW d, FR s)) { @@ -2654,7 +2523,6 @@ MIDFUNC(2,fcos_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fcos_rr,(FW d, FR s)) MIDFUNC(2,ftan_rr,(FW d, FR s)) { @@ -2664,7 +2532,6 @@ MIDFUNC(2,ftan_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,ftan_rr,(FW d, FR s)) MIDFUNC(3,fsincos_rr,(FW d, FW c, FR s)) { @@ -2676,7 +2543,6 @@ MIDFUNC(3,fsincos_rr,(FW d, FW c, FR s)) f_unlock(d); f_unlock(c); } -MENDFUNC(3,fsincos_rr,(FW d, FW c, FR s)) MIDFUNC(2,fscale_rr,(FRW d, FR s)) { @@ -2686,7 +2552,6 @@ MIDFUNC(2,fscale_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fscale_rr,(FRW d, FR s)) MIDFUNC(2,ftwotox_rr,(FW d, FR s)) { @@ -2696,7 +2561,6 @@ MIDFUNC(2,ftwotox_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,ftwotox_rr,(FW d, FR s)) MIDFUNC(2,fetox_rr,(FW d, FR s)) { @@ -2706,7 +2570,6 @@ MIDFUNC(2,fetox_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fetox_rr,(FW d, FR s)) MIDFUNC(2,frndint_rr,(FW d, FR s)) { @@ -2716,7 +2579,6 @@ MIDFUNC(2,frndint_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,frndint_rr,(FW d, FR s)) MIDFUNC(2,fetoxM1_rr,(FW d, FR s)) { @@ -2726,7 +2588,6 @@ MIDFUNC(2,fetoxM1_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fetoxM1_rr,(FW d, FR s)) MIDFUNC(2,ftentox_rr,(FW d, FR s)) { @@ -2736,7 +2597,6 @@ MIDFUNC(2,ftentox_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,ftentox_rr,(FW d, FR s)) MIDFUNC(2,flog2_rr,(FW d, FR s)) { @@ -2746,7 +2606,6 @@ MIDFUNC(2,flog2_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,flog2_rr,(FW d, FR s)) MIDFUNC(2,flogN_rr,(FW d, FR s)) { @@ -2756,7 +2615,6 @@ MIDFUNC(2,flogN_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,flogN_rr,(FW d, FR s)) MIDFUNC(2,flogNP1_rr,(FW d, FR s)) { @@ -2766,7 +2624,6 @@ MIDFUNC(2,flogNP1_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,flogNP1_rr,(FW d, FR s)) MIDFUNC(2,flog10_rr,(FW d, FR s)) { @@ -2776,7 +2633,6 @@ MIDFUNC(2,flog10_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,flog10_rr,(FW d, FR s)) MIDFUNC(2,fasin_rr,(FW d, FR s)) { @@ -2786,7 +2642,6 @@ MIDFUNC(2,fasin_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fasin_rr,(FW d, FR s)) MIDFUNC(2,facos_rr,(FW d, FR s)) { @@ -2796,7 +2651,6 @@ MIDFUNC(2,facos_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,facos_rr,(FW d, FR s)) MIDFUNC(2,fatan_rr,(FW d, FR s)) { @@ -2806,7 +2660,6 @@ MIDFUNC(2,fatan_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fatan_rr,(FW d, FR s)) MIDFUNC(2,fatanh_rr,(FW d, FR s)) { @@ -2816,7 +2669,6 @@ MIDFUNC(2,fatanh_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fatanh_rr,(FW d, FR s)) MIDFUNC(2,fsinh_rr,(FW d, FR s)) { @@ -2826,7 +2678,6 @@ MIDFUNC(2,fsinh_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fsinh_rr,(FW d, FR s)) MIDFUNC(2,fcosh_rr,(FW d, FR s)) { @@ -2836,7 +2687,6 @@ MIDFUNC(2,fcosh_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fcosh_rr,(FW d, FR s)) MIDFUNC(2,ftanh_rr,(FW d, FR s)) { @@ -2846,7 +2696,6 @@ MIDFUNC(2,ftanh_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,ftanh_rr,(FW d, FR s)) MIDFUNC(2,fneg_rr,(FW d, FR s)) { @@ -2856,7 +2705,6 @@ MIDFUNC(2,fneg_rr,(FW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fneg_rr,(FW d, FR s)) MIDFUNC(2,fadd_rr,(FRW d, FR s)) { @@ -2866,7 +2714,6 @@ MIDFUNC(2,fadd_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fadd_rr,(FRW d, FR s)) MIDFUNC(2,fsub_rr,(FRW d, FR s)) { @@ -2876,7 +2723,6 @@ MIDFUNC(2,fsub_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fsub_rr,(FRW d, FR s)) MIDFUNC(2,fcmp_rr,(FR d, FR s)) { @@ -2886,7 +2732,6 @@ MIDFUNC(2,fcmp_rr,(FR d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fcmp_rr,(FR d, FR s)) MIDFUNC(2,fdiv_rr,(FRW d, FR s)) { @@ -2896,7 +2741,6 @@ MIDFUNC(2,fdiv_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fdiv_rr,(FRW d, FR s)) MIDFUNC(2,frem_rr,(FRW d, FR s)) { @@ -2906,7 +2750,6 @@ MIDFUNC(2,frem_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,frem_rr,(FRW d, FR s)) MIDFUNC(2,frem1_rr,(FRW d, FR s)) { @@ -2916,7 +2759,6 @@ MIDFUNC(2,frem1_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,frem1_rr,(FRW d, FR s)) MIDFUNC(2,fmul_rr,(FRW d, FR s)) { @@ -2926,7 +2768,6 @@ MIDFUNC(2,fmul_rr,(FRW d, FR s)) f_unlock(s); f_unlock(d); } -MENDFUNC(2,fmul_rr,(FRW d, FR s)) #ifdef __GNUC__ diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.h b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.h index a0f5cf92..8476d947 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.h +++ b/BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.h @@ -185,6 +185,7 @@ DECLARE_MIDFUNC(xor_b(RW1 d, RR1 s)); DECLARE_MIDFUNC(live_flags(void)); DECLARE_MIDFUNC(dont_care_flags(void)); DECLARE_MIDFUNC(duplicate_carry(void)); +DECLARE_MIDFUNC(setcc_for_cntzero(RR4 d, RR4 data, int size)); DECLARE_MIDFUNC(restore_carry(void)); DECLARE_MIDFUNC(start_needflags(void)); DECLARE_MIDFUNC(end_needflags(void)); @@ -201,17 +202,17 @@ DECLARE_MIDFUNC(fmov_log2_e(FW r)); DECLARE_MIDFUNC(fmov_loge_2(FW r)); DECLARE_MIDFUNC(fmov_1(FW r)); DECLARE_MIDFUNC(fmov_0(FW r)); -DECLARE_MIDFUNC(fmov_rm(FW r, MEMR m)); -DECLARE_MIDFUNC(fmov_mr(MEMW m, FR r)); -DECLARE_MIDFUNC(fmovi_rm(FW r, MEMR m)); -DECLARE_MIDFUNC(fmovi_mr(MEMW m, FR r)); -DECLARE_MIDFUNC(fmovi_mrb(MEMW m, FR r, double *bounds)); -DECLARE_MIDFUNC(fmovs_rm(FW r, MEMR m)); -DECLARE_MIDFUNC(fmovs_mr(MEMW m, FR r)); +DECLARE_MIDFUNC(fmov_rm(FW r, MEMPTRR m)); +DECLARE_MIDFUNC(fmov_mr(MEMPTRW m, FR r)); +DECLARE_MIDFUNC(fmovi_rm(FW r, MEMPTRR m)); +DECLARE_MIDFUNC(fmovi_mr(MEMPTRW m, FR r)); +DECLARE_MIDFUNC(fmovi_mrb(MEMPTRW m, FR r, double *bounds)); +DECLARE_MIDFUNC(fmovs_rm(FW r, MEMPTRR m)); +DECLARE_MIDFUNC(fmovs_mr(MEMPTRW m, FR r)); DECLARE_MIDFUNC(fcuts_r(FRW r)); DECLARE_MIDFUNC(fcut_r(FRW r)); -DECLARE_MIDFUNC(fmov_ext_mr(MEMW m, FR r)); -DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMR m)); +DECLARE_MIDFUNC(fmov_ext_mr(MEMPTRW m, FR r)); +DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMPTRR m)); DECLARE_MIDFUNC(fmov_rr(FW d, FR s)); DECLARE_MIDFUNC(fldcw_m_indexed(RR4 index, IMM base)); DECLARE_MIDFUNC(ftst_r(FR r)); diff --git a/BasiliskII/src/uae_cpu/compiler/compemu_support.cpp b/BasiliskII/src/uae_cpu/compiler/compemu_support.cpp index 068123b8..9b178c0f 100644 --- a/BasiliskII/src/uae_cpu/compiler/compemu_support.cpp +++ b/BasiliskII/src/uae_cpu/compiler/compemu_support.cpp @@ -43,12 +43,6 @@ #error "Only [LS]AHF scheme to [gs]et flags is supported with the JIT Compiler" #endif -//TODO: detect i386 and arm platforms - -#ifdef __x86_64__ -#define CPU_x86_64 1 -#endif - /* NOTE: support for AMD64 assumes translation cache and other code * buffers are allocated into a 32-bit address space because (i) B2/JIT * code is not 64-bit clean and (ii) it's faster to resolve branches @@ -72,7 +66,7 @@ #ifdef UAE #include "options.h" #include "events.h" -#include "memory.h" +#include "uae/memory.h" #include "custom.h" #else #include "cpu_emulation.h" @@ -88,11 +82,15 @@ #include "comptbl.h" #ifdef UAE #include "compemu.h" +#ifdef FSUAE +#include "codegen_udis86.h" +#endif #else #include "compiler/compemu.h" #include "fpu/fpu.h" #include "fpu/flags.h" // #include "parameters.h" +static void build_comp(void); #endif // #include "verify.h" @@ -100,10 +98,16 @@ // uae_log("JIT: " format "\n", ##__VA_ARGS__); #define D2 D - #ifdef UAE +#ifdef FSUAE +#include "uae/fs.h" +#endif #include "uae/log.h" +#if defined(__pie__) || defined (__PIE__) +#error Position-independent code (PIE) cannot be used with JIT +#endif + #include "uae/vm.h" #define VM_PAGE_READ UAE_VM_READ #define VM_PAGE_WRITE UAE_VM_WRITE @@ -149,6 +153,15 @@ static inline int distrust_check(int value) return 1; #else int distrust = value; +#ifdef FSUAE + switch (value) { + case 0: distrust = 0; break; + case 1: distrust = 1; break; + case 2: distrust = ((start_pc & 0xF80000) == 0xF80000); break; + case 3: distrust = !have_done_picasso; break; + default: abort(); + } +#endif return distrust; #endif } @@ -237,7 +250,7 @@ static clock_t emul_end_time = 0; #endif #ifdef PROFILE_UNTRANSLATED_INSNS -static const int untranslated_top_ten = 20; +static const int untranslated_top_ten = 50; static uae_u32 raw_cputbl_count[65536] = { 0, }; static uae_u16 opcode_nums[65536]; @@ -266,8 +279,10 @@ extern bool quit_program; // gb-- Extra data for Basilisk II/JIT #ifdef JIT_DEBUG static bool JITDebug = false; // Enable runtime disassemblers through mon? +// #define JITDebug bx_options.jit.jitdebug // Enable runtime disassemblers through mon? #else const bool JITDebug = false; +// #define JITDebug false // Don't use JIT debug mode at all #endif #if USE_INLINING #ifdef UAE @@ -283,6 +298,7 @@ const uae_u32 MIN_CACHE_SIZE = 1024; // Minimal translation cache size (1 MB) static uae_u32 cache_size = 0; // Size of total cache allocated for compiled blocks static uae_u32 current_cache_size = 0; // Cache grows upwards: how much has been consumed already static bool lazy_flush = true; // Flag: lazy translation cache invalidation +// Flag: compile FPU instructions ? #ifdef UAE #ifdef USE_JIT_FPU #define avoid_fpu (!currprefs.compfpu) @@ -291,6 +307,11 @@ static bool lazy_flush = true; // Flag: lazy translation cache invalidation #endif #else static bool avoid_fpu = true; // Flag: compile FPU instructions ? +// #ifdef USE_JIT_FPU +// #define avoid_fpu (!bx_options.jit.jitfpu) +// #else +// #define avoid_fpu (true) +// #endif #endif static bool have_cmov = false; // target has CMOV instructions ? static bool have_rat_stall = true; // target has partial register stalls ? @@ -370,10 +391,9 @@ static uintptr taken_pc_p; static int branch_cc; static int redo_current_block; +#ifdef UAE int segvcount=0; -int soft_flush_count=0; -int hard_flush_count=0; -int checksum_count=0; +#endif static uae_u8* current_compile_p=NULL; static uae_u8* max_compile_start; static uae_u8* compiled_code=NULL; @@ -395,7 +415,7 @@ static void* popall_check_checksum=NULL; * lists that we maintain for each hash result. */ static cacheline cache_tags[TAGSIZE]; -int letit=0; +static int cache_enabled=0; static blockinfo* hold_bi[MAX_HOLD_BI]; static blockinfo* active; static blockinfo* dormant; @@ -420,12 +440,10 @@ extern const struct cputbl op_smalltbl_4_nf[]; extern const struct cputbl op_smalltbl_5_nf[]; #endif -#ifdef WINUAE_ARANYM -static void flush_icache_hard(int n); -static void flush_icache_lazy(int n); -static void flush_icache_none(int n); -void (*flush_icache)(int n) = flush_icache_none; -#endif +static void flush_icache_hard(void); +static void flush_icache_lazy(void); +static void flush_icache_none(void); +void (*flush_icache)(void) = flush_icache_none; static bigstate live; static smallstate empty_ss; @@ -452,7 +470,7 @@ uae_u32 m68k_pc_offset; * side effects they would have on the flags are not important. This * variable indicates whether we need the side effects or not */ -uae_u32 needflags=0; +static uae_u32 needflags=0; /* Flag handling is complicated. * @@ -500,7 +518,7 @@ static inline blockinfo* get_blockinfo_addr(void* addr) /******************************************************************* * Disassembler support * *******************************************************************/ - + #define TARGET_M68K 0 #define TARGET_POWERPC 1 #define TARGET_X86 2 @@ -531,11 +549,11 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length) #if defined(HAVE_DISASM_M68K) { char buf[256]; - + disasm_info.memory_vma = ((memptr)((uintptr_t)(start) - MEMBaseDiff)); while (length > 0) { - int isize = m68k_disasm_to_buf(&disasm_info, buf); + int isize = m68k_disasm_to_buf(&disasm_info, buf, 1); bug("%s", buf); if (isize < 0) break; @@ -552,10 +570,10 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length) { const uint8 *end = start + length; char buf[256]; - + while (start < end) { - start = x86_disasm(start, buf); + start = x86_disasm(start, buf, 1); bug("%s", buf); } } @@ -566,10 +584,10 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length) { const uint8 *end = start + length; char buf[256]; - + while (start < end) { - start = arm_disasm(start, buf); + start = arm_disasm(start, buf, 1); bug("%s", buf); } } @@ -2640,8 +2658,10 @@ static scratch_t scratch; * Support functions exposed to newcpu * ********************************************************************/ -#define str_on_off(b) b ? "on" : "off" - +static inline const char *str_on_off(bool b) +{ + return b ? "on" : "off"; +} #ifdef UAE static @@ -2673,8 +2693,6 @@ void compiler_init(void) cache_size = PrefsFindInt32("jitcachesize"); jit_log(" : requested translation cache size : %d KB", cache_size); - // Initialize target CPU (check for features, e.g. CMOV, rat stalls) - raw_init_cpu(); setzflg_uses_bsf = target_check_bsf(); jit_log(" : target processor has CMOV instructions : %s", have_cmov ? "yes" : "no"); jit_log(" : target processor can suffer from partial register stalls : %s", have_rat_stall ? "yes" : "no"); @@ -2700,6 +2718,8 @@ void compiler_init(void) jit_log(" : separate blockinfo allocation : %s", str_on_off(USE_SEPARATE_BIA)); // Build compiler tables + read_table68k(); + do_merges(); build_comp(); #endif @@ -2728,7 +2748,7 @@ void compiler_exit(void) #else #if DEBUG #if defined(USE_DATA_BUFFER) - jit_log("data_wasted = %d bytes", data_wasted); + jit_log("data_wasted = %ld bytes", data_wasted); #endif #endif @@ -2759,7 +2779,7 @@ void compiler_exit(void) opcode_nums[i] = i; untranslated_count += raw_cputbl_count[i]; } - jit_log("Sorting out untranslated instructions count..."); + bug("Sorting out untranslated instructions count..."); qsort(opcode_nums, 65536, sizeof(uae_u16), untranslated_compfn); jit_log("Rank Opc Count Name"); for (int i = 0; i < untranslated_top_ten; i++) { @@ -2771,7 +2791,7 @@ void compiler_exit(void) dp = table68k + opcode_nums[i]; for (lookup = lookuptab; lookup->mnemo != (instrmnem)dp->mnemo; lookup++) ; - jit_log("%03d: %04x %10u %s", i, opcode_nums[i], count, lookup->name); + bug("%03d: %04x %10u %s", i, opcode_nums[i], count, lookup->name); } #endif @@ -2793,6 +2813,8 @@ void compiler_exit(void) 100.0*double(cum_reg_count)/double(tot_reg_count)); } #endif + + // exit_table68k(); } #ifdef UAE @@ -2813,7 +2835,7 @@ bool compiler_use_jit(void) } #endif -void init_comp(void) +static void init_comp(void) { int i; uae_s8* cb=can_byte; @@ -3015,14 +3037,18 @@ static void flush_keepflags(void) } #endif -void freescratch(void) +static void freescratch(void) { int i; for (i=0;i= CODE_ALLOC_MAX_ATTEMPTS) - return NULL; - - return do_alloc_code(size, depth + 1); -#else UNUSED(depth); uint8 *code = (uint8 *)vm_acquire(size, VM_MAP_DEFAULT | VM_MAP_32BIT); return code == VM_MAP_FAILED ? NULL : code; -#endif } static inline uint8 *alloc_code(uint32 size) @@ -3559,7 +3540,7 @@ static inline uint8 *alloc_code(uint32 size) void alloc_cache(void) { if (compiled_code) { - flush_icache_hard(6); + flush_icache_hard(); vm_release(compiled_code, cache_size * 1024); compiled_code = 0; } @@ -3719,8 +3700,6 @@ static inline int block_check_checksum(blockinfo* bi) if (bi->status!=BI_NEED_CHECK) return 1; /* This block is in a checked state */ - checksum_count++; - if (bi->c1 || bi->c2) calc_checksum(bi,&c1,&c2); else { @@ -3885,7 +3864,10 @@ static inline void create_popalls(void) r=REG_PC_TMP; compemu_raw_mov_l_rm(r, uae_p32(®s.pc_p)); compemu_raw_and_l_ri(r,TAGMASK); - assert(sizeof(cache_tags[0]) == sizeof(void *)); + { + assert(sizeof(cache_tags[0]) == sizeof(void *)); + // verify(sizeof(cache_tags[0]) == sizeof(void *)); + } compemu_raw_jmp_m_indexed(uae_p32(cache_tags), r, sizeof(void *)); /* now the exit points */ @@ -4020,12 +4002,98 @@ static int read_opcode(const char *p) return opcode; } + +#ifdef USE_JIT_FPU +static struct { + const char *name; + bool *const disabled; +} const jit_opcodes[] = { + { "fbcc", &jit_disable.fbcc }, + { "fdbcc", &jit_disable.fdbcc }, + { "fscc", &jit_disable.fscc }, + { "ftrapcc", &jit_disable.ftrapcc }, + { "fsave", &jit_disable.fsave }, + { "frestore", &jit_disable.frestore }, + { "fmove", &jit_disable.fmove }, + { "fmovec", &jit_disable.fmovec }, + { "fmovem", &jit_disable.fmovem }, + { "fmovecr", &jit_disable.fmovecr }, + { "fint", &jit_disable.fint }, + { "fsinh", &jit_disable.fsinh }, + { "fintrz", &jit_disable.fintrz }, + { "fsqrt", &jit_disable.fsqrt }, + { "flognp1", &jit_disable.flognp1 }, + { "fetoxm1", &jit_disable.fetoxm1 }, + { "ftanh", &jit_disable.ftanh }, + { "fatan", &jit_disable.fatan }, + { "fasin", &jit_disable.fasin }, + { "fatanh", &jit_disable.fatanh }, + { "fsin", &jit_disable.fsin }, + { "ftan", &jit_disable.ftan }, + { "fetox", &jit_disable.fetox }, + { "ftwotox", &jit_disable.ftwotox }, + { "ftentox", &jit_disable.ftentox }, + { "flogn", &jit_disable.flogn }, + { "flog10", &jit_disable.flog10 }, + { "flog2", &jit_disable.flog2 }, + { "fabs", &jit_disable.fabs }, + { "fcosh", &jit_disable.fcosh }, + { "fneg", &jit_disable.fneg }, + { "facos", &jit_disable.facos }, + { "fcos", &jit_disable.fcos }, + { "fgetexp", &jit_disable.fgetexp }, + { "fgetman", &jit_disable.fgetman }, + { "fdiv", &jit_disable.fdiv }, + { "fmod", &jit_disable.fmod }, + { "fadd", &jit_disable.fadd }, + { "fmul", &jit_disable.fmul }, + { "fsgldiv", &jit_disable.fsgldiv }, + { "frem", &jit_disable.frem }, + { "fscale", &jit_disable.fscale }, + { "fsglmul", &jit_disable.fsglmul }, + { "fsub", &jit_disable.fsub }, + { "fsincos", &jit_disable.fsincos }, + { "fcmp", &jit_disable.fcmp }, + { "ftst", &jit_disable.ftst }, +}; + +static bool read_fpu_opcode(const char **pp) +{ + const char *p = *pp; + const char *end; + size_t len; + unsigned int i; + + end = p; + while (*end != '\0' && *end != ',') + end++; + len = end - p; + if (*end != '\0') + end++; + for (i = 0; i < (sizeof(jit_opcodes) / sizeof(jit_opcodes[0])); i++) + { + if (len == strlen(jit_opcodes[i].name) && strncasecmp(jit_opcodes[i].name, p, len) == 0) + { + *jit_opcodes[i].disabled = true; + jit_log(" : disabled %s", jit_opcodes[i].name); + *pp = end; + return true; + } + } + return false; +} +#endif + static bool merge_blacklist() { #ifdef UAE const char *blacklist = ""; #else const char *blacklist = PrefsFindString("jitblacklist"); +#endif +#ifdef USE_JIT_FPU + for (unsigned int i = 0; i < (sizeof(jit_opcodes) / sizeof(jit_opcodes[0])); i++) + *jit_opcodes[i].disabled = false; #endif if (blacklist[0] != '\0') { const char *p = blacklist; @@ -4035,7 +4103,14 @@ static bool merge_blacklist() int opcode1 = read_opcode(p); if (opcode1 < 0) + { +#ifdef USE_JIT_FPU + if (read_fpu_opcode(&p)) + continue; +#endif + bug(" : invalid opcode %s", p); return false; + } p += 4; int opcode2 = opcode1; @@ -4043,7 +4118,10 @@ static bool merge_blacklist() p++; opcode2 = read_opcode(p); if (opcode2 < 0) + { + bug(" : invalid opcode %s", p); return false; + } p += 4; } @@ -4066,6 +4144,12 @@ static bool merge_blacklist() void build_comp(void) { +#ifdef FSUAE + if (!g_fs_uae_jit_compiler) { + jit_log("JIT: JIT compiler is not enabled"); + return; + } +#endif int i; unsigned long opcode; const struct comptbl* tbl=op_smalltbl_0_comp_ff; @@ -4084,6 +4168,8 @@ void build_comp(void) : op_smalltbl_5_nf); #endif #endif + // Initialize target CPU (check for features, e.g. CMOV, rat stalls) + raw_init_cpu(); #ifdef NATMEM_OFFSET #ifdef UAE @@ -4220,7 +4306,7 @@ void build_comp(void) { jit_log(" : blacklist merge failure!"); } - + count=0; for (opcode = 0; opcode < 65536; opcode++) { if (compfunctbl[cft_map(opcode)]) @@ -4258,21 +4344,19 @@ void build_comp(void) } -static void flush_icache_none(int) +static void flush_icache_none(void) { /* Nothing to do. */ } -static void flush_icache_hard(int n) +void flush_icache_hard(void) { blockinfo* bi, *dbi; - hard_flush_count++; #ifndef UAE jit_log("JIT: Flush Icache_hard(%d/%x/%p), %u KB", n,regs.pc,regs.pc_p,current_cache_size/1024); #endif - UNUSED(n); bi=active; while(bi) { cache_tags[cacheline(bi->pc_p)].handler=(cpuop_func*)popall_execute_normal; @@ -4309,22 +4393,11 @@ static void flush_icache_hard(int n) we simply mark everything as "needs to be checked". */ -#ifdef WINUAE_ARANYM -static inline void flush_icache_lazy(int) -#else -void flush_icache(int n) -#endif +static inline void flush_icache_lazy(void) { blockinfo* bi; blockinfo* bi2; -#ifdef UAE - if (currprefs.comp_hardflush) { - flush_icache_hard(n); - return; - } -#endif - soft_flush_count++; if (!active) return; @@ -4359,51 +4432,15 @@ void flush_icache(int n) active=NULL; } -#ifdef UAE -static -#endif -// void flush_icache_range(uae_u32 start, uae_u32 length) -// { -// if (!active) -// return; -// #if LAZY_FLUSH_ICACHE_RANGE -// uae_u8 *start_p = get_real_address(start); -// blockinfo *bi = active; -// while (bi) { -// #if USE_CHECKSUM_INFO -// bool invalidate = false; -// for (checksum_info *csi = bi->csi; csi && !invalidate; csi = csi->next) -// invalidate = (((start_p - csi->start_p) < csi->length) || -// ((csi->start_p - start_p) < length)); -// #else -// // Assume system is consistent and would invalidate the right range -// const bool invalidate = (bi->pc_p - start_p) < length; -// #endif -// if (invalidate) { -// uae_u32 cl = cacheline(bi->pc_p); -// if (bi == cache_tags[cl + 1].bi) -// cache_tags[cl].handler = (cpuop_func *)popall_execute_normal; -// bi->handler_to_use = (cpuop_func *)popall_execute_normal; -// set_dhtu(bi, bi->direct_pen); -// bi->status = BI_NEED_RECOMP; -// } -// bi = bi->next; -// } -// return; -// #else -// UNUSED(start); -// UNUSED(length); -// #endif -// flush_icache(-1); -// } - -void flush_icache_range(uae_u8 *start_p, uae_u32 length) +#if 0 +static void flush_icache_range(uae_u32 start, uae_u32 length) { if (!active) return; #if LAZY_FLUSH_ICACHE_RANGE + uae_u8 *start_p = get_real_address(start); blockinfo *bi = active; while (bi) { #if USE_CHECKSUM_INFO @@ -4427,18 +4464,13 @@ void flush_icache_range(uae_u8 *start_p, uae_u32 length) } return; #else - // UNUSED(start); - // UNUSED(length); + UNUSED(start); + UNUSED(length); #endif - flush_icache(-1); + flush_icache(); } +#endif -/* -static void catastrophe(void) -{ - jit_abort("catastprophe"); -} -*/ int failure; @@ -4465,45 +4497,45 @@ void compiler_dumpstate(void) if (!JITDebug) return; - bug("### Host addresses"); - bug("MEM_BASE : %lx", (unsigned long)MEMBaseDiff); - bug("PC_P : %p", ®s.pc_p); - bug("SPCFLAGS : %p", ®s.spcflags); - bug("D0-D7 : %p-%p", ®s.regs[0], ®s.regs[7]); - bug("A0-A7 : %p-%p", ®s.regs[8], ®s.regs[15]); - bug(" "); + jit_log("### Host addresses"); + jit_log("MEM_BASE : %lx", (unsigned long)MEMBaseDiff); + jit_log("PC_P : %p", ®s.pc_p); + jit_log("SPCFLAGS : %p", ®s.spcflags); + jit_log("D0-D7 : %p-%p", ®s.regs[0], ®s.regs[7]); + jit_log("A0-A7 : %p-%p", ®s.regs[8], ®s.regs[15]); + jit_log(" "); - bug("### M68k processor state"); + jit_log("### M68k processor state"); m68k_dumpstate(stderr, 0); - bug(" "); + jit_log(" "); - bug("### Block in Atari address space"); - bug("M68K block : %p", + jit_log("### Block in Atari address space"); + jit_log("M68K block : %p", (void *)(uintptr)last_regs_pc_p); if (last_regs_pc_p != 0) { - bug("Native block : %p (%d bytes)", + jit_log("Native block : %p (%d bytes)", (void *)last_compiled_block_addr, get_blockinfo_addr(last_regs_pc_p)->direct_handler_size); } - bug(" "); + jit_log(" "); } #endif #ifdef UAE void compile_block(cpu_history *pc_hist, int blocklen, int totcycles) { - if (letit && compiled_code && currprefs.cpu_model >= 68020) { + if (cache_enabled && compiled_code && currprefs.cpu_model >= 68020) { #else static void compile_block(cpu_history* pc_hist, int blocklen) { - if (letit && compiled_code) { + if (cache_enabled && compiled_code) { #endif #ifdef PROFILE_COMPILE_TIME compile_count++; clock_t start_time = clock(); #endif #ifdef JIT_DEBUG - bool disasm_block = true; + bool disasm_block = false; #endif /* OK, here we need to 'compile' a block */ @@ -4527,7 +4559,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) redo_current_block=0; if (current_compile_p >= MAX_COMPILE_PTR) - flush_icache_hard(7); + flush_icache_hard(); alloc_blockinfos(); @@ -4643,12 +4675,12 @@ static void compile_block(cpu_history* pc_hist, int blocklen) #ifdef USE_CPU_EMUL_SERVICES compemu_raw_sub_l_mi((uintptr)&emulated_ticks,blocklen); compemu_raw_jcc_b_oponly(NATIVE_CC_GT); - uae_s8 *branchadd=(uae_s8*)get_target(); + uae_u8 *branchadd=get_target(); skip_byte(); raw_dec_sp(STACK_SHADOW_SPACE); compemu_raw_call((uintptr)cpu_do_check_ticks); raw_inc_sp(STACK_SHADOW_SPACE); - *branchadd=(uintptr)get_target()-((uintptr)branchadd+1); + *branchadd=get_target()-(branchadd+1); #endif #ifdef JIT_DEBUG @@ -4690,7 +4722,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) prepare_for_call_1(); prepare_for_call_2(); raw_mov_l_ri(REG_PAR1, ((uintptr)(pc_hist[i].location)) - MEMBaseDiff); - raw_mov_w_ri(REG_PAR2, opcode); + raw_mov_w_ri(REG_PAR2, cft_map(opcode)); raw_dec_sp(STACK_SHADOW_SPACE); compemu_raw_call((uintptr)m68k_record_step); raw_inc_sp(STACK_SHADOW_SPACE); @@ -4706,11 +4738,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen) } was_comp=1; +#ifdef WINUAE_ARANYM bool isnop = do_get_mem_word(pc_hist[i].location) == 0x4e71 || ((i + 1) < blocklen && do_get_mem_word(pc_hist[i+1].location) == 0x4e71); if (isnop) compemu_raw_mov_l_mi((uintptr)®s.fault_pc, ((uintptr)(pc_hist[i].location)) - MEMBaseDiff); +#endif comptbl[opcode](opcode); freescratch(); @@ -4724,6 +4758,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) flush(1); was_comp=0; #endif +#ifdef WINUAE_ARANYM /* * workaround for buserror handling: on a "nop", write registers back */ @@ -4733,6 +4768,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) nop(); was_comp=0; } +#endif } if (failure) { @@ -4758,7 +4794,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) #endif if (i < blocklen - 1) { - uae_s8* branchadd; + uae_u8* branchadd; /* if (SPCFLAGS_TEST(SPCFLAG_STOP)) popall_do_nothing() */ compemu_raw_mov_l_rm(0,(uintptr)specflags); @@ -4767,13 +4803,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen) data_check_end(8, 64); // just a pessimistic guess... #endif compemu_raw_jz_b_oponly(); - branchadd=(uae_s8*)get_target(); + branchadd=get_target(); skip_byte(); #ifdef UAE raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles)); #endif compemu_raw_jmp((uintptr)popall_do_nothing); - *branchadd=(uintptr)get_target()-(uintptr)branchadd-1; + *branchadd=get_target()-branchadd-1; } } } @@ -4804,7 +4840,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) } #endif log_flush(); - + if (next_pc_p) { /* A branch was registered */ uintptr t1=next_pc_p; uintptr t2=taken_pc_p; @@ -4900,7 +4936,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) tbi = get_blockinfo_addr_new((void*) v, 1); match_states(tbi); - + #ifdef UAE raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles)); raw_jcc_l_oponly(NATIVE_CC_PL); @@ -4936,10 +4972,10 @@ static void compile_block(cpu_history* pc_hist, int blocklen) if (callers_need_recompile(&live,&(bi->env))) { mark_callers_recompile(bi); } - + big_to_small_state(&live,&(bi->env)); #endif - + #if USE_CHECKSUM_INFO remove_from_list(bi); if (trace_in_rom) { @@ -4974,7 +5010,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) } #endif - current_cache_size += get_target() - (uae_u8 *)current_compile_p; + current_cache_size += get_target() - current_compile_p; #ifdef JIT_DEBUG bi->direct_handler_size = get_target() - (uae_u8 *)current_block_start_target; @@ -4983,9 +5019,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen) uaecptr block_addr = start_pc + ((char *)pc_hist[0].location - (char *)start_pc_p); jit_log("M68K block @ 0x%08x (%d insns)", block_addr, blocklen); uae_u32 block_size = ((uae_u8 *)pc_hist[blocklen - 1].location - (uae_u8 *)pc_hist[0].location) + 1; +#ifdef WINUAE_ARANYM disasm_m68k_block((const uae_u8 *)pc_hist[0].location, block_size); +#endif jit_log("Compiled block @ %p", pc_hist[0].location); +#ifdef WINUAE_ARANYM disasm_native_block((const uae_u8 *)current_block_start_target, bi->direct_handler_size); +#endif UNUSED(block_addr); } #endif @@ -5022,7 +5062,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) /* We will flush soon, anyway, so let's do it now */ if (current_compile_p >= MAX_COMPILE_PTR) - flush_icache_hard(7); + flush_icache_hard(); bi->status=BI_ACTIVE; if (redo_current_block) @@ -5037,7 +5077,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen) #endif } -#ifndef UAE +#ifdef USE_CPU_EMUL_SERVICES /* Account for compilation time */ cpu_do_check_ticks(); #endif @@ -5060,7 +5100,7 @@ void exec_nostats(void) for (;;) { uae_u32 opcode = GET_OPCODE; #if FLIGHT_RECORDER - m68k_record_step(m68k_getpc(), opcode); + m68k_record_step(m68k_getpc(), cft_map(opcode)); #endif (*cpufunctbl[opcode])(opcode); cpu_check_ticks(); @@ -5090,7 +5130,7 @@ void execute_normal(void) pc_hist[blocklen++].location = (uae_u16 *)regs.pc_p; uae_u32 opcode = GET_OPCODE; #if FLIGHT_RECORDER - m68k_record_step(m68k_getpc(), opcode); + m68k_record_step(m68k_getpc(), cft_map(opcode)); #endif (*cpufunctbl[opcode])(opcode); cpu_check_ticks(); @@ -5131,11 +5171,15 @@ void m68k_compile_execute (void) setjmpagain: TRY(prb) { for (;;) { - if (quit_program == 1) { + if (quit_program > 0) { + if (quit_program == 1) { #if FLIGHT_RECORDER - dump_flight_recorder(); + dump_flight_recorder(); #endif - break; + break; + } + quit_program = 0; + m68k_reset (); } m68k_do_compile_execute(); } @@ -5148,7 +5192,7 @@ setjmpagain: regs.fault_pc, regs.mmu_fault_addr, get_long (regs.vbr + 4*prb), regs.regs[15]); - flush_icache(0); + flush_icache(); Exception(prb, 0); goto setjmpagain; } diff --git a/BasiliskII/src/uae_cpu/compiler/gencomp.c b/BasiliskII/src/uae_cpu/compiler/gencomp.c index febeddc9..712d7873 100644 --- a/BasiliskII/src/uae_cpu/compiler/gencomp.c +++ b/BasiliskII/src/uae_cpu/compiler/gencomp.c @@ -93,11 +93,16 @@ #define DISABLE_I_FSCC #define DISABLE_I_MOVE16 */ + #endif /* UAE */ #ifdef UAE #define JIT_PATH "jit/" +#ifdef FSUAE +#define GEN_PATH "gen/" +#else #define GEN_PATH "jit/" +#endif #define RETURN "return 0;" #define RETTYPE "uae_u32" #define NEXT_CPU_LEVEL 5 @@ -107,7 +112,6 @@ #define RETURN "return;" #define RETTYPE "void" #define NEXT_CPU_LEVEL 4 -#define ua(s) s #endif #define BOOL_TYPE "int" @@ -738,8 +742,9 @@ static void genmov16(uae_u32 opcode, struct instr *curi) "\tadd_l_ri(dst,4);\n" "\treadlong(src,tmp,scratchie);\n" "\twritelong_clobber(dst,tmp,scratchie);\n"); - comprintf("\t} else {\n"); + comprintf("\t} else\n"); #endif + start_brace(); comprintf("\tint tmp=scratchie;\n"); comprintf("\tscratchie+=4;\n" "\tget_n_addr(src,src,scratchie);\n" @@ -755,9 +760,7 @@ static void genmov16(uae_u32 opcode, struct instr *curi) "\tmov_l_Rr(dst,tmp+2,8);\n" "\tforget_about(tmp+2);\n" "\tmov_l_Rr(dst,tmp+3,12);\n"); -#ifdef UAE - comprintf("\t}\n"); -#endif + close_brace(); } static void @@ -1304,11 +1307,11 @@ genflags (flagtypes type, wordsizes size, const char *value, const char *src, co break; } comprintf("\tlive_flags();\n"); - comprintf("\tif (needed_flags&FLAG_Z) {\n" - "\tcmov_l_rr(zero,one,%d);\n" - "\tset_zero(zero, one);\n" /* No longer need one */ - "\tlive_flags();\n" - "\t}\n",NATIVE_CC_NE); + comprintf("\tif (needed_flags&FLAG_Z) {\n"); + comprintf("\tcmov_l_rr(zero,one,%d);\n", NATIVE_CC_NE); + comprintf("\tset_zero(zero, one);\n"); /* No longer need one */ + comprintf("\tlive_flags();\n"); + comprintf("\t}\n"); comprintf("\tend_needflags();\n"); duplicate_carry(); comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); @@ -2181,158 +2184,63 @@ gen_opcode (unsigned int opcode) genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); - if (curi->smode!=immi) { - if (!noflags) { - uses_cmov; - start_brace(); - comprintf("\tint highmask;\n" - "\tint width;\n" - "\tint cdata=scratchie++;\n" - "\tint tmpcnt=scratchie++;\n" - "\tint highshift=scratchie++;\n"); - comprintf("\tmov_l_rr(tmpcnt,cnt);\n" - "\tand_l_ri(tmpcnt,63);\n" - "\tmov_l_ri(cdata,0);\n" - "\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE); - /* cdata is now either data (for shift count!=0) or - 0 (for shift count==0) */ - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n" - "\thighmask=0x38;\n" - "\twidth=8;\n"); - break; - case sz_word: comprintf("\tshra_w_rr(data,cnt);\n" - "\thighmask=0x30;\n" - "\twidth=16;\n"); - break; - case sz_long: comprintf("\tshra_l_rr(data,cnt);\n" - "\thighmask=0x20;\n" - "\twidth=32;\n"); - break; - default: assert(0); - } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(highshift,0);\n" - "mov_l_ri(scratchie,width/2);\n" - "cmov_l_rr(highshift,scratchie,%d);\n", NATIVE_CC_NE); - /* The x86 masks out bits, so we now make sure that things - really get shifted as much as planned */ - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break; - case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break; - case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break; - default: assert(0); - } - /* And again */ - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break; - case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break; - case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break; - default: assert(0); - } - /* Result of shift is now in data. Now we need to determine - the carry by shifting cdata one less */ - comprintf("\tsub_l_ri(tmpcnt,1);\n"); - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(cdata,tmpcnt);\n");break; - case sz_word: comprintf("\tshra_w_rr(cdata,tmpcnt);\n");break; - case sz_long: comprintf("\tshra_l_rr(cdata,tmpcnt);\n");break; - default: assert(0); - } - /* If the shift count was higher than the width, we need - to pick up the sign from data */ - comprintf("test_l_ri(tmpcnt,highmask);\n" - "cmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE); - /* And create the flags */ + start_brace(); + if (!noflags) comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } - else { + if (curi->smode!=immi) { uses_cmov; start_brace(); - comprintf("\tint highmask;\n" - "\tint width;\n" - "\tint highshift=scratchie++;\n"); + comprintf("\tint zero = scratchie++;\n"); + comprintf("\tint minus1 = scratchie++;\n"); + comprintf("\tand_l_ri(cnt,63);\n"); + comprintf("\tmov_l_ri(zero, 0);\n"); + comprintf("\tmov_l_ri(minus1, -1);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n" - "\thighmask=0x38;\n" - "\twidth=8;\n"); - break; - case sz_word: comprintf("\tshra_w_rr(data,cnt);\n" - "\thighmask=0x30;\n" - "\twidth=16;\n"); - break; - case sz_long: comprintf("\tshra_l_rr(data,cnt);\n" - "\thighmask=0x20;\n" - "\twidth=32;\n"); - break; + case sz_byte: + comprintf("\ttest_b_rr(data,data);\n"); + comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n"); + comprintf("\ttest_l_ri(cnt, 0x38);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshra_b_rr(data,cnt);\n"); + break; + case sz_word: + comprintf("\ttest_w_rr(data,data);\n"); + comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n"); + comprintf("\ttest_l_ri(cnt, 0x30);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshra_w_rr(data,cnt);\n"); + break; + case sz_long: + comprintf("\ttest_l_rr(data,data);\n"); + comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n"); + comprintf("\ttest_l_ri(cnt, 0x20);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshra_l_rr(data,cnt);\n"); + break; default: assert(0); } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(highshift,0);\n" - "mov_l_ri(scratchie,width/2);\n" - "cmov_l_rr(highshift,scratchie,%d);\n",NATIVE_CC_NE); - /* The x86 masks out bits, so we now make sure that things - really get shifted as much as planned */ - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break; - case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break; - case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break; - default: assert(0); - } - /* And again */ - switch(curi->size) { - case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break; - case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break; - case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break; - default: assert(0); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } + /* Result of shift is now in data. */ } else { - start_brace(); - comprintf("\tint tmp=scratchie++;\n" - "\tint bp;\n" - "\tmov_l_rr(tmp,data);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshra_b_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; - case sz_word: comprintf("\tshra_w_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; - case sz_long: comprintf("\tshra_l_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; + case sz_byte: comprintf("\tshra_b_ri(data,srcreg);\n"); break; + case sz_word: comprintf("\tshra_w_ri(data,srcreg);\n"); break; + case sz_long: comprintf("\tshra_l_ri(data,srcreg);\n"); break; default: assert(0); } - - if (!noflags) { - comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); } + /* And create the flags */ + if (!noflags) { + comprintf("\tlive_flags();\n"); + comprintf("\tend_needflags();\n"); + if (curi->smode!=immi) + comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4); + else + comprintf("\tduplicate_carry();\n"); + comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); + } + genastore ("data", curi->dmode, "dstreg", curi->size, "data"); break; case i_ASL: @@ -2359,129 +2267,54 @@ gen_opcode (unsigned int opcode) genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); - if (curi->smode!=immi) { - if (!noflags) { - uses_cmov; - start_brace(); - comprintf("\tint highmask;\n" - "\tint cdata=scratchie++;\n" - "\tint tmpcnt=scratchie++;\n"); - comprintf("\tmov_l_rr(tmpcnt,cnt);\n" - "\tand_l_ri(tmpcnt,63);\n" - "\tmov_l_ri(cdata,0);\n" - "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE); - /* cdata is now either data (for shift count!=0) or - 0 (for shift count==0) */ - switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshll_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshll_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; - default: assert(0); - } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - /* Result of shift is now in data. Now we need to determine - the carry by shifting cdata one less */ - comprintf("\tsub_l_ri(tmpcnt,1);\n"); - switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break; - case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break; - case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break; - default: assert(0); - } - comprintf("test_l_ri(tmpcnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE); - /* And create the flags */ - comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,7);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,15);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,31);\n"); break; - } - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } - else { + if (!noflags) + comprintf("\tstart_needflags();\n"); + if (curi->smode!=immi) { uses_cmov; start_brace(); - comprintf("\tint highmask;\n"); + comprintf("\tint zero = scratchie++;\n"); + comprintf("\tand_l_ri(cnt,63);\n"); + comprintf("\tmov_l_ri(zero, 0);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshll_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshll_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; + case sz_byte: + comprintf("\ttest_l_ri(cnt, 0x38);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_b_rr(data,cnt);\n"); + break; + case sz_word: + comprintf("\ttest_l_ri(cnt, 0x30);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_w_rr(data,cnt);\n"); + break; + case sz_long: + comprintf("\ttest_l_ri(cnt, 0x20);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_l_rr(data,cnt);\n"); + break; default: assert(0); } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } + /* Result of shift is now in data. */ } else { - start_brace(); - comprintf("\tint tmp=scratchie++;\n" - "\tint bp;\n" - "\tmov_l_rr(tmp,data);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n" - "\tbp=8-srcreg;\n"); break; - case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n" - "\tbp=16-srcreg;\n"); break; - case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n" - "\tbp=32-srcreg;\n"); break; + case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"); break; + case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"); break; + case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"); break; default: assert(0); } - - if (!noflags) { - comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); } + /* And create the flags */ + if (!noflags) { + comprintf("\tlive_flags();\n"); + comprintf("\tend_needflags();\n"); + if (curi->smode!=immi) + comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4); + else + comprintf("\tduplicate_carry();\n"); + comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); + } + genastore ("data", curi->dmode, "dstreg", curi->size, "data"); break; case i_LSR: @@ -2500,126 +2333,55 @@ gen_opcode (unsigned int opcode) genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); - if (curi->smode!=immi) { - if (!noflags) { - uses_cmov; - start_brace(); - comprintf("\tint highmask;\n" - "\tint cdata=scratchie++;\n" - "\tint tmpcnt=scratchie++;\n"); - comprintf("\tmov_l_rr(tmpcnt,cnt);\n" - "\tand_l_ri(tmpcnt,63);\n" - "\tmov_l_ri(cdata,0);\n" - "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE); - /* cdata is now either data (for shift count!=0) or - 0 (for shift count==0) */ - switch(curi->size) { - case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; - default: assert(0); - } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - /* Result of shift is now in data. Now we need to determine - the carry by shifting cdata one less */ - comprintf("\tsub_l_ri(tmpcnt,1);\n"); - switch(curi->size) { - case sz_byte: comprintf("\tshrl_b_rr(cdata,tmpcnt);\n");break; - case sz_word: comprintf("\tshrl_w_rr(cdata,tmpcnt);\n");break; - case sz_long: comprintf("\tshrl_l_rr(cdata,tmpcnt);\n");break; - default: assert(0); - } - comprintf("test_l_ri(tmpcnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE); - /* And create the flags */ + + start_brace(); + if (!noflags) comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } - else { + if (curi->smode!=immi) { uses_cmov; start_brace(); - comprintf("\tint highmask;\n"); + comprintf("\tint zero = scratchie++;\n"); + comprintf("\tand_l_ri(cnt,63);\n"); + comprintf("\tmov_l_ri(zero, 0);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; + case sz_byte: + comprintf("\ttest_l_ri(cnt, 0x38);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshrl_b_rr(data,cnt);\n"); + break; + case sz_word: + comprintf("\ttest_l_ri(cnt, 0x30);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshrl_w_rr(data,cnt);\n"); + break; + case sz_long: + comprintf("\ttest_l_ri(cnt, 0x20);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshrl_l_rr(data, cnt);\n"); + break; default: assert(0); } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } + /* Result of shift is now in data. */ } else { - start_brace(); - comprintf("\tint tmp=scratchie++;\n" - "\tint bp;\n" - "\tmov_l_rr(tmp,data);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshrl_b_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; - case sz_word: comprintf("\tshrl_w_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; - case sz_long: comprintf("\tshrl_l_ri(data,srcreg);\n" - "\tbp=srcreg-1;\n"); break; + case sz_byte: comprintf("\tshrl_b_ri(data,srcreg);\n"); break; + case sz_word: comprintf("\tshrl_w_ri(data,srcreg);\n"); break; + case sz_long: comprintf("\tshrl_l_ri(data,srcreg);\n"); break; default: assert(0); } - - if (!noflags) { - comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); } + /* And create the flags */ + if (!noflags) { + comprintf("\tlive_flags();\n"); + comprintf("\tend_needflags();\n"); + if (curi->smode!=immi) + comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4); + else + comprintf("\tduplicate_carry();\n"); + comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); + } + genastore ("data", curi->dmode, "dstreg", curi->size, "data"); break; case i_LSL: @@ -2638,128 +2400,55 @@ gen_opcode (unsigned int opcode) genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0); - if (curi->smode!=immi) { - if (!noflags) { - uses_cmov; - start_brace(); - comprintf("\tint highmask;\n" - "\tint cdata=scratchie++;\n" - "\tint tmpcnt=scratchie++;\n"); - comprintf("\tmov_l_rr(tmpcnt,cnt);\n" - "\tand_l_ri(tmpcnt,63);\n" - "\tmov_l_ri(cdata,0);\n" - "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE); - /* cdata is now either data (for shift count!=0) or - 0 (for shift count==0) */ - switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshll_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshll_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; - default: assert(0); - } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - /* Result of shift is now in data. Now we need to determine - the carry by shifting cdata one less */ - comprintf("\tsub_l_ri(tmpcnt,1);\n"); - switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break; - case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break; - case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break; - default: assert(0); - } - comprintf("test_l_ri(tmpcnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE); - /* And create the flags */ + + start_brace(); + if (!noflags) comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,7);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,15);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); - comprintf("\t bt_l_ri(cdata,31);\n"); break; - } - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } - else { + if (curi->smode!=immi) { uses_cmov; start_brace(); - comprintf("\tint highmask;\n"); + comprintf("\tint zero = scratchie++;\n"); + comprintf("\tand_l_ri(cnt,63);\n"); + comprintf("\tmov_l_ri(zero, 0);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n" - "\thighmask=0x38;\n"); - break; - case sz_word: comprintf("\tshll_w_rr(data,cnt);\n" - "\thighmask=0x30;\n"); - break; - case sz_long: comprintf("\tshll_l_rr(data,cnt);\n" - "\thighmask=0x20;\n"); - break; + case sz_byte: + comprintf("\ttest_l_ri(cnt, 0x38);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_b_rr(data,cnt);\n"); + break; + case sz_word: + comprintf("\ttest_l_ri(cnt, 0x30);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_w_rr(data,cnt);\n"); + break; + case sz_long: + comprintf("\ttest_l_ri(cnt, 0x20);\n"); + comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n"); + comprintf("\tshll_l_rr(data,cnt);\n"); + break; default: assert(0); } - comprintf("test_l_ri(cnt,highmask);\n" - "mov_l_ri(scratchie,0);\n" - "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ); - switch(curi->size) { - case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break; - case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break; - case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break; - default: assert(0); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); - } + /* Result of shift is now in data. */ } else { - start_brace(); - comprintf("\tint tmp=scratchie++;\n" - "\tint bp;\n" - "\tmov_l_rr(tmp,data);\n"); switch(curi->size) { - case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n" - "\tbp=8-srcreg;\n"); break; - case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n" - "\tbp=16-srcreg;\n"); break; - case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n" - "\tbp=32-srcreg;\n"); break; + case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"); break; + case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"); break; + case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"); break; default: assert(0); } - - if (!noflags) { - comprintf("\tstart_needflags();\n"); - comprintf("\tif (needed_flags & FLAG_ZNV)\n"); - switch(curi->size) { - case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; - case sz_word: comprintf("\t test_w_rr(data,data);\n"); break; - case sz_long: comprintf("\t test_l_rr(data,data);\n"); break; - } - comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */ - comprintf("\t live_flags();\n"); - comprintf("\t end_needflags();\n"); - comprintf("\t duplicate_carry();\n"); - comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); - } - genastore ("data", curi->dmode, "dstreg", curi->size, "data"); } + /* And create the flags */ + if (!noflags) { + comprintf("\tlive_flags();\n"); + comprintf("\tend_needflags();\n"); + if (curi->smode!=immi) + comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4); + else + comprintf("\tduplicate_carry();\n"); + comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n"); + } + genastore ("data", curi->dmode, "dstreg", curi->size, "data"); break; case i_ROL: @@ -2787,6 +2476,9 @@ gen_opcode (unsigned int opcode) if (!noflags) { comprintf("\tstart_needflags();\n"); + /* + * x86 ROL instruction does not set ZF/SF, so we need extra checks here + */ comprintf("\tif (needed_flags & FLAG_ZNV)\n"); switch(curi->size) { case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; @@ -2825,6 +2517,9 @@ gen_opcode (unsigned int opcode) if (!noflags) { comprintf("\tstart_needflags();\n"); + /* + * x86 ROR instruction does not set ZF/SF, so we need extra checks here + */ comprintf("\tif (needed_flags & FLAG_ZNV)\n"); switch(curi->size) { case sz_byte: comprintf("\t test_b_rr(data,data);\n"); break; @@ -3133,7 +2828,7 @@ generate_includes (FILE * f) fprintf (f, "#include \"sysdeps.h\"\n"); #ifdef UAE fprintf (f, "#include \"options.h\"\n"); - fprintf (f, "#include \"memory.h\"\n"); + fprintf (f, "#include \"uae/memory.h\"\n"); #else fprintf (f, "#include \"m68k.h\"\n"); fprintf (f, "#include \"memory.h\"\n"); @@ -3147,7 +2842,6 @@ generate_includes (FILE * f) static int postfix; -#ifdef UAE static char *decodeEA (amodes mode, wordsizes size) { static char buffer[80]; @@ -3221,22 +2915,13 @@ static char *decodeEA (amodes mode, wordsizes size) return buffer; } -static char *outopcode (int opcode) +static char *outopcode (const char *name, int opcode) { static char out[100]; struct instr *ins; - int i; ins = &table68k[opcode]; - for (i = 0; lookuptab[i].name[0]; i++) { - if (ins->mnemo == lookuptab[i].mnemo) - break; - } - { - char *s = ua (lookuptab[i].name); - strcpy (out, s); - xfree (s); - } + strcpy (out, name); if (ins->smode == immi) strcat (out, "Q"); if (ins->size == sz_byte) @@ -3254,7 +2939,6 @@ static char *outopcode (int opcode) } return out; } -#endif static void @@ -3266,11 +2950,7 @@ generate_one_opcode (int rp, int noflags) int aborted=0; int have_srcreg=0; int have_dstreg=0; -#ifdef UAE - char *name; -#else const char *name; -#endif if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level) @@ -3459,34 +3139,23 @@ generate_one_opcode (int rp, int noflags) else strcpy(flags, "0"); -#ifdef UAE +#ifdef UAE /* RETTYPE != void */ comprintf ("return 0;\n"); #endif comprintf ("}\n"); -#ifdef UAE - name = ua (lookuptab[i].name); -#else name = lookuptab[i].name; -#endif if (aborted) { fprintf (stblfile, "{ NULL, %u, %s }, /* %s */\n", opcode, flags, name); com_discard(); } else { const char *tbl = noflags ? "nf" : "ff"; -#ifdef UAE - printf ("/* %s */\n", outopcode (opcode)); -#else - printf ("/* %s */\n", name); -#endif fprintf (stblfile, "{ op_%x_%d_comp_%s, %u, %s }, /* %s */\n", opcode, postfix, tbl, opcode, flags, name); fprintf (headerfile, "extern compop_func op_%x_%d_comp_%s;\n", opcode, postfix, tbl); - printf (RETTYPE " REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode)\n{\n", opcode, postfix, tbl); + printf ("/* %s */\n", outopcode (name, opcode)); + printf (RETTYPE " REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, tbl, name); com_flush(); } -#ifdef UAE - xfree (name); -#endif } opcode_next_clev[rp] = next_cpu_level; opcode_last_postfix[rp] = postfix; @@ -3552,7 +3221,12 @@ void cygwin_mingw_abort() } #endif +#if defined(FSUAE) && defined (WINDOWS) +#include "windows.h" +int WINAPI WinMain(HINSTANCE hInstance, HINSTANCE hPrevInstance, LPSTR lpCmdLine, int nCmdShow) +#else int main(void) +#endif { read_table68k (); do_merges (); @@ -3582,6 +3256,7 @@ int main(void) generate_includes (stblfile); printf("#include \"" JIT_PATH "compemu.h\"\n"); + printf("#include \"" JIT_PATH "flags_x86.h\"\n"); noflags=0; generate_func (noflags); diff --git a/BasiliskII/src/uae_cpu/compiler/gencomp_arm.c b/BasiliskII/src/uae_cpu/compiler/gencomp_arm.c index e9bf9bb4..7ec9ff76 100644 --- a/BasiliskII/src/uae_cpu/compiler/gencomp_arm.c +++ b/BasiliskII/src/uae_cpu/compiler/gencomp_arm.c @@ -677,6 +677,7 @@ static void gen_move16(uae_u32 opcode, struct instr *curi) { else if ((opcode & 0xfff8) == 0xf608) comprintf("\tarm_ADD_l_ri8(dstreg+8,16);\n"); + start_brace(); comprintf("\tint tmp=scratchie;\n"); comprintf("\tscratchie+=4;\n"); @@ -693,6 +694,7 @@ static void gen_move16(uae_u32 opcode, struct instr *curi) { "\tmov_l_Rr(dst,tmp+2,8);\n" "\tforget_about(tmp+2);\n" "\tmov_l_Rr(dst,tmp+3,12);\n"); + close_brace(); #endif } @@ -4632,10 +4634,10 @@ gen_opcode(unsigned long int opcode) { failure; break; - case i_NATFEAT_ID: - case i_NATFEAT_CALL: - failure; - break; + // case i_NATFEAT_ID: + // case i_NATFEAT_CALL: + // failure; + // break; case i_MMUOP: isjump; @@ -4665,6 +4667,105 @@ static void generate_includes(FILE * f) { static int postfix; +static char *decodeEA (amodes mode, wordsizes size) +{ + static char buffer[80]; + + buffer[0] = 0; + switch (mode){ + case Dreg: + strcpy (buffer,"Dn"); + break; + case Areg: + strcpy (buffer,"An"); + break; + case Aind: + strcpy (buffer,"(An)"); + break; + case Aipi: + strcpy (buffer,"(An)+"); + break; + case Apdi: + strcpy (buffer,"-(An)"); + break; + case Ad16: + strcpy (buffer,"(d16,An)"); + break; + case Ad8r: + strcpy (buffer,"(d8,An,Xn)"); + break; + case PC16: + strcpy (buffer,"(d16,PC)"); + break; + case PC8r: + strcpy (buffer,"(d8,PC,Xn)"); + break; + case absw: + strcpy (buffer,"(xxx).W"); + break; + case absl: + strcpy (buffer,"(xxx).L"); + break; + case imm: + switch (size){ + case sz_byte: + strcpy (buffer,"#.B"); + break; + case sz_word: + strcpy (buffer,"#.W"); + break; + case sz_long: + strcpy (buffer,"#.L"); + break; + default: + break; + } + break; + case imm0: + strcpy (buffer,"#.B"); + break; + case imm1: + strcpy (buffer,"#.W"); + break; + case imm2: + strcpy (buffer,"#.L"); + break; + case immi: + strcpy (buffer,"#"); + break; + + default: + break; + } + return buffer; +} + +static char *outopcode (const char *name, int opcode) +{ + static char out[100]; + struct instr *ins; + + ins = &table68k[opcode]; + strcpy (out, name); + if (ins->smode == immi) + strcat (out, "Q"); + if (ins->size == sz_byte) + strcat (out,".B"); + if (ins->size == sz_word) + strcat (out,".W"); + if (ins->size == sz_long) + strcat (out,".L"); + strcat (out," "); + if (ins->suse) + strcat (out, decodeEA (ins->smode, ins->size)); + if (ins->duse) { + if (ins->suse) strcat (out,","); + strcat (out, decodeEA (ins->dmode, ins->size)); + } + return out; +} + + static void generate_one_opcode(int rp, int noflags) { int i; uae_u16 smsk, dmsk; @@ -4858,6 +4959,7 @@ static void generate_one_opcode(int rp, int noflags) { opcode, postfix, tbl, opcode, flags, name); fprintf(headerfile, "extern compop_func op_%x_%d_comp_%s;\n", opcode, postfix, tbl); + printf ("/* %s */\n", outopcode (name, opcode)); printf( "void REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, tbl, name); diff --git a/BasiliskII/src/uae_cpu/gencpu.c b/BasiliskII/src/uae_cpu/gencpu.c index 1653adab..5ab3895a 100644 --- a/BasiliskII/src/uae_cpu/gencpu.c +++ b/BasiliskII/src/uae_cpu/gencpu.c @@ -582,7 +582,7 @@ static void genmovemle (uae_u16 opcode) static void duplicate_carry (void) { - printf ("\tCOPY_CARRY;\n"); + printf ("\tCOPY_CARRY();\n"); } typedef enum { @@ -682,7 +682,7 @@ static void genflags_normal (flagtypes type, wordsizes size, char *value, char * switch (type) { case flag_logical: - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); printf ("\tSET_ZFLG (%s == 0);\n", vstr); printf ("\tSET_NFLG (%s < 0);\n", vstr); break; @@ -697,10 +697,10 @@ static void genflags_normal (flagtypes type, wordsizes size, char *value, char * printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n"); break; case flag_z: - printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr); + printf ("\tSET_ZFLG (GET_ZFLG() & (%s == 0));\n", vstr); break; case flag_zn: - printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr); + printf ("\tSET_ZFLG (GET_ZFLG() & (%s == 0));\n", vstr); printf ("\tSET_NFLG (%s < 0);\n", vstr); break; case flag_add: @@ -926,7 +926,7 @@ static void gen_opcode (unsigned long int opcode) genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); start_brace (); - printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);\n"); genflags (flag_subx, curi->size, "newv", "src", "dst"); genflags (flag_zn, curi->size, "newv", "", ""); genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); @@ -935,14 +935,14 @@ static void gen_opcode (unsigned long int opcode) genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); start_brace (); - printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);\n"); printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n"); printf ("\tuae_u16 newv, tmp_newv;\n"); printf ("\tint bcd = 0;\n"); printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n"); printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n"); - printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n"); - printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n"); + printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n"); + printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);\n"); duplicate_carry (); /* Manual says bits NV are undefined though a real 68040 don't change them */ if (cpu_level >= xBCD_KEEPS_NV_FLAGS) { @@ -974,7 +974,7 @@ static void gen_opcode (unsigned long int opcode) genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); start_brace (); - printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);\n"); genflags (flag_addx, curi->size, "newv", "src", "dst"); genflags (flag_zn, curi->size, "newv", "", ""); genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); @@ -983,7 +983,7 @@ static void gen_opcode (unsigned long int opcode) genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); start_brace (); - printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);\n"); printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n"); printf ("\tuae_u16 newv, tmp_newv;\n"); printf ("\tint cflg;\n"); @@ -1014,7 +1014,7 @@ static void gen_opcode (unsigned long int opcode) case i_NEGX: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); start_brace (); - printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);\n"); genflags (flag_subx, curi->size, "newv", "src", "0"); genflags (flag_zn, curi->size, "newv", "", ""); genastore ("newv", curi->smode, "srcreg", curi->size, "src"); @@ -1022,7 +1022,7 @@ static void gen_opcode (unsigned long int opcode) case i_NBCD: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); start_brace (); - printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n"); + printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);\n"); printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n"); printf ("\tuae_u16 newv;\n"); printf ("\tint cflg;\n"); @@ -1295,7 +1295,7 @@ static void gen_opcode (unsigned long int opcode) break; case i_TRAPV: sync_m68k_pc (); - printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc()); goto %s; }\n", endlabelstr); + printf ("\tif (GET_VFLG()) { Exception(7,m68k_getpc()); goto %s; }\n", endlabelstr); need_endlabel = 1; break; case i_RTR: @@ -1505,7 +1505,7 @@ static void gen_opcode (unsigned long int opcode) } printf ("\tSET_ZFLG (upper == reg || lower == reg);\n"); printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n"); - printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr); + printf ("\tif ((extra & 0x800) && GET_CFLG()) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr); need_endlabel = 1; break; @@ -1521,7 +1521,7 @@ static void gen_opcode (unsigned long int opcode) } printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1); printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); printf ("\t\tval = %s & (uae_u32)-(uae_s32)sign;\n", bit_mask (curi->size)); printf ("\t\tSET_CFLG (sign);\n"); @@ -1553,7 +1553,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); printf ("\t\tSET_VFLG (val != 0);\n"); printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", @@ -1589,7 +1589,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n", bit_size (curi->size), bit_size (curi->size) - 1); @@ -1618,7 +1618,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); printf ("\tif (cnt >= %d) {\n", bit_size (curi->size)); printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size)); @@ -1648,7 +1648,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); if (source_is_imm1_8 (curi)) printf ("{"); else @@ -1675,7 +1675,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); if (source_is_imm1_8 (curi)) printf ("{"); else @@ -1702,7 +1702,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); if (source_is_imm1_8 (curi)) printf ("{"); else { @@ -1713,11 +1713,11 @@ static void gen_opcode (unsigned long int opcode) printf ("\t{\n\tuae_u32 carry;\n"); printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1); printf ("\tcarry = loval & 1;\n"); - printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n"); + printf ("\tval = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);\n"); printf ("\tSET_XFLG (carry);\n"); printf ("\tval &= %s;\n", bit_mask (curi->size)); printf ("\t} }\n"); - printf ("\tSET_CFLG (GET_XFLG);\n"); + printf ("\tSET_CFLG (GET_XFLG());\n"); genflags (flag_logical_noclobber, curi->size, "val", "", ""); genastore ("val", curi->dmode, "dstreg", curi->size, "data"); break; @@ -1732,7 +1732,7 @@ static void gen_opcode (unsigned long int opcode) default: abort (); } printf ("\tcnt &= 63;\n"); - printf ("\tCLEAR_CZNV;\n"); + printf ("\tCLEAR_CZNV();\n"); if (source_is_imm1_8 (curi)) printf ("{"); else { @@ -1741,7 +1741,7 @@ static void gen_opcode (unsigned long int opcode) } printf ("\tcnt--;\n"); printf ("\t{\n\tuae_u32 carry;\n"); - printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n"); + printf ("\tuae_u32 hival = (val << 1) | GET_XFLG();\n"); printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1); printf ("\tval >>= cnt;\n"); printf ("\tcarry = val & 1;\n"); @@ -1750,7 +1750,7 @@ static void gen_opcode (unsigned long int opcode) printf ("\tSET_XFLG (carry);\n"); printf ("\tval &= %s;\n", bit_mask (curi->size)); printf ("\t} }\n"); - printf ("\tSET_CFLG (GET_XFLG);\n"); + printf ("\tSET_CFLG (GET_XFLG());\n"); genflags (flag_logical_noclobber, curi->size, "val", "", ""); genastore ("val", curi->dmode, "dstreg", curi->size, "data"); break; @@ -1788,7 +1788,7 @@ static void gen_opcode (unsigned long int opcode) printf ("\tSET_CFLG (sign != 0);\n"); duplicate_carry (); - printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n"); + printf ("\tSET_VFLG (GET_VFLG() | (sign2 != sign));\n"); genastore ("val", curi->smode, "srcreg", curi->size, "data"); break; case i_LSRW: @@ -1866,7 +1866,7 @@ static void gen_opcode (unsigned long int opcode) } printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size)); printf ("\tval <<= 1;\n"); - printf ("\tif (GET_XFLG) val |= 1;\n"); + printf ("\tif (GET_XFLG()) val |= 1;\n"); genflags (flag_logical, curi->size, "val", "", ""); printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1); duplicate_carry (); @@ -1883,7 +1883,7 @@ static void gen_opcode (unsigned long int opcode) } printf ("\tuae_u32 carry = val & 1;\n"); printf ("\tval >>= 1;\n"); - printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size)); + printf ("\tif (GET_XFLG()) val |= %s;\n", cmask (curi->size)); genflags (flag_logical, curi->size, "val", "", ""); printf ("SET_CFLG (carry);\n"); duplicate_carry (); @@ -1912,7 +1912,7 @@ static void gen_opcode (unsigned long int opcode) printf ("\tint ru = (src >> 6) & 7;\n"); printf ("\tint rc = src & 7;\n"); genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst"); - printf ("\tif (GET_ZFLG)"); + printf ("\tif (GET_ZFLG())"); old_brace_level = n_braces; start_brace (); genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst"); @@ -1931,14 +1931,14 @@ static void gen_opcode (unsigned long int opcode) int old_brace_level = n_braces; printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n"); genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1"); - printf ("\tif (GET_ZFLG) {\n"); + printf ("\tif (GET_ZFLG()) {\n"); genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2"); - printf ("\tif (GET_ZFLG) {\n"); + printf ("\tif (GET_ZFLG()) {\n"); printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n"); printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n"); printf ("\t}}\n"); pop_braces (old_brace_level); - printf ("\tif (! GET_ZFLG) {\n"); + printf ("\tif (! GET_ZFLG()) {\n"); printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n"); printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n"); printf ("\t}\n"); @@ -1946,14 +1946,14 @@ static void gen_opcode (unsigned long int opcode) int old_brace_level = n_braces; printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n"); genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1"); - printf ("\tif (GET_ZFLG) {\n"); + printf ("\tif (GET_ZFLG()) {\n"); genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2"); - printf ("\tif (GET_ZFLG) {\n"); + printf ("\tif (GET_ZFLG()) {\n"); printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n"); printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n"); printf ("\t}}\n"); pop_braces (old_brace_level); - printf ("\tif (! GET_ZFLG) {\n"); + printf ("\tif (! GET_ZFLG()) {\n"); printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n"); printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n"); printf ("\t}\n"); @@ -2053,7 +2053,7 @@ static void gen_opcode (unsigned long int opcode) printf ("\ttmp = ~tmp;\n"); break; case i_BFEXTS: - printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n"); + printf ("\tif (GET_NFLG()) tmp |= width == 32 ? 0 : (-1 << width);\n"); printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n"); break; case i_BFCLR: @@ -2185,18 +2185,40 @@ static void gen_opcode (unsigned long int opcode) printf ("\tfpuop_restore(opcode);\n"); break; case i_CINVL: + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); + break; case i_CINVP: + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); + break; case i_CINVA: - /* gb-- srcreg now contains the cache field */ - printf ("\tif (srcreg&0x2)\n"); - printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3)); + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); break; case i_CPUSHL: + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); + break; case i_CPUSHP: + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); + break; case i_CPUSHA: - /* gb-- srcreg now contains the cache field */ - printf ("\tif (srcreg&0x2)\n"); - printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3)); + printf("\n#ifdef USE_JIT\n"); + printf ("\tif (opcode&0x80)\n" + "\t\tflush_icache();\n"); + printf("#endif\n"); break; case i_MOVE16: if ((opcode & 0xfff8) == 0xf620) { diff --git a/BasiliskII/src/uae_cpu/m68k.h b/BasiliskII/src/uae_cpu/m68k.h index f329cb3e..d4d28484 100644 --- a/BasiliskII/src/uae_cpu/m68k.h +++ b/BasiliskII/src/uae_cpu/m68k.h @@ -25,67 +25,108 @@ #ifdef OPTIMIZED_FLAGS -#if defined(X86_ASSEMBLY) || defined(X86_64_ASSEMBLY) || defined(MSVC_INTRINSICS) +#if (defined(CPU_i386) && defined(X86_ASSEMBLY)) || (defined(CPU_x86_64) && defined(X86_64_ASSEMBLY)) + +# include #ifndef SAHF_SETO_PROFITABLE +/* + * Machine dependent structure for holding the 68k CCR flags + */ /* PUSH/POP instructions are naturally 64-bit sized on x86-64, thus unsigned long hereunder is either 64-bit or 32-bit wide depending on the target. */ struct flag_struct { - unsigned long cznv; - unsigned long x; +#if defined(CPU_x86_64) + uint64 cznv; + uint64 x; +#else + uint32 cznv; + uint32 x; +#endif }; -#define FLAGVAL_Z 0x40 -#define FLAGVAL_N 0x80 +/* + * The bits in the cznv field in the above structure are assigned to + * allow the easy mirroring of the x86 rFLAGS register. + * + * The 68k CZNV flags are thus assigned in cznv as: + * + * 76543210 FEDCBA98 --------- --------- + * SZxxxxxC xxxxVxxx xxxxxxxxx xxxxxxxxx + */ -#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x40) | (((y) & 1) << 6)) -#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~1) | ((y) & 1)) -#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x800) | (((y) & 1) << 11)) -#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~0x80) | (((y) & 1) << 7)) -#define SET_XFLG(y) (regflags.x = (y)) +#define FLAGBIT_N 7 +#define FLAGBIT_Z 6 +#define FLAGBIT_C 0 +#define FLAGBIT_V 11 +#define FLAGBIT_X 0 /* must be in position 0 for duplicate_carry() to work */ -#define GET_ZFLG ((regflags.cznv >> 6) & 1) -#define GET_CFLG (regflags.cznv & 1) -#define GET_VFLG ((regflags.cznv >> 11) & 1) -#define GET_NFLG ((regflags.cznv >> 7) & 1) -#define GET_XFLG (regflags.x & 1) +#define FLAGVAL_N (1 << FLAGBIT_N) +#define FLAGVAL_Z (1 << FLAGBIT_Z) +#define FLAGVAL_C (1 << FLAGBIT_C) +#define FLAGVAL_V (1 << FLAGBIT_V) +#define FLAGVAL_X (1 << FLAGBIT_X) -#define CLEAR_CZNV (regflags.cznv = 0) -#define GET_CZNV (regflags.cznv) -#define IOR_CZNV(X) (regflags.cznv |= (X)) -#define SET_CZNV(X) (regflags.cznv = (X)) +#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z)) +#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C)) +#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V)) +#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N)) +#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X) -#define COPY_CARRY (regflags.x = regflags.cznv) +#define GET_ZFLG() ((regflags.cznv >> FLAGBIT_Z) & 1) +#define GET_CFLG() ((regflags.cznv >> FLAGBIT_C) & 1) +#define GET_VFLG() ((regflags.cznv >> FLAGBIT_V) & 1) +#define GET_NFLG() ((regflags.cznv >> FLAGBIT_N) & 1) +#define GET_XFLG() ((regflags.x >> FLAGBIT_X) & 1) -extern struct flag_struct regflags ASM_SYM ("regflags"); +#define CLEAR_CZNV() (regflags.cznv = 0) +#define GET_CZNV() (regflags.cznv) +#define IOR_CZNV(X) (regflags.cznv |= (X)) +#define SET_CZNV(X) (regflags.cznv = (X)) -static __inline__ int cctrue(int cc) +#define COPY_CARRY() (regflags.x = regflags.cznv >> (FLAGBIT_C - FLAGBIT_X)) + +extern struct flag_struct regflags __asm__ ("regflags"); + +/* + * Test CCR condition + */ +static inline int cctrue(int cc) { uae_u32 cznv = regflags.cznv; - switch(cc){ - case 0: return 1; /* T */ - case 1: return 0; /* F */ - case 2: return (cznv & 0x41) == 0; /* !GET_CFLG && !GET_ZFLG; HI */ - case 3: return (cznv & 0x41) != 0; /* GET_CFLG || GET_ZFLG; LS */ - case 4: return (cznv & 1) == 0; /* !GET_CFLG; CC */ - case 5: return (cznv & 1) != 0; /* GET_CFLG; CS */ - case 6: return (cznv & 0x40) == 0; /* !GET_ZFLG; NE */ - case 7: return (cznv & 0x40) != 0; /* GET_ZFLG; EQ */ - case 8: return (cznv & 0x800) == 0;/* !GET_VFLG; VC */ - case 9: return (cznv & 0x800) != 0;/* GET_VFLG; VS */ - case 10:return (cznv & 0x80) == 0; /* !GET_NFLG; PL */ - case 11:return (cznv & 0x80) != 0; /* GET_NFLG; MI */ - case 12:return (((cznv << 4) ^ cznv) & 0x800) == 0; /* GET_NFLG == GET_VFLG; GE */ - case 13:return (((cznv << 4) ^ cznv) & 0x800) != 0;/* GET_NFLG != GET_VFLG; LT */ - case 14: - cznv &= 0x8c0; - return (((cznv << 4) ^ cznv) & 0x840) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG); GT */ - case 15: - cznv &= 0x8c0; - return (((cznv << 4) ^ cznv) & 0x840) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG); LE */ + + switch (cc) { + case 0: return 1; /* T */ + case 1: return 0; /* F */ + case 2: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !CFLG && !ZFLG HI */ + case 3: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* CFLG || ZFLG LS */ + case 4: return (cznv & FLAGVAL_C) == 0; /* !CFLG CC */ + case 5: return (cznv & FLAGVAL_C) != 0; /* CFLG CS */ + case 6: return (cznv & FLAGVAL_Z) == 0; /* !ZFLG NE */ + case 7: return (cznv & FLAGVAL_Z) != 0; /* ZFLG EQ */ + case 8: return (cznv & FLAGVAL_V) == 0; /* !VFLG VC */ + case 9: return (cznv & FLAGVAL_V) != 0; /* VFLG VS */ + case 10: return (cznv & FLAGVAL_N) == 0; /* !NFLG PL */ + case 11: return (cznv & FLAGVAL_N) != 0; /* NFLG MI */ +#if FLAGBIT_N > FLAGBIT_V + case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0; /* NFLG == VFLG GE */ + case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0; /* NFLG != VFLG LT */ + case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* !ZFLG && (NFLG == VFLG) GT */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; + case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG || (NFLG != VFLG) LE */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; +#else + case 12: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) == 0; /* NFLG == VFLG GE */ + case 13: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) != 0; /* NFLG != VFLG LT */ + case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* !ZFLG && (NFLG == VFLG) GT */ + return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) == 0; + case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG || (NFLG != VFLG) LE */ + return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) != 0; +#endif } + abort (); return 0; } @@ -93,34 +134,34 @@ static __inline__ int cctrue(int cc) __asm__ __volatile__ ("andl %1,%1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "r" (v) : "cc") + : "=rm" (regflags.cznv) : "r" (v) : "memory", "cc") #define optflag_testw(v) \ __asm__ __volatile__ ("andw %w1,%w1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "r" (v) : "cc") + : "=rm" (regflags.cznv) : "r" (v) : "memory", "cc") #define optflag_testb(v) \ __asm__ __volatile__ ("andb %b1,%b1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "q" (v) : "cc") + : "=rm" (regflags.cznv) : "q" (v) : "memory", "cc") #define optflag_addl(v, s, d) do { \ __asm__ __volatile__ ("addl %k2,%k1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + : "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \ + COPY_CARRY(); \ } while (0) #define optflag_addw(v, s, d) do { \ __asm__ __volatile__ ("addw %w2,%w1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + : "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \ + COPY_CARRY(); \ } while (0) #define optflag_addb(v, s, d) do { \ @@ -128,113 +169,151 @@ static __inline__ int cctrue(int cc) "pushf\n\t" \ "pop %0\n\t" \ : "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_subl(v, s, d) do { \ __asm__ __volatile__ ("subl %k2,%k1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + : "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \ + COPY_CARRY(); \ } while (0) #define optflag_subw(v, s, d) do { \ __asm__ __volatile__ ("subw %w2,%w1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + : "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \ + COPY_CARRY(); \ } while (0) #define optflag_subb(v, s, d) do { \ __asm__ __volatile__ ("subb %b2,%b1\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \ - COPY_CARRY; \ + : "=rm" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "memory", "cc"); \ + COPY_CARRY(); \ } while (0) #define optflag_cmpl(s, d) \ __asm__ __volatile__ ("cmpl %k1,%k2\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc") + : "=rm" (regflags.cznv) : "rmi" (s), "r" (d) : "memory", "cc") #define optflag_cmpw(s, d) \ __asm__ __volatile__ ("cmpw %w1,%w2\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc") + : "=rm" (regflags.cznv) : "rmi" (s), "r" (d) : "memory", "cc") #define optflag_cmpb(s, d) \ __asm__ __volatile__ ("cmpb %b1,%b2\n\t" \ "pushf\n\t" \ "pop %0\n\t" \ - : "=r" (regflags.cznv) : "qmi" (s), "q" (d) : "cc") + : "=rm" (regflags.cznv) : "qmi" (s), "q" (d) : "memory", "cc") -#else +#else /* !SAHF_SETO_PROFITABLE */ +/* + * Machine dependent structure for holding the 68k CCR flags + */ struct flag_struct { - uae_u32 cznv; - uae_u32 x; + uae_u32 cznv; + uae_u32 x; }; -#define FLAGVAL_Z 0x4000 -#define FLAGVAL_N 0x8000 +extern struct flag_struct regflags __asm__ ("regflags"); -#define SET_ZFLG(y) (regflags.cznv = (regflags.cznv & ~0x4000) | (((y) & 1) << 14)) -#define SET_CFLG(y) (regflags.cznv = (regflags.cznv & ~0x100) | (((y) & 1) << 8)) -#define SET_VFLG(y) (regflags.cznv = (regflags.cznv & ~0x1) | (((y) & 1))) -#define SET_NFLG(y) (regflags.cznv = (regflags.cznv & ~0x8000) | (((y) & 1) << 15)) -#define SET_XFLG(y) (regflags.x = (y)) +/* + * The bits in the cznv field in the above structure are assigned to + * allow the easy mirroring of the x86 condition flags. (For example, + * from the AX register - the x86 overflow flag can be copied to AL + * with a setto %AL instr and the other flags copied to AH with an + * lahf instr). + * + * The 68k CZNV flags are thus assigned in cznv as: + * + * <--AL--> <--AH--> + * 76543210 FEDCBA98 --------- --------- + * xxxxxxxV NZxxxxxC xxxxxxxxx xxxxxxxxx + */ -#define GET_ZFLG ((regflags.cznv >> 14) & 1) -#define GET_CFLG ((regflags.cznv >> 8) & 1) -#define GET_VFLG ((regflags.cznv >> 0) & 1) -#define GET_NFLG ((regflags.cznv >> 15) & 1) -#define GET_XFLG (regflags.x & 1) +#define FLAGBIT_N 15 +#define FLAGBIT_Z 14 +#define FLAGBIT_C 8 +#define FLAGBIT_V 0 +#define FLAGBIT_X 0 /* must be in position 0 for duplicate_carry() to work */ -#define CLEAR_CZNV (regflags.cznv = 0) -#define GET_CZNV (regflags.cznv) -#define IOR_CZNV(X) (regflags.cznv |= (X)) -#define SET_CZNV(X) (regflags.cznv = (X)) +#define FLAGVAL_N (1 << FLAGBIT_N) +#define FLAGVAL_Z (1 << FLAGBIT_Z) +#define FLAGVAL_C (1 << FLAGBIT_C) +#define FLAGVAL_V (1 << FLAGBIT_V) +#define FLAGVAL_X (1 << FLAGBIT_X) -#define COPY_CARRY (regflags.x = (regflags.cznv)>>8) +#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z)) +#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C)) +#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V)) +#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N)) +#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X) -extern struct flag_struct regflags ASM_SYM("regflags"); +#define GET_ZFLG() ((regflags.cznv >> FLAGBIT_Z) & 1) +#define GET_CFLG() ((regflags.cznv >> FLAGBIT_C) & 1) +#define GET_VFLG() ((regflags.cznv >> FLAGBIT_V) & 1) +#define GET_NFLG() ((regflags.cznv >> FLAGBIT_N) & 1) +#define GET_XFLG() ((regflags.x >> FLAGBIT_X) & 1) -static __inline__ int cctrue(int cc) +#define CLEAR_CZNV() (regflags.cznv = 0) +#define GET_CZNV() (regflags.cznv) +#define IOR_CZNV(X) (regflags.cznv |= (X)) +#define SET_CZNV(X) (regflags.cznv = (X)) + +#define COPY_CARRY() (regflags.x = regflags.cznv >> (FLAGBIT_C - FLAGBIT_X)) + + +/* + * Test CCR condition + */ +static inline int cctrue(int cc) { uae_u32 cznv = regflags.cznv; - switch(cc){ - case 0: return 1; /* T */ - case 1: return 0; /* F */ - case 2: return (cznv & 0x4100) == 0; /* !GET_CFLG && !GET_ZFLG; HI */ - case 3: return (cznv & 0x4100) != 0; /* GET_CFLG || GET_ZFLG; LS */ - case 4: return (cznv & 0x100) == 0; /* !GET_CFLG; CC */ - case 5: return (cznv & 0x100) != 0; /* GET_CFLG; CS */ - case 6: return (cznv & 0x4000) == 0; /* !GET_ZFLG; NE */ - case 7: return (cznv & 0x4000) != 0; /* GET_ZFLG; EQ */ - case 8: return (cznv & 0x01) == 0; /* !GET_VFLG; VC */ - case 9: return (cznv & 0x01) != 0; /* GET_VFLG; VS */ - case 10:return (cznv & 0x8000) == 0; /* !GET_NFLG; PL */ - case 11:return (cznv & 0x8000) != 0; /* GET_NFLG; MI */ - case 12:return (((cznv << 15) ^ cznv) & 0x8000) == 0; /* GET_NFLG == GET_VFLG; GE */ - case 13:return (((cznv << 15) ^ cznv) & 0x8000) != 0;/* GET_NFLG != GET_VFLG; LT */ - case 14: - cznv &= 0xc001; - return (((cznv << 15) ^ cznv) & 0xc000) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG); GT */ - case 15: - cznv &= 0xc001; - return (((cznv << 15) ^ cznv) & 0xc000) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG); LE */ + + switch (cc) { + case 0: return 1; /* T */ + case 1: return 0; /* F */ + case 2: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !CFLG && !ZFLG HI */ + case 3: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* CFLG || ZFLG LS */ + case 4: return (cznv & FLAGVAL_C) == 0; /* !CFLG CC */ + case 5: return (cznv & FLAGVAL_C) != 0; /* CFLG CS */ + case 6: return (cznv & FLAGVAL_Z) == 0; /* !ZFLG NE */ + case 7: return (cznv & FLAGVAL_Z) != 0; /* ZFLG EQ */ + case 8: return (cznv & FLAGVAL_V) == 0; /* !VFLG VC */ + case 9: return (cznv & FLAGVAL_V) != 0; /* VFLG VS */ + case 10: return (cznv & FLAGVAL_N) == 0; /* !NFLG PL */ + case 11: return (cznv & FLAGVAL_N) != 0; /* NFLG MI */ +#if FLAGBIT_N > FLAGBIT_V + case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0; /* NFLG == VFLG GE */ + case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0; /* NFLG != VFLG LT */ + case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* !ZFLG && (NFLG == VFLG) GT */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; + case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG || (NFLG != VFLG) LE */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; +#else + case 12: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) == 0; /* NFLG == VFLG GE */ + case 13: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) != 0; /* NFLG != VFLG LT */ + case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* !ZFLG && (NFLG == VFLG) GT */ + return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) == 0; + case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG || (NFLG != VFLG) LE */ + return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) != 0; +#endif } - abort(); + abort (); return 0; } /* Manually emit LAHF instruction so that 64-bit assemblers can grok it */ -#if defined __x86_64__ && defined __GNUC__ +#if defined CPU_x86_64 && defined __GNUC__ #define ASM_LAHF ".byte 0x9f" #else #define ASM_LAHF "lahf" @@ -273,7 +352,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_addw(v, s, d) do { \ @@ -283,7 +362,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_addb(v, s, d) do { \ @@ -293,7 +372,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=q" (v) : "qmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_subl(v, s, d) do { \ @@ -303,7 +382,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_subw(v, s, d) do { \ @@ -313,7 +392,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_subb(v, s, d) do { \ @@ -323,7 +402,7 @@ static __inline__ int cctrue(int cc) "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ : "=q" (v) : "qmi" (s), "0" (d) : "%eax","cc","memory"); \ - COPY_CARRY; \ + COPY_CARRY(); \ } while (0) #define optflag_cmpl(s, d) \ @@ -340,7 +419,7 @@ static __inline__ int cctrue(int cc) "seto %%al\n\t" \ "movb %%al,regflags\n\t" \ "movb %%ah,regflags+1\n\t" \ - : : "rmi" (s), "r" (d) : "%eax","cc","memory"); + : : "rmi" (s), "r" (d) : "%eax","cc","memory") #define optflag_cmpb(s, d) \ __asm__ __volatile__ ("cmpb %b0,%b1\n\t" \ @@ -350,10 +429,306 @@ static __inline__ int cctrue(int cc) "movb %%ah,regflags+1\n\t" \ : : "qmi" (s), "q" (d) : "%eax","cc","memory") +#endif /* SAHF_SETO_PROFITABLE */ + +#elif defined(CPU_arm) && defined(ARM_ASSEMBLY) + +/* + * Machine dependent structure for holding the 68k CCR flags + */ +struct flag_struct { + uae_u32 nzcv; + uae_u32 x; +}; + +#define FLAGBIT_N 31 +#define FLAGBIT_Z 30 +#define FLAGBIT_C 29 +#define FLAGBIT_V 28 +#define FLAGBIT_X FLAGBIT_C /* must be in the same position in as x flag */ + +#define FLAGVAL_N (1 << FLAGBIT_N) +#define FLAGVAL_Z (1 << FLAGBIT_Z) +#define FLAGVAL_C (1 << FLAGBIT_C) +#define FLAGVAL_V (1 << FLAGBIT_V) +#define FLAGVAL_X (1 << FLAGBIT_X) + +#define SET_NFLG(y) (regflags.nzcv = (regflags.nzcv & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N)) +#define SET_ZFLG(y) (regflags.nzcv = (regflags.nzcv & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z)) +#define SET_CFLG(y) (regflags.nzcv = (regflags.nzcv & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C)) +#define SET_VFLG(y) (regflags.nzcv = (regflags.nzcv & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V)) +#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X) + +#define GET_NFLG() ((regflags.nzcv >> FLAGBIT_N) & 1) +#define GET_ZFLG() ((regflags.nzcv >> FLAGBIT_Z) & 1) +#define GET_CFLG() ((regflags.nzcv >> FLAGBIT_C) & 1) +#define GET_VFLG() ((regflags.nzcv >> FLAGBIT_V) & 1) +#define GET_XFLG() ((regflags.x >> FLAGBIT_X) & 1) + +#define CLEAR_CZNV() (regflags.nzcv = 0) +#define GET_CZNV() (regflags.nzcv) +#define IOR_CZNV(X) (regflags.nzcv |= (X)) +#define SET_CZNV(X) (regflags.nzcv = (X)) + +#define COPY_CARRY() (regflags.x = regflags.nzcv >> (FLAGBIT_C - FLAGBIT_X)) + +extern struct flag_struct regflags __asm__ ("regflags"); + +/* + * Test CCR condition + */ +static inline int cctrue(int cc) +{ + unsigned int nzcv = regflags.nzcv; + switch(cc){ + case 0: return 1; /* T */ + case 1: return 0; /* F */ + case 2: return (nzcv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !GET_CFLG && !GET_ZFLG; HI */ + case 3: return (nzcv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* GET_CFLG || GET_ZFLG; LS */ + case 4: return (nzcv & FLAGVAL_C) == 0; /* !GET_CFLG; CC */ + case 5: return (nzcv & FLAGVAL_C) != 0; /* GET_CFLG; CS */ + case 6: return (nzcv & FLAGVAL_Z) == 0; /* !GET_ZFLG; NE */ + case 7: return (nzcv & FLAGVAL_Z) != 0; /* GET_ZFLG; EQ */ + case 8: return (nzcv & FLAGVAL_V) == 0; /* !GET_VFLG; VC */ + case 9: return (nzcv & FLAGVAL_V) != 0; /* GET_VFLG; VS */ + case 10:return (nzcv & FLAGVAL_N) == 0; /* !GET_NFLG; PL */ + case 11:return (nzcv & FLAGVAL_N) != 0; /* GET_NFLG; MI */ + case 12:return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & FLAGVAL_N) == 0; /* GET_NFLG == GET_VFLG; GE */ + case 13:return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & FLAGVAL_N) != 0; /* GET_NFLG != GET_VFLG; LT */ + case 14: nzcv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); + return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG); GT */ + case 15: nzcv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); + return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG); LE */ + } + return 0; +} + +#define optflag_testl(v) do {\ + __asm__ __volatile__ ("tst %[rv],%[rv]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "bic %[nzcv],#0x30000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rv] "r" (v) \ + : "cc"); \ + } while(0) + +#define optflag_addl(v, s, d) do { \ + __asm__ __volatile__ ("adds %[rv],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_subl(v, s, d) do { \ + __asm__ __volatile__ ("subs %[rv],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_cmpl(s, d) do { \ + __asm__ __volatile__ ("cmp %[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rs] "ri" (s), [rd] "0" (d) \ + : "cc"); \ + } while(0) + +#if defined(ARMV6_ASSEMBLY) + +// #pragma message "ARM/v6 Assembly optimized flags" + +#define optflag_testw(v) do { \ + __asm__ __volatile__ ("sxth %[rv],%[rv]\n\t" \ + "tst %[rv],%[rv]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "bic %[nzcv],#0x30000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rv] "0" (v) \ + : "cc"); \ + }while(0) + +#define optflag_testb(v) do {\ + __asm__ __volatile__ ("sxtb %[rv],%[rv]\n\t" \ + "tst %[rv],%[rv]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "bic %[nzcv],#0x30000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rv] "0" (v) \ + : "cc"); \ + }while(0) + +#define optflag_addw(v, s, d) do { \ + __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \ + "sxth %[rs],%[rs]\n\t" \ + "adds %[rd],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_addb(v, s, d) do { \ + __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \ + "sxtb %[rs],%[rs]\n\t" \ + "adds %[rd],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_subw(v, s, d) do { \ + __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \ + "sxth %[rs],%[rs]\n\t" \ + "subs %[rd],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_subb(v, s, d) do { \ + __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \ + "sxtb %[rs],%[rs]\n\t" \ + "subs %[rd],%[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_cmpw(s, d) do { \ + __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \ + "sxth %[rs],%[rs]\n\t" \ + "cmp %[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rs] "ri" (s), [rd] "0" (d) \ + : "cc"); \ + } while(0) + +#define optflag_cmpb(s, d) do { \ + __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \ + "sxtb %[rs],%[rs]\n\t" \ + "cmp %[rd],%[rs]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rs] "ri" (s), [rd] "0" (d) \ + : "cc"); \ + } while(0) + +#else + +// #pragma message "ARM/generic Assembly optimized flags" + +#define optflag_testw(v) do { \ + __asm__ __volatile__ ("lsl %[rv],%[rv],#16\n\t" \ + "tst %[rv],%[rv]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "bic %[nzcv],#0x30000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rv] "0" (v) \ + : "cc"); \ + }while(0) + +#define optflag_testb(v) do {\ + __asm__ __volatile__ ("lsl %[rv],%[rv],#24\n\t" \ + "tst %[rv],%[rv]\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "bic %[nzcv],#0x30000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rv] "0" (v) \ + : "cc"); \ + }while(0) + +#define optflag_addw(v, s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \ + "adds %[rd],%[rd],%[rs],lsl #16\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "lsr %[rv],%[rd],#16\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_addb(v, s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \ + "adds %[rd],%[rd],%[rs],lsl #24\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "lsr %[rv],%[rd],#24\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_subw(v, s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \ + "subs %[rd],%[rd],%[rs],lsl #16\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + "lsr %[rv],%[rd],#16\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_subb(v, s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \ + "subs %[rd],%[rd],%[rs],lsl #24\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + "lsr %[rv],%[rd],#24\n\t" \ + : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \ + : [rs] "ri" (s), [rd] "1" (d) \ + : "cc"); \ + COPY_CARRY(); \ + } while(0) + +#define optflag_cmpw(s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \ + "cmp %[rd],%[rs],lsl #16\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rs] "ri" (s), [rd] "0" (d) \ + : "cc"); \ + } while(0) + +#define optflag_cmpb(s, d) do { \ + __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \ + "cmp %[rd],%[rs],lsl #24\n\t" \ + "mrs %[nzcv],cpsr\n\t" \ + "eor %[nzcv],#0x20000000\n\t" \ + : [nzcv] "=r" (regflags.nzcv) \ + : [rs] "ri" (s), [rd] "0" (d) \ + : "cc"); \ + } while(0) + #endif -#elif defined(SPARC_V8_ASSEMBLY) || defined(SPARC_V9_ASSEMBLY) +#elif defined(CPU_sparc) && (defined(SPARC_V8_ASSEMBLY) || defined(SPARC_V9_ASSEMBLY)) +/* + * Machine dependent structure for holding the 68k CCR flags + */ struct flag_struct { unsigned char nzvc; unsigned char x; @@ -361,52 +736,62 @@ struct flag_struct { extern struct flag_struct regflags; -#define FLAGVAL_Z 0x04 -#define FLAGVAL_N 0x08 +#define FLAGBIT_N 3 +#define FLAGBIT_Z 2 +#define FLAGBIT_V 1 +#define FLAGBIT_C 0 +#define FLAGBIT_X FLAGBIT_C /* should be in the same position as the x flag */ -#define SET_ZFLG(y) (regflags.nzvc = (regflags.nzvc & ~0x04) | (((y) & 1) << 2)) -#define SET_CFLG(y) (regflags.nzvc = (regflags.nzvc & ~1) | ((y) & 1)) -#define SET_VFLG(y) (regflags.nzvc = (regflags.nzvc & ~0x02) | (((y) & 1) << 1)) -#define SET_NFLG(y) (regflags.nzvc = (regflags.nzvc & ~0x08) | (((y) & 1) << 3)) -#define SET_XFLG(y) (regflags.x = (y)) +#define FLAGVAL_N (1 << FLAGBIT_N) +#define FLAGVAL_Z (1 << FLAGBIT_Z) +#define FLAGVAL_C (1 << FLAGBIT_C) +#define FLAGVAL_V (1 << FLAGBIT_V) +#define FLAGVAL_X (1 << FLAGBIT_X) -#define GET_ZFLG ((regflags.nzvc >> 2) & 1) -#define GET_CFLG (regflags.nzvc & 1) -#define GET_VFLG ((regflags.nzvc >> 1) & 1) -#define GET_NFLG ((regflags.nzvc >> 3) & 1) -#define GET_XFLG (regflags.x & 1) +#define SET_ZFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z)) +#define SET_CFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C)) +#define SET_VFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V)) +#define SET_NFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_N)) +#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X) -#define CLEAR_CZNV (regflags.nzvc = 0) -#define GET_CZNV (reflags.nzvc) -#define IOR_CZNV(X) (refglags.nzvc |= (X)) -#define SET_CZNV(X) (regflags.nzvc = (X)) +#define GET_ZFLG() ((regflags.nzvc >> FLAGBIT_Z) & 1) +#define GET_CFLG() ((regflags.nzvc >> FLAGBIT_C) & 1) +#define GET_VFLG() ((regflags.nzvc >> FLAGBIT_V) & 1) +#define GET_NFLG() ((regflags.nzvc >> FLAGBIT_N) & 1) +#define GET_XFLG() ((regflags.x >> FLAGBIT_X) & 1) -#define COPY_CARRY (regflags.x = regflags.nzvc) +#define CLEAR_CZNV() (regflags.nzvc = 0) +#define GET_CZNV() (regflags.nzvc) +#define IOR_CZNV(X) (regflags.nzvc |= (X)) +#define SET_CZNV(X) (regflags.nzvc = (X)) -static __inline__ int cctrue(int cc) +#define COPY_CARRY() (regflags.x = regflags.nzvc >> (FLAGBIT_C - FLAGBIT_X)) + +/* + * Test CCR condition + */ +static inline int cctrue(int cc) { uae_u32 nzvc = regflags.nzvc; - switch(cc){ - case 0: return 1; /* T */ - case 1: return 0; /* F */ - case 2: return (nzvc & 0x05) == 0; /* !GET_CFLG && !GET_ZFLG; HI */ - case 3: return (nzvc & 0x05) != 0; /* GET_CFLG || GET_ZFLG; LS */ - case 4: return (nzvc & 1) == 0; /* !GET_CFLG; CC */ - case 5: return (nzvc & 1) != 0; /* GET_CFLG; CS */ - case 6: return (nzvc & 0x04) == 0; /* !GET_ZFLG; NE */ - case 7: return (nzvc & 0x04) != 0; /* GET_ZFLG; EQ */ - case 8: return (nzvc & 0x02) == 0;/* !GET_VFLG; VC */ - case 9: return (nzvc & 0x02) != 0;/* GET_VFLG; VS */ - case 10:return (nzvc & 0x08) == 0; /* !GET_NFLG; PL */ - case 11:return (nzvc & 0x08) != 0; /* GET_NFLG; MI */ - case 12:return (((nzvc << 2) ^ nzvc) & 0x08) == 0; /* GET_NFLG == GET_VFLG; GE */ - case 13:return (((nzvc << 2) ^ nzvc) & 0x08) != 0;/* GET_NFLG != GET_VFLG; LT */ - case 14: - nzvc &= 0x0e; - return (((nzvc << 2) ^ nzvc) & 0x0c) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG); GT */ - case 15: - nzvc &= 0x0e; - return (((nzvc << 2) ^ nzvc) & 0x0c) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG); LE */ + switch (cc) { + case 0: return 1; /* T */ + case 1: return 0; /* F */ + case 2: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !CFLG && !ZFLG HI */ + case 3: return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* CFLG || ZFLG LS */ + case 4: return (cznv & FLAGVAL_C) == 0; /* !CFLG CC */ + case 5: return (cznv & FLAGVAL_C) != 0; /* CFLG CS */ + case 6: return (cznv & FLAGVAL_Z) == 0; /* !ZFLG NE */ + case 7: return (cznv & FLAGVAL_Z) != 0; /* ZFLG EQ */ + case 8: return (cznv & FLAGVAL_V) == 0; /* !VFLG VC */ + case 9: return (cznv & FLAGVAL_V) != 0; /* VFLG VS */ + case 10: return (cznv & FLAGVAL_N) == 0; /* !NFLG PL */ + case 11: return (cznv & FLAGVAL_N) != 0; /* NFLG MI */ + case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0; /* NFLG == VFLG GE */ + case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0; /* NFLG != VFLG LT */ + case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG && (NFLG == VFLG) GT */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; + case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V); /* ZFLG && (NFLG != VFLG) LE */ + return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; } return 0; } @@ -1008,6 +1393,9 @@ static inline uae_u32 sparc_v9_flag_addx_32(flag_struct *flags, uae_u32 src, uae #else +/* + * Machine independent structure for holding the 68k CCR flags + */ struct flag_struct { unsigned int c; unsigned int z; @@ -1030,22 +1418,25 @@ extern struct flag_struct regflags; #define SET_ZFLG(x) (ZFLG = (x)) #define SET_XFLG(x) (XFLG = (x)) -#define GET_CFLG CFLG -#define GET_NFLG NFLG -#define GET_VFLG VFLG -#define GET_ZFLG ZFLG -#define GET_XFLG XFLG +#define GET_CFLG() CFLG +#define GET_NFLG() NFLG +#define GET_VFLG() VFLG +#define GET_ZFLG() ZFLG +#define GET_XFLG() XFLG -#define CLEAR_CZNV do { \ +#define CLEAR_CZNV() do { \ SET_CFLG (0); \ SET_ZFLG (0); \ SET_NFLG (0); \ SET_VFLG (0); \ } while (0) -#define COPY_CARRY (SET_XFLG (GET_CFLG)) +#define COPY_CARRY() (SET_XFLG (GET_CFLG ())) -static __inline__ int cctrue(const int cc) +/* + * Test CCR condition + */ +static inline int cctrue(const int cc) { switch(cc){ case 0: return 1; /* T */ diff --git a/BasiliskII/src/uae_cpu/newcpu.cpp b/BasiliskII/src/uae_cpu/newcpu.cpp index e981aa2b..dc109422 100644 --- a/BasiliskII/src/uae_cpu/newcpu.cpp +++ b/BasiliskII/src/uae_cpu/newcpu.cpp @@ -678,8 +678,8 @@ void MakeSR (void) #endif regs.sr = ((regs.t1 << 15) | (regs.t0 << 14) | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8) - | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1) - | GET_CFLG); + | (GET_XFLG() << 4) | (GET_NFLG() << 3) | (GET_ZFLG() << 2) | (GET_VFLG() << 1) + | GET_CFLG()); } void MakeFromSR (void) @@ -858,7 +858,7 @@ int m68k_move2c (int regno, uae_u32 *regp) #if USE_JIT set_cache_state(regs.cacr & 0x8000); if (*regp & 0x08) { /* Just to be on the safe side */ - flush_icache(1); + flush_icache(); } #endif break; @@ -1268,7 +1268,7 @@ void mmu_op(uae_u32 opcode, uae_u16 extra) /* PFLUSH */ mmusr = 0; #ifdef USE_JIT - flush_icache(0); + flush_icache(); #endif } else if ((opcode & 0x0FD8) == 0x548) { /* PTEST */ @@ -1501,7 +1501,7 @@ void m68k_dumpstate (uaecptr *nextpc) regs.usp,regs.isp,regs.msp,regs.vbr); printf ("T=%d%d S=%d M=%d X=%ld N=%ld Z=%ld V=%ld C=%ld IMASK=%d\n", regs.t1, regs.t0, regs.s, regs.m, - GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask); + GET_XFLG(), GET_NFLG(), GET_ZFLG(), GET_VFLG(), GET_CFLG(), regs.intmask); fpu_dump_registers(); fpu_dump_flags(); diff --git a/BasiliskII/src/uae_cpu/noflags.h b/BasiliskII/src/uae_cpu/noflags.h index eacbc214..e87d22b4 100644 --- a/BasiliskII/src/uae_cpu/noflags.h +++ b/BasiliskII/src/uae_cpu/noflags.h @@ -62,13 +62,13 @@ static __inline__ void SET_CFLG_ALWAYS(uae_u32 x) #define SET_XFLG(y) do {uae_u32 dummy=(y); } while (0) #undef CLEAR_CZNV -#define CLEAR_CZNV +#define CLEAR_CZNV() do {} while (0) #undef IOR_CZNV #define IOR_CZNV(y) do {uae_u32 dummy=(y); } while (0) #undef SET_CZNV #define SET_CZNV(y) do {uae_u32 dummy=(y); } while (0) #undef COPY_CARRY -#define COPY_CARRY +#define COPY_CARRY() do {} while (0) #ifdef optflag_testl #undef optflag_testl