Macintosh-Tools/macemu
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Now that we have AltiVec emulation, we can pretend for a G4 processor

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Also make sure to actually fix PVR code for 7400
This commit is contained in:
gbeauche 2004-02-15 17:20:36 +00:00
parent 313cddeeb2
commit 546f65a365
3 changed files with 8 additions and 17 deletions
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6
SheepShaver/src/Unix/main_unix.cpp
View File

@ -446,7 +446,9 @@ int main(int argc, char **argv)
PVR = 0x00040000; // Default: 604
CPUClockSpeed = 100000000; // Default: 100MHz
BusClockSpeed = 100000000; // Default: 100MHz
#if !EMULATED_PPC
#if EMULATED_PPC
PVR = 0x000c0000; // Default: 7400 (with AltiVec)
#else
proc_file = fopen("/proc/cpuinfo", "r");
if (proc_file) {
char line[256];
@ -482,7 +484,7 @@ int main(int argc, char **argv)
else if (strcmp(value, "860") == 0)
PVR = 0x00500000;
else if (strcmp(value, "7400") == 0)
PVR = 0x80000000;
PVR = 0x000c0000;
else if (strcmp(value, "7410") == 0)
PVR = 0x800c0000;
else

4
SheepShaver/src/name_registry.cpp
View File

@ -250,8 +250,8 @@ void DoPatchNameRegistry(void)
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
break;
case 0x8000: // 7400
case 0x800c: // 7410
case 12: // 7400, 7410
case 0x800c:
u32.set_value(32);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-block-size", u32.ptr(), 4);
u32.set_value(128);

15
SheepShaver/src/rom_patches.cpp
View File

@ -871,7 +871,8 @@ static bool patch_nanokernel_boot(void)
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
break;
// case 11: // X704?
case 12: // ???
case 12: // 7400, 7410
case 0x800c:
lp[0] = htonl(0x1000); // Page size
lp[1] = htonl(0x8000); // Data cache size
lp[2] = htonl(0x8000); // Inst cache size
@ -906,18 +907,6 @@ static bool patch_nanokernel_boot(void)
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
break;
case 0x8000: // 7400
case 0x800c: // 7410
lp[0] = htonl(0x1000); // Page size
lp[1] = htonl(0x8000); // Data cache size
lp[2] = htonl(0x8000); // Inst cache size
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
break;
default:
printf("WARNING: Unknown CPU type\n");
break;