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We need at least for native registers, hence we are guaranteed to have

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REG_T2 available. Add 16/32 sign-extension in T1. Add call generators
with (T0, T1) and (T0, T1, T2) arguments.
This commit is contained in:
gbeauche 2004-01-24 11:18:29 +00:00
parent 93c472ec0a
commit 6a4463b8fb
4 changed files with 50 additions and 2 deletions
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25
SheepShaver/src/kpx_cpu/src/cpu/jit/basic-dyngen-ops.cpp
View File

@ -179,6 +179,7 @@ DEFINE_OP(ror_32_T0_im, T0 = do_ror_32(T0, PARAM1));
// Sign-/Zero-extension
DEFINE_OP(se_16_32_T0, T0 = (int32)(int16)T0);
DEFINE_OP(se_16_32_T1, T1 = (int32)(int16)T1);
DEFINE_OP(ze_16_32_T0, T0 = (uint32)(uint16)T0);
DEFINE_OP(se_8_32_T0, T0 = (int32)(int8)T0);
DEFINE_OP(ze_8_32_T0, T0 = (uint32)(uint8)T0);
@ -483,6 +484,18 @@ DEFINE_OP(op_invoke_T0, {
CALL(func(T0));
});
DEFINE_OP(op_invoke_T0_T1, {
typedef void (*func_t)(uint32, uint32);
func_t func = (func_t)reg_A0;
CALL(func(T0, T1));
});
DEFINE_OP(op_invoke_T0_T1_T2, {
typedef void (*func_t)(uint32, uint32, uint32);
func_t func = (func_t)reg_A0;
CALL(func(T0, T1, T2));
});
DEFINE_OP(op_invoke_im, {
typedef void (*func_t)(uint32);
func_t func = (func_t)reg_A0;
@ -525,6 +538,18 @@ DEFINE_OP(op_invoke_direct_T0, {
CALL(func(T0));
});
DEFINE_OP(op_invoke_direct_T0_T1, {
typedef void (*func_t)(uint32, uint32);
func_t func = (func_t)PARAM1;
CALL(func(T0, T1));
});
DEFINE_OP(op_invoke_direct_T0_T1_T2, {
typedef void (*func_t)(uint32, uint32, uint32);
func_t func = (func_t)PARAM1;
CALL(func(T0, T1, T2));
});
DEFINE_OP(op_invoke_direct_im, {
typedef void (*func_t)(uint32);
func_t func = (func_t)PARAM1;

22
SheepShaver/src/kpx_cpu/src/cpu/jit/basic-dyngen.cpp
View File

@ -59,6 +59,28 @@ basic_dyngen::gen_invoke_T0(void (*func)(uint32))
}
}
void
basic_dyngen::gen_invoke_T0_T1(void (*func)(uint32, uint32))
{
if (direct_call_possible((uintptr)func))
gen_op_invoke_direct_T0_T1((uintptr)func);
else {
gen_op_mov_ad_A0_im((uintptr)func);
gen_op_invoke_T0_T1();
}
}
void
basic_dyngen::gen_invoke_T0_T1_T2(void (*func)(uint32, uint32, uint32))
{
if (direct_call_possible((uintptr)func))
gen_op_invoke_direct_T0_T1_T2((uintptr)func);
else {
gen_op_mov_ad_A0_im((uintptr)func);
gen_op_invoke_T0_T1_T2();
}
}
void
basic_dyngen::gen_invoke_im(void (*func)(uint32), uint32 value)
{

3
SheepShaver/src/kpx_cpu/src/cpu/jit/basic-dyngen.hpp
View File

@ -77,6 +77,8 @@ public:
void gen_jmp(const uint8 *target);
void gen_invoke(void (*func)(void));
void gen_invoke_T0(void (*func)(uint32));
void gen_invoke_T0_T1(void (*func)(uint32, uint32));
void gen_invoke_T0_T1_T2(void (*func)(uint32, uint32, uint32));
void gen_invoke_im(void (*func)(uint32), uint32 value);
void gen_invoke_CPU(void (*func)(dyngen_cpu_base));
void gen_invoke_CPU_T0(void (*func)(dyngen_cpu_base, uint32));
@ -156,6 +158,7 @@ public:
// Sign-/Zero-extension
DEFINE_ALIAS(se_16_32_T0,0);
DEFINE_ALIAS(se_16_32_T1,0);
DEFINE_ALIAS(ze_16_32_T0,0);
DEFINE_ALIAS(se_8_32_T0,0);
DEFINE_ALIAS(ze_8_32_T0,0);

2
SheepShaver/src/kpx_cpu/src/cpu/jit/dyngen-exec.h
View File

@ -31,10 +31,8 @@
#define REG_T0_ID AREG1_ID
#define REG_T1 AREG2
#define REG_T1_ID AREG2_ID
#ifdef AREG3
#define REG_T2 AREG3
#define REG_T2_ID AREG3_ID
#endif
#ifdef AREG4
#define REG_T3 AREG4
#define REG_T3_ID AREG4_ID