mirror of
https://github.com/kanjitalk755/macemu.git
synced 2024-11-18 18:05:21 +00:00
Additions:
- MOVE16 (Ay)+,(xxx).L - MOVE16 (xxx).L,(Ay)+ - MOVE16 (Ay),(xxx).L - MOVE16 (xxx).L,(Ay) Fixes: - MOVE16 (Ax)+,(Ay)+ where x == y: address register shall be incremented only once - CINV, CPUSH: 'p' field matches correctly the instruction 'cache field'
This commit is contained in:
gbeauche
parent
53973d4b84
commit
7535a1042f
@ -107,6 +107,7 @@ int main(int argc, char **argv)
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case 'r': currbit = bitr; break;
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case 'R': currbit = bitR; break;
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case 'z': currbit = bitz; break;
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case 'p': currbit = bitp; break;
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default: abort();
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}
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if (!(bitmask & 1)) {
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@ -221,7 +221,8 @@ static void sync_m68k_pc (void)
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}
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/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
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* the calling routine handles Apdi and Aipi modes. */
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* the calling routine handles Apdi and Aipi modes.
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* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
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static void genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
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{
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start_brace ();
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@ -2452,15 +2453,34 @@ static void gen_opcode (unsigned long int opcode)
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case i_CPUSHA:
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break;
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case i_MOVE16:
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printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
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printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
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printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
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printf ("\tput_long(memd, get_long(mems));\n");
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printf ("\tput_long(memd+4, get_long(mems+4));\n");
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printf ("\tput_long(memd+8, get_long(mems+8));\n");
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printf ("\tput_long(memd+12, get_long(mems+12));\n");
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printf ("\tm68k_areg(regs, srcreg) += 16;\n");
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printf ("\tm68k_areg(regs, dstreg) += 16;\n");
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if ((opcode & 0xfff8) == 0xf620) {
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/* MOVE16 (Ax)+,(Ay)+ */
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printf ("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
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printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword());
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printf ("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
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printf ("\tput_long(memd, get_long(mems));\n");
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printf ("\tput_long(memd+4, get_long(mems+4));\n");
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printf ("\tput_long(memd+8, get_long(mems+8));\n");
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printf ("\tput_long(memd+12, get_long(mems+12));\n");
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printf ("\tif (srcreg != dstreg)\n");
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printf ("\tm68k_areg(regs, srcreg) += 16;\n");
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printf ("\tm68k_areg(regs, dstreg) += 16;\n");
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}
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else {
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/* Other variants */
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genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2);
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genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2);
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printf ("\tmemsa &= ~15;\n");
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printf ("\tmemda &= ~15;\n");
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printf ("\tput_long(memda, get_long(memsa));\n");
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printf ("\tput_long(memda+4, get_long(memsa+4));\n");
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printf ("\tput_long(memda+8, get_long(memsa+8));\n");
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printf ("\tput_long(memda+12, get_long(memsa+12));\n");
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if ((opcode & 0xfff8) == 0xf600)
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printf ("\tm68k_areg(regs, srcreg) += 16;\n");
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else if ((opcode & 0xfff8) == 0xf608)
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printf ("\tm68k_areg(regs, dstreg) += 16;\n");
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}
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break;
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case i_MMUOP:
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genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
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@ -2523,6 +2543,7 @@ static void generate_one_opcode (int rp)
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case 3: smsk = 7; break;
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case 4: smsk = 7; break;
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case 5: smsk = 63; break;
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case 7: smsk = 3; break;
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default: abort ();
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}
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dmsk = 7;
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@ -339,6 +339,7 @@ static void build_insn (int insn)
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case 'A':
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srcmode = Areg;
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switch (opcstr[pos++]) {
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case 'l': srcmode = absl; break;
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case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
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case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
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default: abort();
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@ -393,6 +394,14 @@ static void build_insn (int insn)
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srcpos = bitpos[bitK];
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}
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break;
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case 'p': srcmode = immi; srcreg = bitval[bitp];
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if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ??
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/* 0..3 */
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srcgather = 1;
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srctype = 7;
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srcpos = bitpos[bitp];
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}
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break;
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default: abort();
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}
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break;
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@ -521,6 +530,7 @@ static void build_insn (int insn)
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case 'A':
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destmode = Areg;
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switch (opcstr[pos++]) {
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case 'l': destmode = absl; break;
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case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
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case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
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default: abort();
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@ -747,6 +757,8 @@ static void handle_merges (long int opcode)
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smsk = 7; sbitdst = 8; break;
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case 5:
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smsk = 63; sbitdst = 64; break;
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case 7:
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smsk = 3; sbitdst = 4; break;
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default:
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smsk = 0; sbitdst = 0;
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abort();
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@ -54,7 +54,7 @@ ENUMDECL {
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ENUMDECL {
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bit0, bit1, bitc, bitC, bitf, biti, bitI, bitj, bitJ, bitk, bitK,
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bits, bitS, bitd, bitD, bitr, bitR, bitz, lastbit
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bits, bitS, bitd, bitD, bitr, bitR, bitz, bitp, lastbit
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} ENUMNAME (bitvals);
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struct instr_def {
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@ -9,6 +9,7 @@
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% J: immediate 0..15
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% k: immediate 0..7
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% K: immediate 0..63
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% p: immediate 0..3 (CINV and CPUSH: cache field)
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% s: source mode
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% S: source reg
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% d: dest mode
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@ -24,6 +25,7 @@
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%
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% Arp: --> -(Ar)
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% ArP: --> (Ar)+
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% Al : --> (xxx).L
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%
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% Fields on a line:
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% 16 chars bitpattern :
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@ -248,10 +250,14 @@
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1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
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% 68040 instructions
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1111 0100 ii00 1rrr:42:-----:-----:02: CINVL #i,Ar
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1111 0100 ii01 0rrr:42:-----:-----:02: CINVP #i,Ar
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1111 0100 ii01 1rrr:42:-----:-----:00: CINVA #i
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1111 0100 ii10 1rrr:42:-----:-----:02: CPUSHL #i,Ar
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1111 0100 ii11 0rrr:42:-----:-----:02: CPUSHP #i,Ar
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1111 0100 ii11 1rrr:42:-----:-----:00: CPUSHA #i
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1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar
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1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar
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1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p
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1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar
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1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar
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1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p
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1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,ARP
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],Al
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Areg-Aipi]
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],Al
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Aipi-Aind]
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