mirror of
https://github.com/kanjitalk755/macemu.git
synced 2025-01-05 14:32:15 +00:00
Improve FPU emulation accurracy. However, PPC_ENABLE_FPU_EXCEPTIONS is still
set to 0 until generated code is optimized enough (current slow down factor
is 3x vs. previous core, expectations are about 50% slower FP code).
The main benefit is exception bits are accurate. All glibc test-fenv,
test-arith{,f}, test-double, test-float pass on ppc, and mostly on x86_64
with gcc 4.0.1. Yes, this is also compiler dependent.
FIXME: find a real Mac application that depends on precise FPSCR bits... I
think I don't want to care optimizing yet until someone shows me a real world
application.
This commit is contained in:
gbeauche
parent
0a74d0559a
commit
7efab4276f
@ -127,7 +127,7 @@ protected:
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{ record_cr(0, value); }
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void record_cr1()
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{ cr().set((cr().get() & ~CR_field<1>::mask()) | ((fpscr() >> 4) & 0x0f000000)); }
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void record_fpscr();
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void record_fpscr(int exceptions);
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void record_cr6(powerpc_vr const & vS, bool check_one) {
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if (check_one && (vS.j[0] == UVAL64(0xffffffffffffffff) &&
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vS.j[1] == UVAL64(0xffffffffffffffff)))
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@ -442,28 +442,31 @@ void powerpc_cpu::execute_multiply(uint32 opcode)
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* Update FP exception bits
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**/
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void powerpc_cpu::record_fpscr()
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void powerpc_cpu::record_fpscr(int exceptions)
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{
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#if PPC_ENABLE_FPU_EXCEPTIONS
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// Reset non-sticky bits
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fpscr() &= ~(FPSCR_VX_field::mask() | FPSCR_FEX_field::mask());
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// Always update FX if exception bits changed
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if (exceptions)
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fpscr() |= FPSCR_FX_field::mask() | exceptions;
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// Always update VX
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if (fpscr() & (FPSCR_VXSNAN_field::mask() | FPSCR_VXISI_field::mask() | \
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FPSCR_VXISI_field::mask() | FPSCR_VXIDI_field::mask() | \
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FPSCR_VXZDZ_field::mask() | FPSCR_VXIMZ_field::mask() | \
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FPSCR_VXVC_field::mask() | FPSCR_VXSOFT_field::mask() | \
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if (fpscr() & (FPSCR_VXSNAN_field::mask() | FPSCR_VXISI_field::mask() |
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FPSCR_VXISI_field::mask() | FPSCR_VXIDI_field::mask() |
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FPSCR_VXZDZ_field::mask() | FPSCR_VXIMZ_field::mask() |
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FPSCR_VXVC_field::mask() | FPSCR_VXSOFT_field::mask() |
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FPSCR_VXSQRT_field::mask() | FPSCR_VXCVI_field::mask()))
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fpscr() |= FPSCR_VX_field::mask();
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else
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fpscr() &= ~FPSCR_VX_field::mask();
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// Always update FEX
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if (((fpscr() & FPSCR_VX_field::mask()) && (fpscr() & FPSCR_VE_field::mask())) \
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|| ((fpscr() & FPSCR_OX_field::mask()) && (fpscr() & FPSCR_OE_field::mask())) \
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|| ((fpscr() & FPSCR_UX_field::mask()) && (fpscr() & FPSCR_UE_field::mask())) \
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|| ((fpscr() & FPSCR_ZX_field::mask()) && (fpscr() & FPSCR_ZE_field::mask())) \
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|| ((fpscr() & FPSCR_XX_field::mask()) && (fpscr() & FPSCR_XE_field::mask())))
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if (((fpscr() & FPSCR_VX_field::mask()) && (fpscr() & FPSCR_VE_field::mask())) ||
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((fpscr() & FPSCR_OX_field::mask()) && (fpscr() & FPSCR_OE_field::mask())) ||
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((fpscr() & FPSCR_UX_field::mask()) && (fpscr() & FPSCR_UE_field::mask())) ||
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((fpscr() & FPSCR_ZX_field::mask()) && (fpscr() & FPSCR_ZE_field::mask())) ||
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((fpscr() & FPSCR_XX_field::mask()) && (fpscr() & FPSCR_XE_field::mask())))
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fpscr() |= FPSCR_FEX_field::mask();
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else
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fpscr() &= ~FPSCR_FEX_field::mask();
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#endif
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}
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@ -487,53 +490,38 @@ void powerpc_cpu::execute_fp_arith(uint32 opcode)
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const double b = RB::get(this, opcode);
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const double c = RC::get(this, opcode);
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// Check for FP Exception Conditions
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#if PPC_ENABLE_FPU_EXCEPTIONS
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int exceptions = 0;
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int exceptions;
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if (FPSCR) {
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exceptions = op_apply<uint32, fp_exception_condition<OP>, RA, RB, RC>::apply(a, b, c);
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feclearexcept(FE_ALL_EXCEPT);
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febarrier();
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}
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#endif
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FP d = op_apply<double, OP, RA, RB, RC>::apply(a, b, c);
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#if PPC_ENABLE_FPU_EXCEPTIONS
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if (FPSCR) {
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// Check exceptions raised
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int masked = 0xffffffff;
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int raised = fetestexcept(FE_ALL_EXCEPT);
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if (raised & FE_INEXACT) {
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exceptions |= FPSCR_XX_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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if (raised & FE_DIVBYZERO) {
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exceptions |= FPSCR_ZX_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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else masked &= ~FPSCR_ZX_field::mask();
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if (raised & FE_UNDERFLOW) {
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exceptions |= FPSCR_UX_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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else masked &= ~FPSCR_UX_field::mask();
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if (raised & FE_OVERFLOW) {
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exceptions |= FPSCR_OX_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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else masked &= ~FPSCR_OX_field::mask();
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fpscr() &= masked;
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fpscr() |= exceptions;
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// Update FPSCR exception bits
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record_fpscr();
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#if PPC_ENABLE_FPU_EXCEPTIONS
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febarrier();
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int raised = fetestexcept(FE_ALL_EXCEPT);
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if (raised & FE_INEXACT)
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exceptions |= FPSCR_XX_field::mask();
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if (raised & FE_DIVBYZERO)
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exceptions |= FPSCR_ZX_field::mask();
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if (raised & FE_UNDERFLOW)
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exceptions |= FPSCR_UX_field::mask();
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if (raised & FE_OVERFLOW)
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exceptions |= FPSCR_OX_field::mask();
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record_fpscr(exceptions);
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#endif
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// FPSCR[FPRF] is set to the class and sign of the result
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if (!exceptions || !FPSCR_VE_field::test(fpscr()))
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if (!FPSCR_VE_field::test(fpscr()))
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fp_classify(d);
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}
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#endif
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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@ -806,24 +794,18 @@ void powerpc_cpu::execute_fp_compare(uint32 opcode)
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FPSCR_FPCC_field::insert(fpscr(), c);
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cr().set(crfd, c);
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// Check for FP exception condition
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#if PPC_ENABLE_FPU_EXCEPTIONS
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if (is_SNaN(a) || is_SNaN(b)) {
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fpscr() |= FPSCR_VXSNAN_field::mask();
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fpscr() |= FPSCR_FX_field::mask();
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if (OC && !FPSCR_VE_field::test(fpscr())) {
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fpscr() |= FPSCR_VXVC_field::mask();
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fpscr() |= FPSCR_FX_field::mask();
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}
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}
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else if (OC && (is_QNaN(a) || is_QNaN(b))) {
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fpscr() |= FPSCR_VXVC_field::mask();
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fpscr() |= FPSCR_FX_field::mask();
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}
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#endif
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// Update FPSCR exception bits
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record_fpscr();
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#if PPC_ENABLE_FPU_EXCEPTIONS
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int exceptions = 0;
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if (is_SNaN(a) || is_SNaN(b)) {
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exceptions |= FPSCR_VXSNAN_field::mask();
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if (OC && !FPSCR_VE_field::test(fpscr()))
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exceptions |= FPSCR_VXVC_field::mask();
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}
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else if (OC && (is_QNaN(a) || is_QNaN(b)))
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exceptions |= FPSCR_VXVC_field::mask();
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record_fpscr(exceptions);
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#endif
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increment_pc(4);
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}
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@ -842,6 +824,20 @@ void powerpc_cpu::execute_fp_int_convert(uint32 opcode)
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const uint32 r = RN::get(this, opcode);
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any_register d;
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#if PPC_ENABLE_FPU_EXCEPTIONS
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int exceptions = 0;
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if (is_NaN(b)) {
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exceptions |= FPSCR_VXCVI_field::mask();
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if (is_SNaN(b))
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exceptions |= FPSCR_VXSNAN_field::mask();
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}
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if (isinf(b))
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exceptions |= FPSCR_VXCVI_field::mask();
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feclearexcept(FE_ALL_EXCEPT);
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febarrier();
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#endif
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// Convert to integer word if operand fits bounds
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if (b >= -(double)0x80000000 && b <= (double)0x7fffffff) {
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#if defined mathlib_lrint
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@ -866,7 +862,15 @@ void powerpc_cpu::execute_fp_int_convert(uint32 opcode)
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d.j = 0x80000000;
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// Update FPSCR exception bits
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record_fpscr();
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#if PPC_ENABLE_FPU_EXCEPTIONS
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febarrier();
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int raised = fetestexcept(FE_ALL_EXCEPT);
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if (raised & FE_UNDERFLOW)
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exceptions |= FPSCR_UX_field::mask();
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if (raised & FE_INEXACT)
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exceptions |= FPSCR_XX_field::mask();
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record_fpscr(exceptions);
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#endif
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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@ -918,10 +922,32 @@ template< class Rc >
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void powerpc_cpu::execute_fp_round(uint32 opcode)
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{
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const double b = operand_fp_RB::get(this, opcode);
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#if PPC_ENABLE_FPU_EXCEPTIONS
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int exceptions =
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fp_invalid_operation_condition<double>::
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apply(FPSCR_VXSNAN_field::mask(), b);
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feclearexcept(FE_ALL_EXCEPT);
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febarrier();
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#endif
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float d = (float)b;
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// Update FPSCR exception bits
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#if PPC_ENABLE_FPU_EXCEPTIONS
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febarrier();
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int raised = fetestexcept(FE_ALL_EXCEPT);
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if (raised & FE_UNDERFLOW)
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exceptions |= FPSCR_UX_field::mask();
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if (raised & FE_INEXACT)
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exceptions |= FPSCR_XX_field::mask();
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record_fpscr(exceptions);
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#endif
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// FPSCR[FPRF] is set to the class and sign of the result
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fp_classify(d);
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if (!FPSCR_VE_field::test(fpscr()))
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fp_classify(d);
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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@ -1006,8 +1032,15 @@ void powerpc_cpu::execute_mtfsf(uint32 opcode)
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if ((f & 0x80) == 0)
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m &= ~FPSCR_FX_field::mask();
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// The mtfsf instruction cannot alter FPSCR[FEX] nor FPSCR[VX] explicitly
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int exceptions = fsf & m;
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exceptions &= ~(FPSCR_FEX_field::mask() | FPSCR_VX_field::mask());
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// Move frB bits to FPSCR according to field mask
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fpscr() = (fsf & m) | (fpscr() & ~m);
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fpscr() = (fpscr() & ~m) | exceptions;
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// Update FPSCR exception bits (don't implicitly update FX)
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record_fpscr(0);
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// Update native FP control word
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if (m & FPSCR_RN_field::mask())
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@ -1030,15 +1063,19 @@ void powerpc_cpu::execute_mtfsfi(uint32 opcode)
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if (crfD == 0)
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m &= ~FPSCR_FX_field::mask();
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// The mtfsfi instruction cannot alter FPSCR[FEX] nor FPSCR[VX] explicitly
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int exceptions = RB::get(this, opcode) & m;
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exceptions &= ~(FPSCR_FEX_field::mask() | FPSCR_VX_field::mask());
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// Move immediate to FPSCR according to field crfD
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fpscr() = (RB::get(this, opcode) & m) | (fpscr() & ~m);
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fpscr() = (fpscr() & ~m) | exceptions;
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// Update native FP control word
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if (m & FPSCR_RN_field::mask())
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fesetround(ppc_to_native_rounding_mode(FPSCR_RN_field::extract(fpscr())));
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// Update FPSCR exception bits
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record_fpscr();
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// Update FPSCR exception bits (don't implicitly update FX)
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record_fpscr(0);
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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@ -1050,16 +1087,21 @@ void powerpc_cpu::execute_mtfsfi(uint32 opcode)
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template< class RB, class Rc >
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void powerpc_cpu::execute_mtfsb(uint32 opcode)
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{
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// Bit crbD of the FPSCR is set or cleared
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const uint32 crbD = crbD_field::extract(opcode);
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fpscr() = (fpscr() & ~(1 << (31 - crbD))) | (RB::get(this, opcode) << (31 - crbD));
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// The mtfsb0 and mtfsb1 instructions cannot alter FPSCR[FEX] nor FPSCR[VX] explicitly
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int exceptions = RB::get(this, opcode) << (31 - crbD);
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exceptions &= ~(FPSCR_FEX_field::mask() | FPSCR_VX_field::mask());
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// Bit crbD of the FPSCR is set or cleared
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fpscr() &= ~(1 << (31 - crbD));
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// Update native FP control word
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if (crbD & FPSCR_RN_field::mask())
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fesetround(ppc_to_native_rounding_mode(FPSCR_RN_field::extract(fpscr())));
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// Update FPSCR exception bits
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record_fpscr();
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record_fpscr(exceptions);
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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@ -1074,9 +1116,6 @@ void powerpc_cpu::execute_mffs(uint32 opcode)
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// Move FPSCR to FPR(FRD)
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operand_fp_dw_RD::set(this, opcode, fpscr());
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// Update FPSCR exception bits
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record_fpscr();
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// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
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if (Rc::test(opcode))
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record_cr1();
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@ -228,34 +228,40 @@ static inline uint32 fp_store_single_convert(uint64 v)
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* FP classification
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**/
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static inline bool is_NaN(double v) {
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static inline bool is_NaN(double v)
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{
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any_register x; x.d = v;
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return (((x.j & UVAL64(0x7ff0000000000000)) == UVAL64(0x7ff0000000000000)) &&
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((x.j & UVAL64(0x000fffffffffffff)) != 0));
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}
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static inline bool is_SNaN(double v) {
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static inline bool is_QNaN(double v)
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{
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any_register x; x.d = v;
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return is_NaN(v) && !(x.j & UVAL64(0x0008000000000000)) ? signbit(v) : false;
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return is_NaN(v) && (x.j & UVAL64(0x0008000000000000));
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}
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static inline bool is_QNaN(double v) {
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return is_NaN(v) && !is_SNaN(v);
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static inline bool is_SNaN(double v)
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{
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return is_NaN(v) && !is_QNaN(v);
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}
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static inline bool is_NaN(float v) {
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static inline bool is_NaN(float v)
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{
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any_register x; x.f = v;
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return (((x.i & 0x7f800000) == 0x7f800000) &&
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((x.i & 0x007fffff) != 0));
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}
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static inline bool is_SNaN(float v) {
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static inline bool is_QNaN(float v)
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{
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any_register x; x.f = v;
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return is_NaN(v) && !(x.i & 0x00400000) ? signbit(v) : false;
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return is_NaN(v) && (x.i & 0x00400000);
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}
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static inline bool is_QNaN(float v) {
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return is_NaN(v) && !is_SNaN(v);
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static inline bool is_SNaN(float v)
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{
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return is_NaN(v) && !is_QNaN(v);
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}
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/**
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@ -277,43 +283,35 @@ struct fp_exception_condition {
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template< class FP >
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struct fp_invalid_operation_condition {
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static inline uint32 apply(FP a, FP b, int check, bool negate = false) {
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static inline uint32 apply(int flags) {
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uint32 exceptions = 0;
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if (FPSCR_VXSNAN_field::test(check) && (is_SNaN(a) || is_SNaN(b))) {
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exceptions |= FPSCR_VXSNAN_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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if (FPSCR_VXISI_field::test(check) && isinf(a) && isinf(b)) {
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if ((negate && (signbit(a) == signbit(b))) ||
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(!negate && (signbit(a) != signbit(b)))) {
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exceptions |= FPSCR_VXISI_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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}
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if (FPSCR_VXIDI_field::test(check) && isinf(a) && isinf(b)) {
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exceptions |= FPSCR_VXIDI_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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if (FPSCR_VXZDZ_field::test(check) && a == 0 && b == 0) {
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exceptions |= FPSCR_VXZDZ_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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}
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if (FPSCR_VXIMZ_field::test(check) && a == 0 && isinf(b)) {
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exceptions |= FPSCR_VXIMZ_field::mask();
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exceptions |= FPSCR_FX_field::mask();
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||||
}
|
||||
if (FPSCR_VXVC_field::test(check) && (is_NaN(a) || is_NaN(b))) {
|
||||
exceptions |= FPSCR_VXVC_field::mask();
|
||||
exceptions |= FPSCR_FX_field::mask();
|
||||
}
|
||||
if (FPSCR_VXSOFT_field::test(check)) {
|
||||
if (FPSCR_VXSOFT_field::test(flags))
|
||||
exceptions |= FPSCR_VXSOFT_field::mask();
|
||||
exceptions |= FPSCR_FX_field::mask();
|
||||
}
|
||||
if (FPSCR_VXSQRT_field::test(check) && signbit(a)) {
|
||||
return 0;
|
||||
}
|
||||
static inline uint32 apply(int flags, FP a) {
|
||||
uint32 exceptions = 0;
|
||||
if (FPSCR_VXSNAN_field::test(flags) && is_SNaN(a))
|
||||
exceptions |= FPSCR_VXSNAN_field::mask();
|
||||
if (FPSCR_VXVC_field::test(flags) && is_NaN(a))
|
||||
exceptions |= FPSCR_VXVC_field::mask();
|
||||
if (FPSCR_VXSQRT_field::test(flags) && signbit(a))
|
||||
exceptions |= FPSCR_VXSQRT_field::mask();
|
||||
exceptions |= FPSCR_FX_field::mask();
|
||||
return exceptions;
|
||||
}
|
||||
static inline uint32 apply(int flags, FP a, FP b, bool negate = false) {
|
||||
uint32 exceptions = apply(flags) | apply(flags, a) | apply(flags, b);
|
||||
if (FPSCR_VXISI_field::test(flags) && isinf(a) && isinf(b)) {
|
||||
if (( negate && (signbit(a) == signbit(b))) ||
|
||||
(!negate && (signbit(a) != signbit(b))))
|
||||
exceptions |= FPSCR_VXISI_field::mask();
|
||||
}
|
||||
if (FPSCR_VXIDI_field::test(flags) && isinf(a) && isinf(b))
|
||||
exceptions |= FPSCR_VXIDI_field::mask();
|
||||
if (FPSCR_VXZDZ_field::test(flags) && a == 0 && b == 0)
|
||||
exceptions |= FPSCR_VXZDZ_field::mask();
|
||||
if (FPSCR_VXIMZ_field::test(flags) && ((a == 0 && isinf(b)) || (isinf(a) && b == 0)))
|
||||
exceptions |= FPSCR_VXIMZ_field::mask();
|
||||
return exceptions;
|
||||
}
|
||||
};
|
||||
@ -322,7 +320,7 @@ struct fp_invalid_operation_condition {
|
||||
template<> \
|
||||
struct fp_exception_condition<OP> { \
|
||||
static inline uint32 apply(TYPE a, TYPE b) { \
|
||||
return fp_invalid_operation_condition<TYPE>::apply(a, b, EXCP, NEGATE); \
|
||||
return fp_invalid_operation_condition<TYPE>::apply(EXCP, a, b, NEGATE); \
|
||||
} \
|
||||
};
|
||||
|
||||
@ -335,32 +333,31 @@ struct fp_divide_exception_condition {
|
||||
static inline uint32 apply(FP a, FP b) {
|
||||
int exceptions =
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(a, b,
|
||||
FPSCR_VXSNAN_field::mask() | FPSCR_VXIDI_field::mask() | FPSCR_VXZDZ_field::mask());
|
||||
#if 0
|
||||
if (!exceptions && b == 0)
|
||||
exceptions = FPSCR_ZX_field::mask() | FPSCR_FX_field::mask();
|
||||
#endif
|
||||
apply(FPSCR_VXSNAN_field::mask() | FPSCR_VXIDI_field::mask() | FPSCR_VXZDZ_field::mask(),
|
||||
a, b);
|
||||
if (isfinite(a) && a != 0 && b == 0)
|
||||
exceptions = FPSCR_ZX_field::mask();
|
||||
return exceptions;
|
||||
}
|
||||
};
|
||||
|
||||
template<> struct fp_exception_condition<op_fdiv> : fp_divide_exception_condition<double> { };
|
||||
|
||||
template< class FP, bool NG >
|
||||
template< class FP, bool negate >
|
||||
struct fp_fma_exception_condition {
|
||||
static inline uint32 apply(FP a, FP b, FP c) {
|
||||
#if 1
|
||||
return fp_invalid_operation_condition<FP>::
|
||||
apply(a, b, FPSCR_VXSNAN_field::mask() | FPSCR_VXIMZ_field::mask());
|
||||
#else
|
||||
// FIXME: we are losing precision
|
||||
double p = a * b;
|
||||
return (fp_invalid_operation_condition<FP>::
|
||||
apply(a, b, FPSCR_VXSNAN_field::mask() | FPSCR_VXIMZ_field::mask(), false) |
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(p, c, FPSCR_VXSNAN_field::mask() | FPSCR_VXISI_field::mask(), NG));
|
||||
#endif
|
||||
return
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(FPSCR_VXSNAN_field::mask(), a) |
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(FPSCR_VXSNAN_field::mask(), b) |
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(FPSCR_VXSNAN_field::mask(), c) |
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(FPSCR_VXIMZ_field::mask(), a, b) |
|
||||
fp_invalid_operation_condition<FP>::
|
||||
apply(FPSCR_VXISI_field::mask(), a * b, c, negate)
|
||||
;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
@ -46,6 +46,16 @@ extern "C" int fesetround(int);
|
||||
|
||||
#endif /* FENV_H */
|
||||
|
||||
// Make sure previous instructions are executed first
|
||||
// XXX this is most really a hint to the compiler so that is doesn't
|
||||
// reorder calls to fe*() functions before the actual compuation...
|
||||
#if defined __GNUC__
|
||||
#define febarrier() __asm__ __volatile__ ("")
|
||||
#endif
|
||||
#ifndef febarrier
|
||||
#define febarrier()
|
||||
#endif
|
||||
|
||||
// HOST_FLOAT_WORDS_BIG_ENDIAN is a tristate:
|
||||
// yes (1) / no (0) / default (undefined)
|
||||
#if HOST_FLOAT_WORDS_BIG_ENDIAN
|
||||
|
||||
Loading…
Reference in New Issue
Block a user