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Code Issues Projects Releases Wiki Activity

Recognize 7400 & 7410 cpus

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This commit is contained in:
gbeauche 2004-01-31 11:10:49 +00:00
parent 74cf5d2686
commit 8d4108dd3a
3 changed files with 36 additions and 1 deletions
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6
SheepShaver/src/Unix/main_unix.cpp
View File

@ -460,7 +460,7 @@ int main(int argc, char **argv)
// Parse line
int i;
char value[256];
if (sscanf(line, "cpu : %s", value) == 1) {
if (sscanf(line, "cpu : %[0-9A-Za-a]", value) == 1) {
if (strcmp(value, "601") == 0)
PVR = 0x00010000;
else if (strcmp(value, "603") == 0)
@ -481,6 +481,10 @@ int main(int argc, char **argv)
PVR = 0x00320000;
else if (strcmp(value, "860") == 0)
PVR = 0x00500000;
else if (strcmp(value, "7400") == 0)
PVR = 0x80000000;
else if (strcmp(value, "7410") == 0)
PVR = 0x800c0000;
else
printf("WARNING: Unknown CPU type '%s', assuming 604\n", value);
}

19
SheepShaver/src/name_registry.cpp
View File

@ -250,6 +250,25 @@ void DoPatchNameRegistry(void)
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
break;
case 0x8000: // 7400
case 0x800c: // 7410
u32.set_value(32);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-block-size", u32.ptr(), 4);
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-sets", u32.ptr(), 4);
u32.set_value(0x8000);
RegistryPropertyCreate(power_pc.ptr(), "d-cache-size", u32.ptr(), 4);
u32.set_value(32);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-block-size", u32.ptr(), 4);
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-sets", u32.ptr(), 4);
u32.set_value(0x8000);
RegistryPropertyCreate(power_pc.ptr(), "i-cache-size", u32.ptr(), 4);
u32.set_value(64);
RegistryPropertyCreate(power_pc.ptr(), "tlb-sets", u32.ptr(), 4);
u32.set_value(128);
RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
break;
default:
break;
}

12
SheepShaver/src/rom_patches.cpp
View File

@ -906,6 +906,18 @@ static bool patch_nanokernel_boot(void)
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
break;
case 0x8000: // 7400
case 0x800c: // 7410
lp[0] = htonl(0x1000); // Page size
lp[1] = htonl(0x8000); // Data cache size
lp[2] = htonl(0x8000); // Inst cache size
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
break;
default:
printf("WARNING: Unknown CPU type\n");
break;