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- Start emulating the FPSCR. Fix mtfsf, mffs.

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- Implement mftbr so that MacOS can fully boot with extensions. However,
  using clock() is probably not the right solution. Patching UpTime from
  DriverServicesLib et al. may be a better solution.
This commit is contained in:
gbeauche 2003-11-09 15:39:30 +00:00
parent 59e6227c08
commit cd86ff9e94
3 changed files with 21 additions and 10 deletions
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2
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-config.hpp
View File

@ -86,7 +86,7 @@
**/ **/
#ifndef PPC_NO_FPSCR_UPDATE #ifndef PPC_NO_FPSCR_UPDATE
#define PPC_NO_FPSCR_UPDATE #undef PPC_NO_FPSCR_UPDATE
#endif #endif

2
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-decode.cpp
View File

@ -663,7 +663,7 @@ const powerpc_cpu::instr_info_t powerpc_cpu::powerpc_ii_table[] = {
X_form, 63, 38, CFLOW_NORMAL X_form, 63, 38, CFLOW_NORMAL
}, },
{ "mtfsf", { "mtfsf",
EXECUTE_3(mtfsf, operand_FM, operand_RB, RC_BIT_G), EXECUTE_3(mtfsf, operand_FM, operand_fp_dw_RB, RC_BIT_G),
NULL, NULL,
XFL_form, 63, 711, CFLOW_NORMAL XFL_form, 63, 711, CFLOW_NORMAL
}, },

27
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-execute.cpp
View File

@ -20,6 +20,7 @@
#include <stdio.h> #include <stdio.h>
#include <math.h> #include <math.h>
#include <time.h>
#include "sysdeps.h" #include "sysdeps.h"
#include "cpu/vm.hpp" #include "cpu/vm.hpp"
@ -965,9 +966,7 @@ void powerpc_cpu::execute_mtcrf(uint32 opcode)
template< class FM, class RB, class Rc > template< class FM, class RB, class Rc >
void powerpc_cpu::execute_mtfsf(uint32 opcode) void powerpc_cpu::execute_mtfsf(uint32 opcode)
{ {
any_register x; const uint64 fsf = RB::get(this, opcode);
x.d = RB::get(this, opcode);
const uint32 f = FM::get(this, opcode); const uint32 f = FM::get(this, opcode);
uint32 m = field2mask[f]; uint32 m = field2mask[f];
@ -977,7 +976,7 @@ void powerpc_cpu::execute_mtfsf(uint32 opcode)
#ifndef PPC_NO_FPSCR_UPDATE #ifndef PPC_NO_FPSCR_UPDATE
// Move frB bits to FPSCR according to field mask // Move frB bits to FPSCR according to field mask
fpscr() = (x.i & m) | (fpscr() & ~m); fpscr() = (fsf & m) | (fpscr() & ~m);
#endif #endif
// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set // Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
@ -1027,9 +1026,7 @@ template< class Rc >
void powerpc_cpu::execute_mffs(uint32 opcode) void powerpc_cpu::execute_mffs(uint32 opcode)
{ {
// Move FPSCR to FPR(FRD) // Move FPSCR to FPR(FRD)
any_register x; operand_fp_dw_RD::set(this, opcode, fpscr());
x.j = fpscr();
operand_fp_RD::set(this, opcode, x.d);
// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set // Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
if (Rc::test(opcode)) if (Rc::test(opcode))
@ -1053,7 +1050,19 @@ void powerpc_cpu::execute_mfspr(uint32 opcode)
case 1: d = xer().get(); break; case 1: d = xer().get(); break;
case 8: d = lr(); break; case 8: d = lr(); break;
case 9: d = ctr(); break; case 9: d = ctr(); break;
#ifdef SHEEPSHAVER
case 25: // SDR1
d = 0xdead001f;
break;
case 287: { // PVR
extern uint32 PVR;
d = PVR;
break;
}
default: d = 0;
#else
default: execute_illegal(opcode); default: execute_illegal(opcode);
#endif
} }
operand_RD::set(this, opcode, d); operand_RD::set(this, opcode, d);
increment_pc(4); increment_pc(4);
@ -1069,7 +1078,9 @@ void powerpc_cpu::execute_mtspr(uint32 opcode)
case 1: xer().set(s); break; case 1: xer().set(s); break;
case 8: lr() = s; break; case 8: lr() = s; break;
case 9: ctr() = s; break; case 9: ctr() = s; break;
#ifndef SHEEPSHAVER
default: execute_illegal(opcode); default: execute_illegal(opcode);
#endif
} }
increment_pc(4); increment_pc(4);
@ -1081,7 +1092,7 @@ void powerpc_cpu::execute_mftbr(uint32 opcode)
uint32 tbr = TBR::get(this, opcode); uint32 tbr = TBR::get(this, opcode);
uint32 d; uint32 d;
switch (tbr) { switch (tbr) {
case 268: d = tbl(); break; case 268: d = clock(); break;
case 269: d = tbu(); break; case 269: d = tbu(); break;
default: execute_illegal(opcode); default: execute_illegal(opcode);
} }