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Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE,

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PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
This commit is contained in:
gbeauche 2003-11-11 11:32:27 +00:00
parent d4ad77d734
commit cf0ed72f24
6 changed files with 21 additions and 139 deletions
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3
SheepShaver/src/Unix/sysdeps.h
View File

@ -79,8 +79,7 @@
#endif
// Configure PowerPC emulator
#define PPC_CHECK_INTERRUPTS (ASYNC_IRQ ? 0 : 1)
#define PPC_NO_LAZY_PC_UPDATE 1
//#define PPC_NO_DECODE_CACHE 1
#define PPC_DECODE_CACHE 1
#define PPC_FLIGHT_RECORDER 1
#else
// Mac ROM is write protected

95
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-config.hpp
View File

@ -78,84 +78,15 @@
/**
* PPC_NO_FPSCR_UPDATE
* PPC_DECODE_CACHE
*
* Define to not touch to FPSCR register. This is only useful for
* debugging purposes and side-by-side comparision with other
* PowerPC emulators that don't handle the FPSCR register.
**/
#ifndef PPC_NO_FPSCR_UPDATE
#undef PPC_NO_FPSCR_UPDATE
#endif
/**
* PPC_LAZY_PC_UPDATE
*
* Define to update program counter lazily, i.e. update it only
* on branch instructions. On entry of a block, program counter
* is speculatively set to the last instruction of that block.
**/
#ifndef PPC_LAZY_PC_UPDATE
#define PPC_LAZY_PC_UPDATE
#endif
#ifdef PPC_NO_LAZY_PC_UPDATE
#undef PPC_LAZY_PC_UPDATE
#endif
/**
* PPC_LAZY_CC_UPDATE
*
* Define to update condition code register lazily, i.e. (LT, GT,
* EQ) fields will be computed on-demand from the last recorded
* operation result. (SO) is always copied from the XER register.
*
* This implies PPC_HAVE_SPLIT_CR to be set. See below.
**/
#ifndef PPC_LAZY_CC_UPDATE
#undef PPC_LAZY_CC_UPDATE
#endif
/**
* PPC_HAVE_SPLIT_CR
*
* Define to split condition register fields into 8 smaller
* aggregates. This is only useful for JIT backends where we
* don't want to bother shift-masking CR values.
**/
#ifndef PPC_HAVE_SPLIT_CR
#undef PPC_HAVE_SPLIT_CR
#endif
/**
* PPC_NO_DECODE_CACHE
*
* Define to disable the decode cache. This is only useful for
* debugging purposes and side-by-side comparison with other
* Define to 0 to disable the decode cache. This is only useful
* for debugging purposes and side-by-side comparison with other
* PowerPC emulators.
**/
#ifndef PPC_NO_DECODE_CACHE
#undef PPC_NO_DECODE_CACHE
#endif
/**
* PPC_NO_DECODE_CACHE_UNROLL_EXECUTE
*
* Define to disable decode_cache[] execute loop unrolling. This
* is a manual unrolling as a Duff's device makes things worse.
**/
#ifndef PPC_NO_DECODE_CACHE_UNROLL_EXECUTE
#undef PPC_NO_DECODE_CACHE_UNROLL_EXECUTE
#ifndef PPC_DECODE_CACHE
#define PPC_DECODE_CACHE 1
#endif
@ -167,7 +98,7 @@
**/
#ifndef PPC_EXECUTE_DUMP_STATE
#undef PPC_EXECUTE_DUMP_STATE
#define PPC_EXECUTE_DUMP_STATE 0
#endif
@ -180,7 +111,7 @@
**/
#ifndef PPC_FLIGHT_RECORDER
#undef PPC_FLIGHT_RECORDER
#define PPC_FLIGHT_RECORDER 0
#endif
@ -193,16 +124,4 @@
#undef PPC_NO_STATIC_II_INDEX_TABLE
#endif
#ifdef PPC_NO_DECODE_CACHE
#undef PPC_LAZY_PC_UPDATE
#endif
#if PPC_FLIGHT_RECORDER || PPC_EXECUTE_DUMP_STATE
#undef PPC_LAZY_PC_UPDATE
#endif
#if defined(PPC_LAZY_CC_UPDATE) && !defined(PPC_HAVE_SPLIT_CR)
#define PPC_HAVE_SPLIT_CR 1
#endif
#endif /* PPC_CONFIG_H */

35
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.cpp
View File

@ -248,7 +248,7 @@ powerpc_cpu::~powerpc_cpu()
clock_t emul_end_time = clock();
const char *type = NULL;
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
type = "predecode";
#endif
if (type) {
@ -341,10 +341,10 @@ bool powerpc_cpu::check_spcflags()
void powerpc_cpu::execute(uint32 entry, bool enable_cache)
{
pc() = entry;
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
const bool dump_state = true;
#endif
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
if (enable_cache) {
for (;;) {
#if PROFILE_COMPILE_TIME
@ -361,7 +361,7 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
do {
uint32 opcode = vm_read_memory_4(dpc += 4);
ii = decode(opcode);
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
if (dump_state) {
di->opcode = opcode;
di->execute = nv_mem_fun(&powerpc_cpu::dump_instruction);
@ -377,7 +377,7 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
di->opcode = opcode;
di->execute = ii->decode ? ii->decode(this, opcode) : ii->execute;
di++;
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
if (dump_state) {
di->opcode = 0;
di->execute = nv_mem_fun(&powerpc_cpu::fake_dump_registers);
@ -404,16 +404,8 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
// Execute all cached blocks
for (;;) {
#ifdef PPC_LAZY_PC_UPDATE
pc() = bi->end_pc;
#endif
di = bi->di;
#ifdef PPC_NO_DECODE_CACHE_UNROLL_EXECUTE
for (int i = 0; i < bi->size; i++)
di[i].execute(this, di[i].opcode);
#else
const int r = bi->size % 4;
di += r;
di = bi->di + r;
int n = (bi->size + 3) / 4;
switch (r) {
case 0: do {
@ -424,7 +416,6 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
case 1: di[-1].execute(this, di[-1].opcode);
} while (--n > 0);
}
#endif
if (!spcflags().empty()) {
if (!check_spcflags())
@ -447,7 +438,7 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
for (;;) {
uint32 opcode = vm_read_memory_4(pc());
const instr_info_t *ii = decode(opcode);
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
if (dump_state)
dump_instruction(opcode);
#endif
@ -457,7 +448,7 @@ void powerpc_cpu::execute(uint32 entry, bool enable_cache)
#endif
assert(ii->execute != 0);
ii->execute(this, opcode);
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
if (dump_state)
dump_registers();
#endif
@ -473,7 +464,7 @@ void powerpc_cpu::execute()
void powerpc_cpu::init_decode_cache()
{
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
decode_cache = (block_info::decode_info *)vm_acquire(DECODE_CACHE_SIZE);
if (decode_cache == VM_MAP_FAILED) {
fprintf(stderr, "powerpc_cpu: Could not allocate decode cache\n");
@ -487,7 +478,7 @@ void powerpc_cpu::init_decode_cache()
// Leave enough room to last call to record_step()
decode_cache_end_p -= 2;
#endif
#ifdef PPC_EXECUTE_DUMP_STATE
#if PPC_EXECUTE_DUMP_STATE
// Leave enough room to last calls to dump state functions
decode_cache_end_p -= 2;
#endif
@ -498,14 +489,14 @@ void powerpc_cpu::init_decode_cache()
void powerpc_cpu::kill_decode_cache()
{
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
vm_release(decode_cache, DECODE_CACHE_SIZE);
#endif
}
void powerpc_cpu::invalidate_cache()
{
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
block_cache.clear();
block_cache.initialize();
decode_cache_p = decode_cache;
@ -516,7 +507,7 @@ void powerpc_cpu::invalidate_cache()
void powerpc_cpu::invalidate_cache_range(uintptr start, uintptr end)
{
D(bug("Invalidate cache block [%08x - %08x]\n", start, end));
#ifndef PPC_NO_DECODE_CACHE
#if PPC_DECODE_CACHE
block_cache.clear_range(start, end);
#endif
}

8
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp
View File

@ -55,11 +55,7 @@ protected:
uint32 ctr() const { return regs.ctr; }
uint32 & pc() { return regs.pc; }
uint32 pc() const { return regs.pc; }
#ifdef PPC_LAZY_PC_UPDATE
void increment_pc(int o) { }
#else
void increment_pc(int o) { pc() += o; }
#endif
uint32 & tbl() { return regs.tbl; }
uint32 tbl() const { return regs.tbl; }
uint32 & tbu() { return regs.tbu; }
@ -133,12 +129,8 @@ protected:
CFLOW_JUMP = 2,
CFLOW_TRAP = 4,
CFLOW_CONST_JUMP = 8,
#ifdef PPC_LAZY_PC_UPDATE
CFLOW_END_BLOCK = 7
#else
// Instructions that can trap don't mark the end of a block
CFLOW_END_BLOCK = 3
#endif
};
// Callbacks associated with each instruction

18
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-execute.cpp
View File

@ -353,15 +353,6 @@ void powerpc_cpu::execute_compare(uint32 opcode)
template< class OP >
void powerpc_cpu::execute_cr_op(uint32 opcode)
{
#if PPC_HAVE_SPLIT_CR
const uint32 crbA = crbA_field::extract(opcode);
uint32 a = (cr().get(crbA / 4) << (crbA % 4));
const uint32 crbB = crbB_field::extract(opcode);
uint32 b = (cr().get(crbB / 4) << (crbB % 4));
const uint32 crbD = crbD_field::extract(opcode);
uint32 d = ((OP::apply(a, b) & 8) >> (crbD % 4));
cr().set(crbD / 4, d | (cr().get(crbD / 4) & ~(1 << (3 - (crbD % 4)))));
#else
const uint32 crbA = crbA_field::extract(opcode);
uint32 a = (cr().get() >> (31 - crbA)) & 1;
const uint32 crbB = crbB_field::extract(opcode);
@ -369,7 +360,6 @@ void powerpc_cpu::execute_cr_op(uint32 opcode)
const uint32 crbD = crbD_field::extract(opcode);
uint32 d = OP::apply(a, b) & 1;
cr().set((cr().get() & ~(1 << (31 - crbD))) | (d << (31 - crbD)));
#endif
increment_pc(4);
}
@ -826,7 +816,6 @@ void powerpc_cpu::execute_fp_compare(uint32 opcode)
else
cr().set(crfd, 2);
#ifndef PPC_NO_FPSCR_UPDATE
fpscr() = (fpscr() & ~FPSCR_FPCC_field::mask()) | (cr().get(crfd) << 12);
if (is_SNaN(a) || is_SNaN(b)) {
fpscr() |= FPSCR_VXSNAN_field::mask();
@ -835,7 +824,6 @@ void powerpc_cpu::execute_fp_compare(uint32 opcode)
}
else if (OC && (is_QNaN(a) || is_QNaN(b)))
fpscr() |= FPSCR_VXVC_field::mask();
#endif
increment_pc(4);
}
@ -886,7 +874,6 @@ void powerpc_cpu::execute_fp_int_convert(uint32 opcode)
void powerpc_cpu::fp_classify(double x)
{
#ifndef PPC_NO_FPSCR_UPDATE
uint32 c = fpscr() & ~FPSCR_FPRF_field::mask();
uint8 fc = fpclassify(x);
switch (fc) {
@ -913,7 +900,6 @@ void powerpc_cpu::fp_classify(double x)
break;
}
fpscr() = c;
#endif
}
template< class Rc >
@ -974,10 +960,8 @@ void powerpc_cpu::execute_mtfsf(uint32 opcode)
if ((f & 0x80) == 0)
m &= ~FPSCR_FX_field::mask();
#ifndef PPC_NO_FPSCR_UPDATE
// Move frB bits to FPSCR according to field mask
fpscr() = (fsf & m) | (fpscr() & ~m);
#endif
// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
if (Rc::test(opcode))
@ -996,10 +980,8 @@ void powerpc_cpu::execute_mtfsfi(uint32 opcode)
if (crfD == 0)
m &= ~FPSCR_FX_field::mask();
#ifndef PPC_NO_FPSCR_UPDATE
// Move immediate to FPSCR according to field crfD
fpscr() = (RB::get(this, opcode) & m) | (fpscr() & ~m);
#endif
// Set CR1 (FX, FEX, VX, VOX) if instruction has Rc set
if (Rc::test(opcode))

1
SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp
View File

@ -144,7 +144,6 @@ private:
// Emulated registers IDs
enum {
R_ = -1,
RD = 3,
RA = 4,
RB = 5