Port JIT to IRIX/mips (initial code from QEMU)

SheepShaver/src/kpx_cpu/src/cpu/jit/basic-dyngen-ops.cpp

@@ -301,7 +301,7 @@ void OPPROTO op_execute(uint8 *entry_point, basic_cpu *this_cpu)
 	asm volatile (ASM_DATA_SECTION);
 	asm volatile (ASM_GLOBAL " " ASM_NAME(op_exec_return_offset));
 	asm volatile (ASM_NAME(op_exec_return_offset) ":");
-	asm volatile (".long 1f-" ASM_NAME(op_execute));
+	asm volatile (ASM_LONG " 1f-" ASM_NAME(op_execute));
 	asm volatile (ASM_SIZE(op_exec_return_offset));
 	asm volatile (ASM_PREVIOUS_SECTION);
 	asm volatile ("1:");

SheepShaver/src/kpx_cpu/src/cpu/jit/dyngen-exec.h

@@ -86,6 +86,16 @@
 extern int __op_param1 __hidden;
 extern int __op_param2 __hidden;
 extern int __op_param3 __hidden;
+#elif defined __mips__
+/* On MIPS, parameters to a C expression are passed via the global pointer.
+ * We don't want that. */
+#define PARAMN(index) ({ register int _r; \
+		asm("lui %0,%%hi(__op_param" #index ")\n\t" \
+		    "ori %0,%0,%%lo(__op_param" #index ")" \
+		    : "=r"(_r)); _r; })
+#define PARAM1 PARAMN(1)
+#define PARAM2 PARAMN(2)
+#define PARAM3 PARAMN(3)
 #else
 #if defined(__APPLE__) && defined(__MACH__)
 static int __op_param1, __op_param2, __op_param3;
@@ -135,6 +145,13 @@ extern int __op_jmp0, __op_jmp1;
 #if defined(__i386__)
 #define ASM_OP_EXEC_RETURN_INSN "0x0f,0xa6,0xf0"
 #endif
+#elif defined __sgi && defined __mips
+#define ASM_DATA_SECTION		".data\n"
+#define ASM_PREVIOUS_SECTION	".text\n"
+#define ASM_GLOBAL				".globl"
+#define ASM_NAME(NAME)			#NAME
+#define ASM_SIZE(NAME)			""
+#define ASM_LONG				".word"
 #else
 #define ASM_DATA_SECTION		".section \".data\"\n"
 #define ASM_PREVIOUS_SECTION	".previous\n"
@@ -142,5 +159,8 @@ extern int __op_jmp0, __op_jmp1;
 #define ASM_NAME(NAME)			#NAME
 #define ASM_SIZE(NAME)			".size " ASM_NAME(NAME) ",.-" ASM_NAME(NAME)
 #endif
+#ifndef ASM_LONG
+#define ASM_LONG				".long"
+#endif
 
 #endif /* DYNGEN_EXEC_H */

SheepShaver/src/kpx_cpu/src/cpu/jit/dyngen.c

@@ -64,6 +64,8 @@
 #define HOST_AMD64 1
 #elif defined(__m68k__)
 #define HOST_M68K 1
+#elif defined(__mips__)
+#define HOST_MIPS 1
 #endif
 
 /* Debug generated code */
@@ -224,6 +226,14 @@ static int pretty_print(char *buf, uintptr_t addr, uintptr_t base)
 #define elf_check_arch(x) ((x) == EM_68K)
 #define ELF_USES_RELOCA
 
+#elif defined(HOST_MIPS)
+
+#define ELF_CLASS	ELFCLASS32
+#define ELF_ARCH	EM_MIPS
+#define elf_check_arch(x) ((x) == EM_MIPS)
+#define ELF_USES_RELOCA
+#define ELF_USES_ALSO_RELOC
+
 #else
 #error unsupported CPU - please update the code
 #endif
@@ -641,19 +651,24 @@ elf_shdr *find_elf_section(elf_shdr *shdr, int shnum, const char *shstr,
     return NULL;
 }
 
-int find_reloc(int sh_index)
+static int do_find_reloc(int sh_index, ElfW(Word) type)
 {
     elf_shdr *sec;
     int i;
 
     for(i = 0; i < ehdr.e_shnum; i++) {
         sec = &shdr[i];
-        if (sec->sh_type == SHT_RELOC && sec->sh_info == sh_index) 
+        if (sec->sh_type == type && sec->sh_info == sh_index) 
             return i;
     }
     return 0;
 }
 
+static int find_reloc(int sh_index)
+{
+    return do_find_reloc(sh_index, SHT_RELOC);
+}
+
 static host_ulong get_rel_offset(EXE_RELOC *rel)
 {
     return rel->r_offset;
@@ -742,7 +757,7 @@ int load_object(const char *filename, FILE *outfile)
     /* swap relocations */
     for(i = 0; i < ehdr.e_shnum; i++) {
         sec = &shdr[i];
-        if (sec->sh_type == SHT_RELOC) {
+        if (sec->sh_type == SHT_REL || sec->sh_type == SHT_RELA) {
             nb_relocs = sec->sh_size / sec->sh_entsize;
             if (do_swap) {
                 for(j = 0, rel = (ELF_RELOC *)sdata[i]; j < nb_relocs; j++, rel++)
@@ -753,10 +768,14 @@ int load_object(const char *filename, FILE *outfile)
 
     /* data section */
     data_sec = find_elf_section(shdr, ehdr.e_shnum, shstr, ".data");
-    if (!data_sec)
+    if (data_sec) {
-      error("could not find .data section");
+        data_shndx = data_sec - shdr;
-    data_shndx = data_sec - shdr;
+        data = sdata[data_shndx];
-    data = sdata[data_shndx];
+    }
+    else {
+        data_shndx = -1;
+        data = NULL;
+    }
 
     /* rodata sections */
     rodata_cst4_sec = find_elf_section(shdr, ehdr.e_shnum, shstr, ".rodata.cst4");
@@ -790,6 +809,24 @@ int load_object(const char *filename, FILE *outfile)
         relocs = (ELF_RELOC *)sdata[i];
         nb_relocs = shdr[i].sh_size / shdr[i].sh_entsize;
     }
+#ifdef ELF_USES_ALSO_RELOC
+    i = do_find_reloc(text_shndx, SHT_REL);
+    if (i != 0) {
+        if (relocs) {
+            int j, nb_rels = shdr[i].sh_size / shdr[i].sh_entsize;
+            ElfW(Rel) *rels = (ElfW(Rel) *)sdata[i];
+            ELF_RELOC *new_relocs = (ELF_RELOC *)malloc(sizeof(ELF_RELOC) * (nb_relocs + nb_rels));
+            memcpy(new_relocs, relocs, sizeof(ELF_RELOC) * nb_relocs);
+            for (j = 0; j < nb_rels; j++) {
+                new_relocs[j + nb_relocs].r_offset = rels[j].r_offset;
+                new_relocs[j + nb_relocs].r_info = rels[j].r_info;
+                new_relocs[j + nb_relocs].r_addend = 0;
+            }
+            nb_relocs += nb_rels;
+            relocs = new_relocs;
+        }
+    }
+#endif
 
     symtab_sec = find_elf_section(shdr, ehdr.e_shnum, shstr, ".symtab");
     if (!symtab_sec)
@@ -1811,6 +1848,18 @@ void gen_code(const char *name, const char *demangled_name,
             error("rts expected at the end of %s", name);
         copy_size = p - p_start;
     }
+#elif defined(HOST_MIPS)
+    {
+        uint8_t *p;
+        p = (void *)(p_end - 4);
+        if (p == p_start)
+            error("empty code for %s", name);
+        while (p > p_start && get32((uint32_t *)p) != 0x03e00008)
+            p -= 4;
+        if (get32((uint32_t *)p) != 0x03e00008)
+            error("jr ra expected at the end of %s", name);
+        copy_size = p - p_start;
+    }
 #else
 #error unsupported CPU
 #endif
@@ -2621,6 +2670,53 @@ void gen_code(const char *name, const char *demangled_name,
                 }
                 }
             }
+#elif defined(HOST_MIPS)
+            {
+                char name[256];
+                int type;
+                int addend;
+                for (i = 0, rel = relocs; i < nb_relocs; i++, rel++) {
+                    if (rel->r_offset >= start_offset &&
+                        rel->r_offset < start_offset + copy_size) {
+                        sym_name = strtab + symtab[ELFW(R_SYM)(rel->r_info)].st_name;
+                        if (strstart(sym_name, "__op_jmp", &p)) {
+                            int n;
+                            n = strtol(p, NULL, 10);
+                            /* __op_jmp relocations are done at
+                               runtime to do translated block
+                               chaining: the offset of the instruction
+                               needs to be stored */
+                            fprintf(outfile, "    jmp_addr[%d] = code_ptr() + %d;\n",
+                                    n, rel->r_offset - start_offset);
+                            continue;
+                        }
+
+                        if (strstart(sym_name, "__op_param", &p)) {
+                            snprintf(name, sizeof(name), "param%s", p);
+                        } else {
+                            snprintf(name, sizeof(name), "(long)(&%s)", sym_name);
+                        }
+                        type = ELFW(R_TYPE)(rel->r_info);
+                        addend = rel->r_addend;
+                        if (addend)
+                            error("non zero addend (%d), deal with this", addend);
+                        switch (type) {
+                        case R_MIPS_HI16:
+                            fprintf(outfile, "    /* R_MIPS_HI16 reloc, offset %x */\n", rel->r_offset);
+                            fprintf(outfile, "    *(uint16_t *)(code_ptr() + %d) = (uint16_t)((uint32_t)(%s)>>16);\n",
+                                    rel->r_offset - start_offset + 2, name);
+                            break;
+                        case R_MIPS_LO16:
+                            fprintf(outfile, "    /* R_MIPS_LO16 reloc, offset %x */\n", rel->r_offset);
+                            fprintf(outfile, "    *(uint16_t *)(code_ptr() + %d) = (uint16_t)((uint32_t)(%s)&0xffff);\n",
+                                    rel->r_offset - start_offset + 2, name);
+                            break;
+                        default:
+                            error("unsupported MIPS relocation (%d)", type);
+                        }
+                    }
+                }
+            }
 #else
 #error unsupported CPU
 #endif
@@ -2666,6 +2762,8 @@ int gen_file(FILE *outfile, int out_type)
                 if (sym->st_shndx != data_shndx)
                     error("invalid section for data (0x%x)", sym->st_shndx);
 #endif
+                if (data == NULL)
+                    error("no .data section found");
                 fprintf(outfile, "DEFINE_CST(%s,0x%xL)\n\n", name, *((host_ulong *)(data + sym->st_value)));
             }
             else if (strstart(name, OP_PREFIX "invoke", NULL)) {

SheepShaver/src/kpx_cpu/src/cpu/jit/mips/dyngen-target-exec.h

@@ -0,0 +1,45 @@
+/*
+ *  dyngen defines for micro operation code
+ *
+ *  Copyright (c) 2003-2004-2004 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef DYNGEN_TARGET_EXEC_H
+#define DYNGEN_TARGET_EXEC_H
+
+enum {
+  /* callee save registers */
+#define AREG0 "s0"
+  AREG0_ID = 16,
+
+#define AREG1 "s1"
+  AREG1_ID = 17,
+
+#define AREG2 "s2"
+  AREG2_ID = 18,
+
+#define AREG3 "s3"
+  AREG3_ID = 19,
+
+#define AREG4 "s4"
+  AREG4_ID = 20,
+
+#define AREG5 "s5"
+  AREG5_ID = 21,
+};
+
+#endif /* DYNGEN_TARGET_EXEC_H */

SheepShaver/src/kpx_cpu/src/cpu/jit/mips/jit-target-cache.hpp

@@ -0,0 +1,34 @@
+/*
+ *  jit-target-cache.hpp - Target specific code to invalidate cache
+ *
+ *  Kheperix (C) 2003-2005 Gwenole Beauchesne
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef JIT_TARGET_CACHE_H
+#define JIT_TARGET_CACHE_H
+
+#if defined __sgi
+#include <sys/cachectl.h>
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+	cacheflush((void *)start, stop - start, BCACHE);
+}
+#elif defined __GNUC__
+#error "FIXME: implement assembly code for code cache invalidation"
+#endif
+
+#endif /* JIT_TARGET_CACHE_H */