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Implement ISYNC, MTCRF, MCRF.

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This commit is contained in:
gbeauche 2003-12-01 13:40:38 +00:00
parent 054748532a
commit e2ca6270f8
3 changed files with 30 additions and 0 deletions
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8
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
View File

@ -841,3 +841,11 @@ void OPPROTO op_inc_32_mem(void)
uint32 *m = (uint32 *)PARAM1;
*m += 1;
}
void OPPROTO op_mtcrf_T0_im(void)
{
const uint32 mask = PARAM1;
uint32 cr = powerpc_dyngen_helper::get_cr() & ~mask;
cr |= T0 & mask;
powerpc_dyngen_helper::set_cr(cr);
}

1
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
View File

@ -105,6 +105,7 @@ public:
// Misc instructions
DEFINE_ALIAS(inc_32_mem,1);
DEFINE_ALIAS(mtcrf_T0_im,1);
// Condition registers
private:

21
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-translate.cpp
View File

@ -994,6 +994,27 @@ powerpc_cpu::compile_block(uint32 entry_point)
{
break;
}
case PPC_I(ISYNC): // Instruction synchronize
{
typedef void (*func_t)(dyngen_cpu_base);
func_t func = (func_t)nv_mem_fun(&powerpc_cpu::execute_invalidate_cache_range).ptr();
dg.gen_invoke_CPU(func);
break;
}
case PPC_I(MTCRF): // Move to Condition Register Fields
{
dg.gen_commit_cr();
dg.gen_load_T0_GPR(rS_field::extract(opcode));
dg.gen_mtcrf_T0_im(field2mask[CRM_field::extract(opcode)]);
break;
}
case PPC_I(MCRF): // Move Condition Register Field
{
dg.gen_commit_cr();
dg.gen_load_RC_cr(crfS_field::extract(opcode));
dg.gen_store_RC_cr(crfD_field::extract(opcode));
break;
}
default: // Direct call to instruction handler
{
typedef void (*func_t)(dyngen_cpu_base, uint32);