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- When X86_ASSEMBLY is set, aka when cpuopti is used, do call the

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instruction handler by hand and make sure to save %ebp too
- Really merge cpu core with uae-0.8.21:
  - Trace mode fixes (Bernd Roesch & Bernd Schmidt)
  - Reintegrate PTEST and PFLUSH instructions back as no-ops
This commit is contained in:
gbeauche
2002-03-23 13:57:38 +00:00
parent ed628a548b
commit f5e58c95d6
3 changed files with 31 additions and 13 deletions
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37
BasiliskII/src/uae_cpu/newcpu.cpp
View File

@@ -707,7 +707,9 @@ void MakeFromSR (void)
if (regs.t1 || regs.t0) if (regs.t1 || regs.t0)
regs.spcflags |= SPCFLAG_TRACE; regs.spcflags |= SPCFLAG_TRACE;
else else
regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE); /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
SR-modifying instructions (including STOP). */
regs.spcflags &= ~SPCFLAG_TRACE;
} }
void Exception(int nr, uaecptr oldpc) void Exception(int nr, uaecptr oldpc)
@@ -788,13 +790,13 @@ static void Interrupt(int nr)
regs.spcflags |= SPCFLAG_INT; regs.spcflags |= SPCFLAG_INT;
} }
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp;
int m68k_move2c (int regno, uae_u32 *regp) int m68k_move2c (int regno, uae_u32 *regp)
{ {
if ((CPUType == 1 && (regno & 0x7FF) > 1) if ((CPUType == 1 && (regno & 0x7FF) > 1)
|| (CPUType < 4 && (regno & 0x7FF) > 2) || (CPUType < 4 && (regno & 0x7FF) > 2)
|| (CPUType == 4 && regno == 0x802)) || (CPUType == 4 && regno == 0x802))
{ {
op_illg (0x4E7B); op_illg (0x4E7B);
return 0; return 0;
@@ -813,6 +815,9 @@ int m68k_move2c (int regno, uae_u32 *regp)
case 0x802: caar = *regp &0xfc; break; case 0x802: caar = *regp &0xfc; break;
case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break; case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
case 0x805: mmusr = *regp; break;
case 0x806: urp = *regp; break;
case 0x807: srp = *regp; break;
default: default:
op_illg (0x4E7B); op_illg (0x4E7B);
return 0; return 0;
@@ -824,8 +829,8 @@ int m68k_move2c (int regno, uae_u32 *regp)
int m68k_movec2 (int regno, uae_u32 *regp) int m68k_movec2 (int regno, uae_u32 *regp)
{ {
if ((CPUType == 1 && (regno & 0x7FF) > 1) if ((CPUType == 1 && (regno & 0x7FF) > 1)
|| (CPUType < 4 && (regno & 0x7FF) > 2) || (CPUType < 4 && (regno & 0x7FF) > 2)
|| (CPUType == 4 && regno == 0x802)) || (CPUType == 4 && regno == 0x802))
{ {
op_illg (0x4E7A); op_illg (0x4E7A);
return 0; return 0;
@@ -844,6 +849,9 @@ int m68k_movec2 (int regno, uae_u32 *regp)
case 0x802: *regp = caar; break; case 0x802: *regp = caar; break;
case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break; case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
case 0x805: *regp = mmusr; break;
case 0x806: *regp = urp; break;
case 0x807: *regp = srp; break;
default: default:
op_illg (0x4E7A); op_illg (0x4E7A);
return 0; return 0;
@@ -1195,12 +1203,13 @@ void REGPARAM2 op_illg (uae_u32 opcode)
void mmu_op(uae_u32 opcode, uae_u16 extra) void mmu_op(uae_u32 opcode, uae_u16 extra)
{ {
if ((extra & 0xB000) == 0) { /* PMOVE instruction */ if ((opcode & 0xFE0) == 0x0500) {
/* PFLUSH */
} else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */ mmusr = 0;
} else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */ } else if ((opcode & 0x0FD8) == 0x548) {
/* PTEST */
} else } else
op_illg (opcode); op_illg (opcode);
} }
static int n_insns = 0, n_spcinsns = 0; static int n_insns = 0, n_spcinsns = 0;
@@ -1289,7 +1298,13 @@ static void m68k_run_1 (void)
#if FLIGHT_RECORDER #if FLIGHT_RECORDER
record_step(m68k_getpc()); record_step(m68k_getpc());
#endif #endif
#ifdef X86_ASSEMBLY
__asm__ __volatile__("\tpushl %%ebp\n\tcall *%%ebx\n\tpopl %%ebp" /* FIXME */
: : "b" (cpufunctbl[opcode]), "a" (opcode)
: "%edx", "%ecx", "%esi", "%edi", "%ebp", "memory", "cc");
#else
(*cpufunctbl[opcode])(opcode); (*cpufunctbl[opcode])(opcode);
#endif
if (regs.spcflags) { if (regs.spcflags) {
if (do_specialties()) if (do_specialties())
return; return;

4
BasiliskII/src/uae_cpu/newcpu.h
View File

@@ -222,7 +222,9 @@ static __inline__ void m68k_do_jsr(uaecptr oldpc, uaecptr dest)
static __inline__ void m68k_setstopped (int stop) static __inline__ void m68k_setstopped (int stop)
{ {
regs.stopped = stop; regs.stopped = stop;
if (stop) /* A traced STOP instruction drops through immediately without
actually stopping. */
if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0)
regs.spcflags |= SPCFLAG_STOP; regs.spcflags |= SPCFLAG_STOP;
} }

3
BasiliskII/src/uae_cpu/table68k
View File

@@ -25,7 +25,7 @@
% %
% Arp: --> -(Ar) % Arp: --> -(Ar)
% ArP: --> (Ar)+ % ArP: --> (Ar)+
% L: (xxx).L % L: (xxx.L)
% %
% Fields on a line: % Fields on a line:
% 16 chars bitpattern : % 16 chars bitpattern :
@@ -246,6 +246,7 @@
1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] 1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
% 68040 instructions % 68040 instructions
1111 0101 iiii iSSS:40:?????:?????:11: MMUOP #i,s
1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar 1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar
1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar 1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar
1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p 1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p