mirror of
https://github.com/kanjitalk755/macemu.git
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Add FPU instructions.
This commit is contained in:
gbeauche
parent
b083b08fd1
commit
f6aecb472d
@ -42,7 +42,6 @@
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* TODO
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*
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* o Fix FIXMEs
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* o i387 FPU instructions
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* o SSE instructions
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* o Optimize for cases where register numbers are not integral constants
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*/
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@ -111,6 +110,7 @@ enum {
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X86_Reg64_Base = 0x50,
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X86_RegMMX_Base = 0x60,
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X86_RegXMM_Base = 0x70,
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X86_RegFPU_Base = 0x80
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#else
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X86_NOREG = -1,
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X86_Reg8L_Base = 0,
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@ -120,6 +120,7 @@ enum {
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X86_Reg64_Base = 0,
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X86_RegMMX_Base = 0,
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X86_RegXMM_Base = 0,
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X86_RegFPU_Base = 0
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#endif
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};
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@ -171,6 +172,12 @@ enum {
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X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15
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};
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enum {
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X86_ST0 = X86_RegFPU_Base,
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X86_ST1, X86_ST2, X86_ST3,
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X86_ST4, X86_ST5, X86_ST6, X86_ST7
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};
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/* Register control and access
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*
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* _r0P(R) Null register?
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@ -187,9 +194,11 @@ enum {
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* _r8(R) 64-bit register ID
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* _rM(R) MMX register ID
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* _rX(R) XMM register ID
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* _rF(R) FPU register ID
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* _rA(R) Address register ID used for EA calculation
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*/
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#define _rST0P(R) ((int)(R) == (int)X86_ST0)
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#define _r0P(R) ((int)(R) == (int)X86_NOREG)
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#define _rIP(R) (X86_TARGET_64BIT ? ((int)(R) == (int)X86_RIP) : 0)
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@ -212,6 +221,7 @@ enum {
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#define _rA(R) _rN(R)
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#define _rM(R) _rN(R)
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#define _rX(R) _rN(R)
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#define _rF(R) _rN(R)
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#else
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#define _r1(R) ( ((_rC(R) & (X86_Reg8L_Base | X86_Reg8H_Base)) != 0) ? _rN(R) : x86_emit_failure0( "8-bit register required"))
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#define _r2(R) ( (_rC(R) == X86_Reg16_Base) ? _rN(R) : x86_emit_failure0("16-bit register required"))
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@ -222,6 +232,7 @@ enum {
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( (_rC(R) == X86_Reg32_Base) ? _rN(R) : x86_emit_failure0("not a valid 32-bit base/index expression")) )
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#define _rM(R) ( (_rC(R) == X86_RegMMX_Base) ? _rN(R) : x86_emit_failure0("MMX register required"))
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#define _rX(R) ( (_rC(R) == X86_RegXMM_Base) ? _rN(R) : x86_emit_failure0("SSE register required"))
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#define _rF(R) ( (_rC(R) == X86_RegFPU_Base) ? _rN(R) : x86_emit_failure0("FPU register required"))
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#endif
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#define _rSP() (X86_TARGET_64BIT ? (int)X86_RSP : (int)X86_ESP)
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@ -2326,99 +2337,229 @@ enum {
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#define MOVLPSrm(RS, MD, MB, MI, MS) __SSELrm( 0x13, RS,_rX, MD, MB, MI, MS)
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/* --- FLoating-Point instructions ----------------------------------------- */
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/* --- Floating-Point instructions ----------------------------------------- */
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#define _ESCmi(D,B,I,S,OP) (_REXLrm(0,B,I), _O_r_X(0xd8|(OP & 7), (OP >> 3), D,B,I,S))
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enum {
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X86_F2XM1 = 0xd9f0,
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X86_FABS = 0xd9e1,
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X86_FADD = 0xd8c0, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FIADD = 0xda00, // m32int, m16int
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X86_FBLD = 0xdf04, // mem
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X86_FBSTP = 0xdf06, // mem
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X86_FCHS = 0xd9e0,
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X86_FCMOVB = 0xdac0, // sti0
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X86_FCMOVE = 0xdac8, // sti0
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X86_FCMOVBE = 0xdad0, // sti0
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X86_FCMOVU = 0xdad8, // sti0
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X86_FCMOVNB = 0xdbc0, // sti0
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X86_FCMOVNE = 0xdbc8, // sti0
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X86_FCMOVNBE = 0xdbd0, // sti0
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X86_FCMOVNU = 0xdbd8, // sti0
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X86_FCOM = 0xd8d2, // m32fp, m64fp, sti
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X86_FCOMP = 0xd8db, // m32fp, m64fp, sti
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X86_FCOMPP = 0xded9,
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X86_FCOMI = 0xdbf0, // sti0
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X86_FCOMIP = 0xdff0, // sti0
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X86_FUCOMI = 0xdbe8, // sti0
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X86_FUCOMIP = 0xdfe8, // sti0
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X86_FCOS = 0xd9ff,
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X86_FDECSTP = 0xd9f6,
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X86_FDIV = 0xd8f6, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FIDIV = 0xda06, // m32int, m16int
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X86_FDIVR = 0xd8ff, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FIDIVR = 0xda07, // m32int, m16int
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X86_FFREE = 0xddc0, // sti
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X86_FICOM = 0xda02, // m32int, m16int
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X86_FICOMP = 0xda03, // m32int, m16int
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X86_FILD = 0xdb00, // m32int, m16int
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X86_FILDQ = 0xdf05, // mem
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X86_FINCSTP = 0xd9f7,
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X86_FIST = 0xdb02, // m32int, m16int
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X86_FISTP = 0xdb03, // m32int, m16int
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X86_FISTPQ = 0xdf07, // mem
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X86_FISTTP = 0xdb01, // m32int, m16int
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X86_FISTTPQ = 0xdd01, // mem
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X86_FLD = 0xd900, // m32fp, m64fp
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X86_FLDT = 0xdb05, // mem
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X86_FLD1 = 0xd9e8,
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X86_FLDL2T = 0xd9e9,
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X86_FLDL2E = 0xd9ea,
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X86_FLDPI = 0xd9eb,
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X86_FLDLG2 = 0xd9ec,
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X86_FLDLN2 = 0xd9ed,
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X86_FLDZ = 0xd9ee,
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X86_FMUL = 0xd8c9, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FIMUL = 0xda01, // m32int, m16int
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X86_FNOP = 0xd9d0,
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X86_FPATAN = 0xd9f3,
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X86_FPREM = 0xd9f8,
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X86_FPREM1 = 0xd9f5,
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X86_FPTAN = 0xd9f2,
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X86_FRNDINT = 0xd9fc,
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X86_FSCALE = 0xd9fd,
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X86_FSIN = 0xd9fe,
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X86_FSINCOS = 0xd9fb,
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X86_FSQRT = 0xd9fa,
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X86_FSTS = 0xd902, // mem
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X86_FSTL = 0xdd02, // mem
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X86_FST = 0xddd0, // sti
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X86_FSTPS = 0xd903, // mem
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X86_FSTPL = 0xdd03, // mem
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X86_FSTPT = 0xdb07, // mem
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X86_FSTP = 0xddd8, // sti
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X86_FSUB = 0xd8e4, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FISUB = 0xda04, // m32int, m16int
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X86_FSUBR = 0xd8ed, // m32fp, m64fp, sti0, st0i, pst0i
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X86_FISUBR = 0xda05, // m32int, m16int
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X86_FTST = 0xd9e4,
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X86_FUCOM = 0xdde0, // sti
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X86_FUCOMP = 0xdde8, // sti
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X86_FUCOMPP = 0xdae9,
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X86_FXAM = 0xd9e5,
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X86_FXCH = 0xd9c8, // sti
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X86_FXTRACT = 0xd9f4,
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X86_FYL2X = 0xd9f1,
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X86_FYL2XP1 = 0xd9f9,
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};
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#define FLDr(R) _OOr(0xd9c0,_rN(R))
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#define FLDLm(D,B,I,S) _ESCmi(D,B,I,S,005)
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#define FLDSm(D,B,I,S) _ESCmi(D,B,I,S,001)
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#define FLDTm(D,B,I,S) _ESCmi(D,B,I,S,053)
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#define _FPU(OP) _OO(OP)
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#define _FPUm(OP, MD, MB, MI, MS) (_REXLrm(0, MB, MI), _O_r_X((OP)>>8, (OP)&7, MD, MB, MI, MS))
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#define _FPUSm(OP, MD, MB, MI, MS) _FPUm(OP, MD, MB, MI, MS)
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#define _FPUDm(OP, MD, MB, MI, MS) _FPUm((OP)|0x400, MD, MB, MI, MS)
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#define _FPULm(OP, MD, MB, MI, MS) _FPUm(OP, MD, MB, MI, MS)
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#define _FPUWm(OP, MD, MB, MI, MS) _FPUm((OP)|0x400, MD, MB, MI, MS)
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#define _FPUr(OP, RR) _OOr((OP)&0xfff8, _rF(RR))
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#define _FPU0r(OP, RD) _FPUr((OP)|0x400, RD)
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#define _FPUr0(OP, RS) _FPUr((OP) , RS)
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#define _FPUrr(OP, RS, RD) (_rST0P(RS) ? _FPU0r(OP, RD) : (_rST0P(RD) ? _FPUr0(OP, RS) : x86_emit_failure("FPU instruction without st0")))
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#define _FPUP0r(OP, RD) _FPU0r((OP)|0x200, RD)
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#define FSTr(R) _OOr(0xddd0,_rN(R))
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#define FSTSm(D,B,I,S) _ESCmi(D,B,I,S,021)
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#define FSTLm(D,B,I,S) _ESCmi(D,B,I,S,025)
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#define FSTPr(R) _OOr(0xddd8,_rN(R))
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#define FSTPSm(D,B,I,S) _ESCmi(D,B,I,S,031)
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#define FSTPLm(D,B,I,S) _ESCmi(D,B,I,S,035)
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#define FSTPTm(D,B,I,S) _ESCmi(D,B,I,S,073)
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#define FADDr0(R) _OOr(0xd8c0,_rN(R))
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#define FADD0r(R) _OOr(0xdcc0,_rN(R))
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#define FADDP0r(R) _OOr(0xdec0,_rN(R))
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#define FADDSm(D,B,I,S) _ESCmi(D,B,I,S,000)
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#define FADDLm(D,B,I,S) _ESCmi(D,B,I,S,004)
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#define FSUBSm(D,B,I,S) _ESCmi(D,B,I,S,040)
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#define FSUBLm(D,B,I,S) _ESCmi(D,B,I,S,044)
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#define FSUBr0(R) _OOr(0xd8e0,_rN(R))
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#define FSUB0r(R) _OOr(0xdce8,_rN(R))
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#define FSUBP0r(R) _OOr(0xdee8,_rN(R))
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#define FSUBRr0(R) _OOr(0xd8e8,_rN(R))
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#define FSUBR0r(R) _OOr(0xdce0,_rN(R))
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#define FSUBRP0r(R) _OOr(0xdee0,_rN(R))
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#define FSUBRSm(D,B,I,S) _ESCmi(D,B,I,S,050)
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#define FSUBRLm(D,B,I,S) _ESCmi(D,B,I,S,054)
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#define FMULr0(R) _OOr(0xd8c8,_rN(R))
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#define FMUL0r(R) _OOr(0xdcc8,_rN(R))
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#define FMULP0r(R) _OOr(0xdec8,_rN(R))
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#define FMULSm(D,B,I,S) _ESCmi(D,B,I,S,010)
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#define FMULLm(D,B,I,S) _ESCmi(D,B,I,S,014)
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#define FDIVr0(R) _OOr(0xd8f0,_rN(R))
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#define FDIV0r(R) _OOr(0xdcf8,_rN(R))
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#define FDIVP0r(R) _OOr(0xdef8,_rN(R))
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#define FDIVSm(D,B,I,S) _ESCmi(D,B,I,S,060)
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#define FDIVLm(D,B,I,S) _ESCmi(D,B,I,S,064)
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#define FDIVRr0(R) _OOr(0xd8f8,_rN(R))
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#define FDIVR0r(R) _OOr(0xdcf0,_rN(R))
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#define FDIVRP0r(R) _OOr(0xdef0,_rN(R))
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#define FDIVRSm(D,B,I,S) _ESCmi(D,B,I,S,070)
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#define FDIVRLm(D,B,I,S) _ESCmi(D,B,I,S,074)
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#define FCMOVBr0(R) _OOr(0xdac0,_rN(R))
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#define FCMOVBEr0(R) _OOr(0xdad0,_rN(R))
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#define FCMOVEr0(R) _OOr(0xdac8,_rN(R))
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#define FCMOVNBr0(R) _OOr(0xdbc0,_rN(R))
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#define FCMOVNBEr0(R) _OOr(0xdbd0,_rN(R))
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#define FCMOVNEr0(R) _OOr(0xdbc8,_rN(R))
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#define FCMOVNUr0(R) _OOr(0xdbd8,_rN(R))
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#define FCMOVUr0(R) _OOr(0xdad8,_rN(R))
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#define FCOMIr0(R) _OOr(0xdbf0,_rN(R))
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#define FCOMIPr0(R) _OOr(0xdff0,_rN(R))
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#define FCOMr(R) _OOr(0xd8d0,_rN(R))
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#define FCOMSm(D,B,I,S) _ESCmi(D,B,I,S,020)
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#define FCOMLm(D,B,I,S) _ESCmi(D,B,I,S,024)
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#define FCOMPr(R) _OOr(0xd8d8,_rN(R))
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#define FCOMPSm(D,B,I,S) _ESCmi(D,B,I,S,030)
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#define FCOMPLm(D,B,I,S) _ESCmi(D,B,I,S,034)
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#define FUCOMIr0(R) _OOr(0xdbe8,_rN(R))
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#define FUCOMIPr0(R) _OOr(0xdfe8,_rN(R))
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#define FUCOMPr(R) _OOr(0xdde8,_rN(R))
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#define FUCOMr(R) _OOr(0xdde0,_rN(R))
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#define FIADDLm(D,B,I,S) _ESCmi(D,B,I,S,002)
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#define FICOMLm(D,B,I,S) _ESCmi(D,B,I,S,022)
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#define FICOMPLm(D,B,I,S) _ESCmi(D,B,I,S,032)
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#define FIDIVLm(D,B,I,S) _ESCmi(D,B,I,S,062)
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#define FIDIVRLm(D,B,I,S) _ESCmi(D,B,I,S,072)
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#define FILDLm(D,B,I,S) _ESCmi(D,B,I,S,003)
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#define FILDQm(D,B,I,S) _ESCmi(D,B,I,S,057)
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#define FIMULLm(D,B,I,S) _ESCmi(D,B,I,S,012)
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#define FISTLm(D,B,I,S) _ESCmi(D,B,I,S,023)
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#define FISTPLm(D,B,I,S) _ESCmi(D,B,I,S,033)
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#define FISTPQm(D,B,I,S) _ESCmi(D,B,I,S,077)
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#define FISUBLm(D,B,I,S) _ESCmi(D,B,I,S,042)
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#define FISUBRLm(D,B,I,S) _ESCmi(D,B,I,S,052)
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#define FREEr(R) _OOr(0xddc0,_rN(R))
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#define FXCHr(R) _OOr(0xd9c8,_rN(R))
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#define F2XM1() _FPU(X86_F2XM1)
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#define FABS() _FPU(X86_FABS)
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#define FADDSm(MD, MB, MI, MS) _FPUSm(X86_FADD, MD, MB, MI, MS)
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#define FADDDm(MD, MB, MI, MS) _FPUDm(X86_FADD, MD, MB, MI, MS)
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#define FADDP0r(RD) _FPUP0r(X86_FADD, RD)
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#define FADDrr(RS, RD) _FPUrr(X86_FADD, RS, RD)
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#define FADD0r(RD) _FPU0r(X86_FADD, RD)
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#define FADDr0(RS) _FPUr0(X86_FADD, RS)
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#define FIADDWm(MD, MB, MI, MS) _FPUWm(X86_FIADD, MD, MB, MI, MS)
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#define FIADDLm(MD, MB, MI, MS) _FPULm(X86_FIADD, MD, MB, MI, MS)
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#define FBLDm(MD, MB, MI, MS) _FPUm(X86_FBLD, MD, MB, MI, MS)
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#define FBSTPm(MD, MB, MI, MS) _FPUm(X86_FBSTP, MD, MB, MI, MS)
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#define FCHS() _FPU(X86_FCHS)
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#define FCMOVBr0(RS) _FPUr0(X86_FCMOVB, RS)
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#define FCMOVEr0(RS) _FPUr0(X86_FCMOVE, RS)
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#define FCMOVBEr0(RS) _FPUr0(X86_FCMOVBE, RS)
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#define FCMOVUr0(RS) _FPUr0(X86_FCMOVU, RS)
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#define FCMOVNBr0(RS) _FPUr0(X86_FCMOVNB, RS)
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#define FCMOVNEr0(RS) _FPUr0(X86_FCMOVNE, RS)
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#define FCMOVNBEr0(RS) _FPUr0(X86_FCMOVNBE, RS)
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#define FCMOVNUr0(RS) _FPUr0(X86_FCMOVNU, RS)
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#define FCOMSm(MD, MB, MI, MS) _FPUSm(X86_FCOM, MD, MB, MI, MS)
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#define FCOMDm(MD, MB, MI, MS) _FPUDm(X86_FCOM, MD, MB, MI, MS)
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#define FCOMr(RD) _FPUr(X86_FCOM, RD)
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#define FCOMPSm(MD, MB, MI, MS) _FPUSm(X86_FCOMP, MD, MB, MI, MS)
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#define FCOMPDm(MD, MB, MI, MS) _FPUDm(X86_FCOMP, MD, MB, MI, MS)
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#define FCOMPr(RD) _FPUr(X86_FCOMP, RD)
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#define FCOMPP() _FPU(X86_FCOMPP)
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#define FCOMIr0(RS) _FPUr0(X86_FCOMI, RS)
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#define FCOMIPr0(RS) _FPUr0(X86_FCOMIP, RS)
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#define FUCOMIr0(RS) _FPUr0(X86_FUCOMI, RS)
|
||||
#define FUCOMIPr0(RS) _FPUr0(X86_FUCOMIP, RS)
|
||||
#define FCOS() _FPU(X86_FCOS)
|
||||
#define FDECSTP() _FPU(X86_FDECSTP)
|
||||
#define FDIVSm(MD, MB, MI, MS) _FPUSm(X86_FDIV, MD, MB, MI, MS)
|
||||
#define FDIVDm(MD, MB, MI, MS) _FPUDm(X86_FDIV, MD, MB, MI, MS)
|
||||
#define FDIVP0r(RD) _FPUP0r(X86_FDIV, RD)
|
||||
#define FDIVrr(RS, RD) _FPUrr(X86_FDIV, RS, RD)
|
||||
#define FDIV0r(RD) _FPU0r(X86_FDIV, RD)
|
||||
#define FDIVr0(RS) _FPUr0(X86_FDIV, RS)
|
||||
#define FIDIVWm(MD, MB, MI, MS) _FPUWm(X86_FIDIV, MD, MB, MI, MS)
|
||||
#define FIDIVLm(MD, MB, MI, MS) _FPULm(X86_FIDIV, MD, MB, MI, MS)
|
||||
#define FDIVRSm(MD, MB, MI, MS) _FPUSm(X86_FDIVR, MD, MB, MI, MS)
|
||||
#define FDIVRDm(MD, MB, MI, MS) _FPUDm(X86_FDIVR, MD, MB, MI, MS)
|
||||
#define FDIVRP0r(RD) _FPUP0r(X86_FDIVR, RD)
|
||||
#define FDIVRrr(RS, RD) _FPUrr(X86_FDIVR, RS, RD)
|
||||
#define FDIVR0r(RD) _FPU0r(X86_FDIVR, RD)
|
||||
#define FDIVRr0(RS) _FPUr0(X86_FDIVR, RS)
|
||||
#define FIDIVRWm(MD, MB, MI, MS) _FPUWm(X86_FIDIVR, MD, MB, MI, MS)
|
||||
#define FIDIVRLm(MD, MB, MI, MS) _FPULm(X86_FIDIVR, MD, MB, MI, MS)
|
||||
#define FFREEr(RD) _FPUr(X86_FFREE, RD)
|
||||
#define FICOMWm(MD, MB, MI, MS) _FPUWm(X86_FICOM, MD, MB, MI, MS)
|
||||
#define FICOMLm(MD, MB, MI, MS) _FPULm(X86_FICOM, MD, MB, MI, MS)
|
||||
#define FICOMPWm(MD, MB, MI, MS) _FPUWm(X86_FICOMP, MD, MB, MI, MS)
|
||||
#define FICOMPLm(MD, MB, MI, MS) _FPULm(X86_FICOMP, MD, MB, MI, MS)
|
||||
#define FILDWm(MD, MB, MI, MS) _FPUWm(X86_FILD, MD, MB, MI, MS)
|
||||
#define FILDLm(MD, MB, MI, MS) _FPULm(X86_FILD, MD, MB, MI, MS)
|
||||
#define FILDQm(MD, MB, MI, MS) _FPUm(X86_FILDQ, MD, MB, MI, MS)
|
||||
#define FINCSTP() _FPU(X86_FINCSTP)
|
||||
#define FISTWm(MD, MB, MI, MS) _FPUWm(X86_FIST, MD, MB, MI, MS)
|
||||
#define FISTLm(MD, MB, MI, MS) _FPULm(X86_FIST, MD, MB, MI, MS)
|
||||
#define FISTPWm(MD, MB, MI, MS) _FPUWm(X86_FISTP, MD, MB, MI, MS)
|
||||
#define FISTPLm(MD, MB, MI, MS) _FPULm(X86_FISTP, MD, MB, MI, MS)
|
||||
#define FISTPQm(MD, MB, MI, MS) _FPUm(X86_FISTPQ, MD, MB, MI, MS)
|
||||
#define FISTTPWm(MD, MB, MI, MS) _FPUWm(X86_FISTTP, MD, MB, MI, MS)
|
||||
#define FISTTPLm(MD, MB, MI, MS) _FPULm(X86_FISTTP, MD, MB, MI, MS)
|
||||
#define FISTTPQm(MD, MB, MI, MS) _FPUm(X86_FISTTPQ, MD, MB, MI, MS)
|
||||
#define FLDSm(MD, MB, MI, MS) _FPUSm(X86_FLD, MD, MB, MI, MS)
|
||||
#define FLDDm(MD, MB, MI, MS) _FPUDm(X86_FLD, MD, MB, MI, MS)
|
||||
#define FLDTm(MD, MB, MI, MS) _FPUm(X86_FLDT, MD, MB, MI, MS)
|
||||
#define FLD1() _FPU(X86_FLD1)
|
||||
#define FLDL2T() _FPU(X86_FLDL2T)
|
||||
#define FLDL2E() _FPU(X86_FLDL2E)
|
||||
#define FLDPI() _FPU(X86_FLDPI)
|
||||
#define FLDLG2() _FPU(X86_FLDLG2)
|
||||
#define FLDLN2() _FPU(X86_FLDLN2)
|
||||
#define FLDZ() _FPU(X86_FLDZ)
|
||||
#define FMULSm(MD, MB, MI, MS) _FPUSm(X86_FMUL, MD, MB, MI, MS)
|
||||
#define FMULDm(MD, MB, MI, MS) _FPUDm(X86_FMUL, MD, MB, MI, MS)
|
||||
#define FMULP0r(RD) _FPUP0r(X86_FMUL, RD)
|
||||
#define FMULrr(RS, RD) _FPUrr(X86_FMUL, RS, RD)
|
||||
#define FMUL0r(RD) _FPU0r(X86_FMUL, RD)
|
||||
#define FMULr0(RS) _FPUr0(X86_FMUL, RS)
|
||||
#define FIMULWm(MD, MB, MI, MS) _FPUWm(X86_FIMUL, MD, MB, MI, MS)
|
||||
#define FIMULLm(MD, MB, MI, MS) _FPULm(X86_FIMUL, MD, MB, MI, MS)
|
||||
#define FNOP() _FPU(X86_FNOP)
|
||||
#define FPATAN() _FPU(X86_FPATAN)
|
||||
#define FPREM() _FPU(X86_FPREM)
|
||||
#define FPREM1() _FPU(X86_FPREM1)
|
||||
#define FPTAN() _FPU(X86_FPTAN)
|
||||
#define FRNDINT() _FPU(X86_FRNDINT)
|
||||
#define FSCALE() _FPU(X86_FSCALE)
|
||||
#define FSIN() _FPU(X86_FSIN)
|
||||
#define FSINCOS() _FPU(X86_FSINCOS)
|
||||
#define FSQRT() _FPU(X86_FSQRT)
|
||||
#define FSTSm(MD, MB, MI, MS) _FPUm(X86_FSTS, MD, MB, MI, MS)
|
||||
#define FSTLm(MD, MB, MI, MS) _FPUm(X86_FSTL, MD, MB, MI, MS)
|
||||
#define FSTr(RD) _FPUr(X86_FST, RD)
|
||||
#define FSTPSm(MD, MB, MI, MS) _FPUm(X86_FSTPS, MD, MB, MI, MS)
|
||||
#define FSTPLm(MD, MB, MI, MS) _FPUm(X86_FSTPL, MD, MB, MI, MS)
|
||||
#define FSTPTm(MD, MB, MI, MS) _FPUm(X86_FSTPT, MD, MB, MI, MS)
|
||||
#define FSTPr(RD) _FPUr(X86_FSTP, RD)
|
||||
#define FSUBSm(MD, MB, MI, MS) _FPUSm(X86_FSUB, MD, MB, MI, MS)
|
||||
#define FSUBDm(MD, MB, MI, MS) _FPUDm(X86_FSUB, MD, MB, MI, MS)
|
||||
#define FSUBP0r(RD) _FPUP0r(X86_FSUB, RD)
|
||||
#define FSUBrr(RS, RD) _FPUrr(X86_FSUB, RS, RD)
|
||||
#define FSUB0r(RD) _FPU0r(X86_FSUB, RD)
|
||||
#define FSUBr0(RS) _FPUr0(X86_FSUB, RS)
|
||||
#define FISUBWm(MD, MB, MI, MS) _FPUWm(X86_FISUB, MD, MB, MI, MS)
|
||||
#define FISUBLm(MD, MB, MI, MS) _FPULm(X86_FISUB, MD, MB, MI, MS)
|
||||
#define FSUBRSm(MD, MB, MI, MS) _FPUSm(X86_FSUBR, MD, MB, MI, MS)
|
||||
#define FSUBRDm(MD, MB, MI, MS) _FPUDm(X86_FSUBR, MD, MB, MI, MS)
|
||||
#define FSUBRP0r(RD) _FPUP0r(X86_FSUBR, RD)
|
||||
#define FSUBRrr(RS, RD) _FPUrr(X86_FSUBR, RS, RD)
|
||||
#define FSUBR0r(RD) _FPU0r(X86_FSUBR, RD)
|
||||
#define FSUBRr0(RS) _FPUr0(X86_FSUBR, RS)
|
||||
#define FISUBRWm(MD, MB, MI, MS) _FPUWm(X86_FISUBR, MD, MB, MI, MS)
|
||||
#define FISUBRLm(MD, MB, MI, MS) _FPULm(X86_FISUBR, MD, MB, MI, MS)
|
||||
#define FTST() _FPU(X86_FTST)
|
||||
#define FUCOMr(RD) _FPUr(X86_FUCOM, RD)
|
||||
#define FUCOMPr(RD) _FPUr(X86_FUCOMP, RD)
|
||||
#define FUCOMPP() _FPU(X86_FUCOMPP)
|
||||
#define FXAM() _FPU(X86_FXAM)
|
||||
#define FXCHr(RD) _FPUr(X86_FXCH, RD)
|
||||
#define FXTRACT() _FPU(X86_FXTRACT)
|
||||
#define FYL2X() _FPU(X86_FYL2X)
|
||||
#define FYL2XP1() _FPU(X86_FYL2XP1)
|
||||
|
||||
#endif /* X86_RTASM_H */
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Copyright 2004 Gwenole Beauchesne
|
||||
* Copyright 2004-2008 Gwenole Beauchesne
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@ -47,6 +47,7 @@
|
||||
static int verbose = 2;
|
||||
|
||||
#define TEST_INST_ALU 1
|
||||
#define TEST_INST_FPU 1
|
||||
#define TEST_INST_MMX 1
|
||||
#define TEST_INST_SSE 1
|
||||
#if TEST_INST_ALU
|
||||
@ -56,6 +57,11 @@ static int verbose = 2;
|
||||
#define TEST_INST_ALU_IMM_REG 1
|
||||
#define TEST_INST_ALU_MEM_REG 1
|
||||
#endif
|
||||
#if TEST_INST_FPU
|
||||
#define TEST_INST_FPU_UNARY 1
|
||||
#define TEST_INST_FPU_REG 1
|
||||
#define TEST_INST_FPU_MEM 1
|
||||
#endif
|
||||
#if TEST_INST_MMX
|
||||
#define TEST_INST_MMX_REG_REG 1
|
||||
#define TEST_INST_MMX_IMM_REG 1
|
||||
@ -87,6 +93,7 @@ static int verbose = 2;
|
||||
#define X86_MAX_ALU_REGS 8
|
||||
#define X86_MAX_SSE_REGS 8
|
||||
#endif
|
||||
#define X86_MAX_FPU_REGS 8
|
||||
#define X86_MAX_MMX_REGS 8
|
||||
|
||||
#define VALID_REG(r, b, n) (((unsigned)((r) - X86_##b)) < (n))
|
||||
@ -365,8 +372,13 @@ static int parse_reg(operand_t *op, int optype, char *buf)
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case '(':
|
||||
if ((p[1] == 't' || p[1] == 'T') && isdigit(p[3]) && p[4] == ')')
|
||||
len += 3, reg = X86_ST0 + (p[3] - '0');
|
||||
break;
|
||||
default:
|
||||
switch (p[1]) {
|
||||
case 't': case 'T': reg = X86_ST0; break;
|
||||
case 'p': case 'P': reg = X86_SP; break;
|
||||
case 'i': case 'I': reg = X86_SI; break;
|
||||
}
|
||||
@ -643,6 +655,21 @@ static void parse_insn(insn_t *ii, char *buf)
|
||||
static unsigned long n_tests, n_failures;
|
||||
static unsigned long n_all_tests, n_all_failures;
|
||||
|
||||
static bool check_unary(insn_t *ii, const char *name)
|
||||
{
|
||||
if (strcasecmp(ii->name, name) != 0) {
|
||||
fprintf(stderr, "ERROR: instruction mismatch, expected %s, got %s\n", name, ii->name);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (ii->n_operands != 0) {
|
||||
fprintf(stderr, "ERROR: instruction expected 0 operand, got %d\n", ii->n_operands);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool check_reg(insn_t *ii, const char *name, int r)
|
||||
{
|
||||
if (strcasecmp(ii->name, name) != 0) {
|
||||
@ -755,26 +782,13 @@ static bool check_imm_reg(insn_t *ii, const char *name, uint32 v, int d, int mod
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool check_mem_reg(insn_t *ii, const char *name, uint32 D, int B, int I, int S, int R, int Rpos = 1)
|
||||
static bool do_check_mem(insn_t *ii, uint32 D, int B, int I, int S, int Mpos)
|
||||
{
|
||||
if (strcasecmp(ii->name, name) != 0) {
|
||||
fprintf(stderr, "ERROR: instruction mismatch, expected %s, got %s\n", name, ii->name);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (ii->n_operands != 2) {
|
||||
fprintf(stderr, "ERROR: instruction expected 2 operands, got %d\n", ii->n_operands);
|
||||
return false;
|
||||
}
|
||||
|
||||
operand_t *mem = &ii->operands[Rpos ^ 1];
|
||||
operand_t *reg = &ii->operands[Rpos];
|
||||
|
||||
operand_t *mem = &ii->operands[Mpos];
|
||||
uint32 d = mem->disp;
|
||||
int b = mem->base;
|
||||
int i = mem->index;
|
||||
int s = mem->scale;
|
||||
int r = reg->reg;
|
||||
|
||||
if (d != D) {
|
||||
fprintf(stderr, "ERROR: instruction expected 0x%08x as displacement, got 0x%08x\n", D, d);
|
||||
@ -796,6 +810,41 @@ static bool check_mem_reg(insn_t *ii, const char *name, uint32 D, int B, int I,
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool check_mem(insn_t *ii, const char *name, uint32 D, int B, int I, int S)
|
||||
{
|
||||
if (strcasecmp(ii->name, name) != 0) {
|
||||
fprintf(stderr, "ERROR: instruction mismatch, expected %s, got %s\n", name, ii->name);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (ii->n_operands != 1) {
|
||||
fprintf(stderr, "ERROR: instruction expected 1 operand, got %d\n", ii->n_operands);
|
||||
return false;
|
||||
}
|
||||
|
||||
return do_check_mem(ii, D, B, I, S, 0);
|
||||
}
|
||||
|
||||
static bool check_mem_reg(insn_t *ii, const char *name, uint32 D, int B, int I, int S, int R, int Rpos = 1)
|
||||
{
|
||||
if (strcasecmp(ii->name, name) != 0) {
|
||||
fprintf(stderr, "ERROR: instruction mismatch, expected %s, got %s\n", name, ii->name);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (ii->n_operands != 2) {
|
||||
fprintf(stderr, "ERROR: instruction expected 2 operands, got %d\n", ii->n_operands);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!do_check_mem(ii, D, B, I, S, Rpos ^ 1))
|
||||
return false;
|
||||
|
||||
int r = ii->operands[Rpos].reg;
|
||||
|
||||
if (r != R) {
|
||||
fprintf(stderr, "ERROR: instruction expected r%d as reg operand, got r%d\n", R, r);
|
||||
return false;
|
||||
@ -1030,7 +1079,6 @@ int main(void)
|
||||
parse_insn(&ii, buffer);
|
||||
|
||||
if (!check_reg_reg(&ii, insns[i], s, d)) {
|
||||
fprintf(stderr, "s %d, d %d\n", s, d);
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
@ -1337,6 +1385,273 @@ int main(void)
|
||||
n_all_failures += n_failures;
|
||||
#endif
|
||||
|
||||
#if TEST_INST_FPU_UNARY
|
||||
printf("Testing FPU unary forms\n");
|
||||
n_tests = n_failures = 0;
|
||||
{
|
||||
set_target(block);
|
||||
uint8 *b = get_target();
|
||||
int i = 0;
|
||||
#define GEN(INSN, GENOP) do { \
|
||||
insns[i++] = INSN; \
|
||||
GENOP(); \
|
||||
} while (0)
|
||||
GEN("f2xm1", F2XM1);
|
||||
GEN("fabs", FABS);
|
||||
GEN("fchs", FCHS);
|
||||
GEN("fcompp", FCOMPP);
|
||||
GEN("fcos", FCOS);
|
||||
GEN("fdecstp", FDECSTP);
|
||||
GEN("fincstp", FINCSTP);
|
||||
GEN("fld1", FLD1);
|
||||
GEN("fldl2t", FLDL2T);
|
||||
GEN("fldl2e", FLDL2E);
|
||||
GEN("fldpi", FLDPI);
|
||||
GEN("fldlg2", FLDLG2);
|
||||
GEN("fldln2", FLDLN2);
|
||||
GEN("fldz", FLDZ);
|
||||
GEN("fnop", FNOP);
|
||||
GEN("fpatan", FPATAN);
|
||||
GEN("fprem", FPREM);
|
||||
GEN("fprem1", FPREM1);
|
||||
GEN("fptan", FPTAN);
|
||||
GEN("frndint", FRNDINT);
|
||||
GEN("fscale", FSCALE);
|
||||
GEN("fsin", FSIN);
|
||||
GEN("fsincos", FSINCOS);
|
||||
GEN("fsqrt", FSQRT);
|
||||
GEN("ftst", FTST);
|
||||
GEN("fucompp", FUCOMPP);
|
||||
GEN("fxam", FXAM);
|
||||
GEN("fxtract", FXTRACT);
|
||||
GEN("fyl2x", FYL2X);
|
||||
GEN("fyl2xp1", FYL2XP1);
|
||||
#undef GEN
|
||||
int last_insn = i;
|
||||
uint8 *e = get_target();
|
||||
|
||||
uint8 *p = b;
|
||||
i = 0;
|
||||
while (p < e) {
|
||||
int n = disass_x86(buffer, (uintptr)p);
|
||||
insn_t ii;
|
||||
parse_insn(&ii, buffer);
|
||||
|
||||
if (!check_unary(&ii, insns[i])) {
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
|
||||
p += n;
|
||||
i += 1;
|
||||
n_tests++;
|
||||
}
|
||||
if (i != last_insn)
|
||||
abort();
|
||||
}
|
||||
printf(" done %ld/%ld\n", n_tests - n_failures, n_tests);
|
||||
n_all_tests += n_tests;
|
||||
n_all_failures += n_failures;
|
||||
#endif
|
||||
|
||||
#if TEST_INST_FPU_REG
|
||||
printf("Testing FPU reg forms\n");
|
||||
n_tests = n_failures = 0;
|
||||
for (int r = 0; r < X86_MAX_FPU_REGS; r++) {
|
||||
set_target(block);
|
||||
uint8 *b = get_target();
|
||||
int i = 0;
|
||||
#define GENr(INSN, GENOP) do { \
|
||||
insns[i] = INSN; \
|
||||
modes[i] = 0; \
|
||||
i++, GENOP##r(r); \
|
||||
} while (0)
|
||||
#define GENr0(INSN, GENOP) do { \
|
||||
insns[i] = INSN; \
|
||||
modes[i] = 1; \
|
||||
i++, GENOP##r0(r); \
|
||||
} while (0)
|
||||
#define GEN0r(INSN, GENOP) do { \
|
||||
insns[i] = INSN; \
|
||||
modes[i] = 2; \
|
||||
i++, GENOP##0r(r); \
|
||||
} while (0)
|
||||
GENr("fcom", FCOM);
|
||||
GENr("fcomp", FCOMP);
|
||||
GENr("ffree", FFREE);
|
||||
GENr("fxch", FXCH);
|
||||
GENr("fst", FST);
|
||||
GENr("fstp", FSTP);
|
||||
GENr("fucom", FUCOM);
|
||||
GENr("fucomp", FUCOMP);
|
||||
GENr0("fadd", FADD);
|
||||
GENr0("fcmovb", FCMOVB);
|
||||
GENr0("fcmove", FCMOVE);
|
||||
GENr0("fcmovbe", FCMOVBE);
|
||||
GENr0("fcmovu", FCMOVU);
|
||||
GENr0("fcmovnb", FCMOVNB);
|
||||
GENr0("fcmovne", FCMOVNE);
|
||||
GENr0("fcmovnbe", FCMOVNBE);
|
||||
GENr0("fcmovnu", FCMOVNU);
|
||||
GENr0("fcomi", FCOMI);
|
||||
GENr0("fcomip", FCOMIP);
|
||||
GENr0("fucomi", FUCOMI);
|
||||
GENr0("fucomip", FUCOMIP);
|
||||
GENr0("fdiv", FDIV);
|
||||
GENr0("fdivr", FDIVR);
|
||||
GENr0("fmul", FMUL);
|
||||
GENr0("fsub", FSUB);
|
||||
GENr0("fsubr", FSUBR);
|
||||
#undef GEN0r
|
||||
#undef GENr0
|
||||
#undef GENr
|
||||
int last_insn = i;
|
||||
uint8 *e = get_target();
|
||||
|
||||
uint8 *p = b;
|
||||
i = 0;
|
||||
while (p < e) {
|
||||
int n = disass_x86(buffer, (uintptr)p);
|
||||
insn_t ii;
|
||||
parse_insn(&ii, buffer);
|
||||
|
||||
switch (modes[i]) {
|
||||
case 0:
|
||||
if (!check_reg(&ii, insns[i], r)) {
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (!check_reg_reg(&ii, insns[i], r, 0)) {
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (!check_reg_reg(&ii, insns[i], 0, r)) {
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
p += n;
|
||||
i += 1;
|
||||
n_tests++;
|
||||
}
|
||||
if (i != last_insn)
|
||||
abort();
|
||||
}
|
||||
printf(" done %ld/%ld\n", n_tests - n_failures, n_tests);
|
||||
n_all_tests += n_tests;
|
||||
n_all_failures += n_failures;
|
||||
#endif
|
||||
|
||||
#if TEST_INST_FPU_MEM
|
||||
printf("Testing FPU mem forms\n");
|
||||
n_tests = n_failures = 0;
|
||||
for (int d = 0; d < off_table_count; d++) {
|
||||
const uint32 D = off_table[d];
|
||||
for (int B = -1; B < X86_MAX_ALU_REGS; B++) {
|
||||
for (int I = -1; I < X86_MAX_ALU_REGS; I++) {
|
||||
if (I == X86_RSP)
|
||||
continue;
|
||||
for (int S = 1; S < 16; S *= 2) {
|
||||
if (I == -1 && S > 1)
|
||||
continue;
|
||||
set_target(block);
|
||||
uint8 *b = get_target();
|
||||
int i = 0;
|
||||
#define GEN(INSN, GENOP) do { \
|
||||
insns[i++] = INSN; \
|
||||
GENOP##m(D, B, I, S); \
|
||||
} while (0)
|
||||
GEN("fadds", FADDS);
|
||||
GEN("faddl", FADDD);
|
||||
GEN("fiadd", FIADDW);
|
||||
GEN("fiaddl", FIADDL);
|
||||
GEN("fbld", FBLD);
|
||||
GEN("fbstp", FBSTP);
|
||||
GEN("fcoms", FCOMS);
|
||||
GEN("fcoml", FCOMD);
|
||||
GEN("fcomps", FCOMPS);
|
||||
GEN("fcompl", FCOMPD);
|
||||
GEN("fdivs", FDIVS);
|
||||
GEN("fdivl", FDIVD);
|
||||
GEN("fidiv", FIDIVW);
|
||||
GEN("fidivl", FIDIVL);
|
||||
GEN("fdivrs", FDIVRS);
|
||||
GEN("fdivrl", FDIVRD);
|
||||
GEN("fidivr", FIDIVRW);
|
||||
GEN("fidivrl", FIDIVRL);
|
||||
GEN("ficom", FICOMW);
|
||||
GEN("ficoml", FICOML);
|
||||
GEN("ficomp", FICOMPW);
|
||||
GEN("ficompl", FICOMPL);
|
||||
GEN("fild", FILDW);
|
||||
GEN("fildl", FILDL);
|
||||
GEN("fildll", FILDQ);
|
||||
GEN("fist", FISTW);
|
||||
GEN("fistl", FISTL);
|
||||
GEN("fistp", FISTPW);
|
||||
GEN("fistpl", FISTPL);
|
||||
GEN("fistpll", FISTPQ);
|
||||
GEN("fisttp", FISTTPW);
|
||||
GEN("fisttpl", FISTTPL);
|
||||
GEN("fisttpll", FISTTPQ);
|
||||
GEN("flds", FLDS);
|
||||
GEN("fldl", FLDD);
|
||||
GEN("fldt", FLDT);
|
||||
GEN("fmuls", FMULS);
|
||||
GEN("fmull", FMULD);
|
||||
GEN("fimul", FIMULW);
|
||||
GEN("fimull", FIMULL);
|
||||
GEN("fsts", FSTS);
|
||||
GEN("fstl", FSTL);
|
||||
GEN("fstps", FSTPS);
|
||||
GEN("fstpl", FSTPL);
|
||||
GEN("fstpt", FSTPT);
|
||||
GEN("fsubs", FSUBS);
|
||||
GEN("fsubl", FSUBD);
|
||||
GEN("fisub", FISUBW);
|
||||
GEN("fisubl", FISUBL);
|
||||
GEN("fsubrs", FSUBRS);
|
||||
GEN("fsubrl", FSUBRD);
|
||||
GEN("fisubr", FISUBRW);
|
||||
GEN("fisubrl", FISUBRL);
|
||||
#undef GEN
|
||||
int last_insn = i;
|
||||
uint8 *e = get_target();
|
||||
|
||||
uint8 *p = b;
|
||||
i = 0;
|
||||
while (p < e) {
|
||||
int n = disass_x86(buffer, (uintptr)p);
|
||||
insn_t ii;
|
||||
parse_insn(&ii, buffer);
|
||||
|
||||
if (!check_mem(&ii, insns[i], D, B, I, S)) {
|
||||
show_instruction(buffer, p);
|
||||
n_failures++;
|
||||
}
|
||||
|
||||
p += n;
|
||||
i += 1;
|
||||
n_tests++;
|
||||
show_status(n_tests);
|
||||
}
|
||||
if (i != last_insn)
|
||||
abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
printf(" done %ld/%ld\n", n_tests - n_failures, n_tests);
|
||||
n_all_tests += n_tests;
|
||||
n_all_failures += n_failures;
|
||||
#endif
|
||||
|
||||
#if TEST_INST_MMX_REG_REG
|
||||
printf("Testing MMX reg,reg forms\n");
|
||||
n_tests = n_failures = 0;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user