diff --git a/BasiliskII/src/uae_cpu/gencpu.c b/BasiliskII/src/uae_cpu/gencpu.c index 8ab51fb3..2c802133 100644 --- a/BasiliskII/src/uae_cpu/gencpu.c +++ b/BasiliskII/src/uae_cpu/gencpu.c @@ -910,22 +910,20 @@ static void gen_opcode (unsigned long int opcode) genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); break; case i_SBCD: - /* Let's hope this works... */ genamode (curi->smode, "srcreg", curi->size, "src", 1, 0); genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0); start_brace (); printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n"); printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n"); - printf ("\tuae_u16 newv;\n"); - printf ("\tint cflg;\n"); - printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n"); - printf ("\tnewv = newv_hi + (newv_lo & 0xF);"); - printf ("\tcflg = (newv_hi & 0x1F0) > 0x90;\n"); - printf ("\tSET_CFLG (cflg);\n"); + printf ("\tuae_u16 newv, tmp_newv;\n"); + printf ("\tint bcd = 0;\n"); + printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n"); + printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n"); + printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n"); + printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n"); duplicate_carry (); - printf ("\tif (cflg) newv -= 0x60;\n"); genflags (flag_zn, curi->size, "newv", "", ""); - genflags (flag_sv, curi->size, "newv", "src", "dst"); + printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n"); genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); break; case i_ADD: @@ -957,16 +955,16 @@ static void gen_opcode (unsigned long int opcode) start_brace (); printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n"); printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n"); - printf ("\tuae_u16 newv;\n"); + printf ("\tuae_u16 newv, tmp_newv;\n"); printf ("\tint cflg;\n"); - printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n"); - printf ("\tnewv = newv_hi + newv_lo;"); - printf ("\tcflg = (newv & 0x1F0) > 0x90;\n"); + printf ("\tnewv = tmp_newv = newv_hi + newv_lo;"); + printf ("\tif (newv_lo > 9) { newv += 6; }\n"); + printf ("\tcflg = (newv & 0x3F0) > 0x90;\n"); + printf ("\tif (cflg) newv += 0x60;\n"); printf ("\tSET_CFLG (cflg);\n"); duplicate_carry (); - printf ("\tif (cflg) newv += 0x60;\n"); genflags (flag_zn, curi->size, "newv", "", ""); - genflags (flag_sv, curi->size, "newv", "src", "dst"); + printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n"); genastore ("newv", curi->dmode, "dstreg", curi->size, "dst"); break; case i_NEG: @@ -990,12 +988,12 @@ static void gen_opcode (unsigned long int opcode) printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n"); printf ("\tuae_u16 newv;\n"); printf ("\tint cflg;\n"); - printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n"); - printf ("\tnewv = newv_hi + (newv_lo & 0xF);"); - printf ("\tcflg = cflg = (newv_hi & 0x1F0) > 0x90;\n"); + printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n"); + printf ("\tnewv = newv_hi + newv_lo;"); + printf ("\tcflg = (newv & 0x1F0) > 0x90;\n"); + printf ("\tif (cflg) newv -= 0x60;\n"); printf ("\tSET_CFLG (cflg);\n"); duplicate_carry(); - printf ("\tif (cflg) newv -= 0x60;\n"); genflags (flag_zn, curi->size, "newv", "", ""); genastore ("newv", curi->smode, "srcreg", curi->size, "src"); break; diff --git a/BasiliskII/src/uae_cpu/readcpu.cpp b/BasiliskII/src/uae_cpu/readcpu.cpp index 82a2c418..708f2f4f 100644 --- a/BasiliskII/src/uae_cpu/readcpu.cpp +++ b/BasiliskII/src/uae_cpu/readcpu.cpp @@ -339,7 +339,6 @@ static void build_insn (int insn) case 'A': srcmode = Areg; switch (opcstr[pos++]) { - case 'l': srcmode = absl; break; case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; default: abort(); @@ -349,6 +348,9 @@ static void build_insn (int insn) case 'P': srcmode = Aipi; pos++; break; } break; + case 'L': + srcmode = absl; + break; case '#': switch (opcstr[pos++]) { case 'z': srcmode = imm; break; @@ -395,7 +397,7 @@ static void build_insn (int insn) } break; case 'p': srcmode = immi; srcreg = bitval[bitp]; - if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ?? + if (CPU_EMU_SIZE < 5) { /* 0..3 */ srcgather = 1; srctype = 7; @@ -526,20 +528,27 @@ static void build_insn (int insn) case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; default: abort(); } + if (dstpos < 0 || dstpos >= 32) + abort(); break; case 'A': destmode = Areg; switch (opcstr[pos++]) { - case 'l': destmode = absl; break; case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; + case 'x': destreg = 0; dstgather = 0; dstpos = 0; break; default: abort(); } + if (dstpos < 0 || dstpos >= 32) + abort(); switch (opcstr[pos]) { case 'p': destmode = Apdi; pos++; break; case 'P': destmode = Aipi; pos++; break; } break; + case 'L': + destmode = absl; + break; case '#': switch (opcstr[pos++]) { case 'z': destmode = imm; break; diff --git a/BasiliskII/src/uae_cpu/table68k b/BasiliskII/src/uae_cpu/table68k index 90ea8659..1d9438d8 100644 --- a/BasiliskII/src/uae_cpu/table68k +++ b/BasiliskII/src/uae_cpu/table68k @@ -25,7 +25,7 @@ % % Arp: --> -(Ar) % ArP: --> (Ar)+ -% Al : --> (xxx).L +% L: (xxx).L % % Fields on a line: % 16 chars bitpattern : @@ -146,18 +146,14 @@ 0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd] 0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar -% This variant of ADDQ is word and long sized only 0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg] 0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg] 0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg] - -% This variant of SUBQ is word and long sized only 0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg] 0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg] 0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg] - -0101 cccc 1100 1rrr:00:-----:+++++:31: DBcc.W Dr,#1 -0101 cccc 11dd dDDD:00:-----:+++++:20: Scc.B d[!Areg] +0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1 +0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg] 0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1 0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2 0101 cccc 1111 1100:20:?????:?????:00: TRAPcc @@ -168,9 +164,9 @@ 0110 0001 0000 0000:00://///://///:40: BSR.W #1 0110 0001 IIII IIII:00://///://///:40: BSR.B #i 0110 0001 1111 1111:00://///://///:40: BSR.L #2 -0110 CCCC 0000 0000:00:-----:+++++:40: Bcc.W #1 -0110 CCCC IIII IIII:00:-----:+++++:40: Bcc.B #i -0110 CCCC 1111 1111:00:-----:+++++:40: Bcc.L #2 +0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1 +0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i +0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2 0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr @@ -256,8 +252,9 @@ 1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar 1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar 1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p -1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,ARP -1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],Al -1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Areg-Aipi] -1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],Al -1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Aipi-Aind] +% destination register number is encoded in the following word +1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi] +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind]