gbeauche
4d60dea4ee
Revert last change until I can check myself...
2004-07-11 08:12:21 +00:00
gbeauche
58e74f3ca0
Enable ethernet everywhere, several users got it to work. Hangs may be
...
unrelated to ethernet code anyway and ethernet driver should be endian
safe nowadays.
2004-07-11 07:54:56 +00:00
gbeauche
623a804814
Remove "native" EmulOp stuff as it is useless and duplicates functionalities
2004-07-11 06:42:28 +00:00
gbeauche
3e5c98c7d4
Performance of VOSF is heuristically determined at run-time, so have to
...
initialize SIGSEGV handlers early, as in Basilisk II. Besides, also add
missing call to vm_init() in case host system doesn't have MAP_ANON.
2004-06-26 15:26:18 +00:00
gbeauche
0dcb2b4516
SDL support in SheepShaver too, though it doesn't work in native mode
...
on Linux/ppc as libSDL is pulling in libpthread which conflicts with
our sheepthreads.
2004-06-24 15:37:26 +00:00
gbeauche
e0a76f9e38
Don't handle XLM_IRQ_NEST atomically in emulated mode. That's useless since
...
this variable is modified only within a single thread and interrupts are
not handled asynchronously.
2004-06-22 17:10:08 +00:00
gbeauche
070ac7079f
Always handle interrupt even if InterruptFlags == 0, though it should not
...
really happen in practise.
2004-06-22 14:18:35 +00:00
gbeauche
301d3a3192
STATS: Account for all interrupts, but still count native interrupts. It
...
turns out that for a regular bootup sequence to the Finder, less than 30%
interrupts triggered were in native mode.
Default EMUL_TIME_STATS to 0, end user probably doesn't want garbage to
be printed to his console.
2004-06-05 07:09:38 +00:00
gbeauche
389dd61d0d
Check for SIGSEGVs from DR Cache code too.
2004-05-31 10:08:31 +00:00
gbeauche
05bd5f40b4
Fix NativeOp code generation, especially in PPC_REENTRANT_JIT mode
2004-05-23 05:28:12 +00:00
gbeauche
bd6eaf680a
Get rid of old (and broken) ASYNC_IRQ / MUTICORE code
2004-05-20 12:33:58 +00:00
gbeauche
3a960764ea
Don't allow "recursive" NanoKernel interrupts
2004-05-20 11:47:27 +00:00
gbeauche
ec6c98035b
Better interrupt context checking code
2004-05-20 11:05:30 +00:00
gbeauche
c3f2342f47
Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly
...
GPR macro definition.
Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.
2004-05-19 21:23:17 +00:00
gbeauche
ae0e7293dd
Don't take an EMUL_OP mode switch for Microseconds() and SynchIdleTime()
2004-05-15 17:26:28 +00:00
gbeauche
7da40bee5c
Handle SAFE_INTERRUPT_PPC to check possible nested calls (and this happens)
2004-05-12 15:54:23 +00:00
gbeauche
ba7bfc478e
Extend NativeOp count to 64 (6-bit value), aka fix NATIVE_FILLRECT opcpdes.
...
Translate NQD_{bitblt,fillrect,invrect} to direct native calls.
Use Mac2HostAddr() for converting Mac base address to native.
2004-04-22 22:54:47 +00:00
gbeauche
8b40a7e721
NQD: use ReadMacInt*() and WriteMacInt*() accessors, i.e. code should now
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be little-endian and 64-bit safe.
2004-04-22 21:45:18 +00:00
gbeauche
b4ac3fb507
Basic fillrect/invrect NQD. Code may need to be factored out somehow.
...
Verify that bitblt NQD transfer modes are really CopyBits() ones [MB5].
2004-04-22 20:57:31 +00:00
gbeauche
a65a6c6db2
Start Native QuickDraw acceleration
2004-04-18 23:03:53 +00:00
gbeauche
47348e8120
16-byte aligned memory allocator will try the following functions in-order
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(determined at compile-time): posix_memalign, memalign, valloc, malloc.
2004-02-24 14:09:12 +00:00
gbeauche
ae93ea2f16
Make SheepShaver work with OS 8.6 out-of-the-box with no extra patch for
...
the time being. i.e. ignore writes to the zero page when faking SCSIGlobals
2004-02-24 11:12:54 +00:00
gbeauche
cdab3d6975
we have to 16-byte align sheepshaver_cpu object has it contains SSE values
...
that require this alignment.
2004-02-20 17:20:15 +00:00
gbeauche
18893e22bd
GCC 3.4 does not allow the lazy_allocator instantiation, the other form is
...
not supported by any GCC but ICC accepts it.
2004-02-16 15:34:55 +00:00
gbeauche
313cddeeb2
AltiVec emulation! ;-)
2004-02-15 17:17:37 +00:00
gbeauche
10b9ab2c34
Generate PowerPC code wrapping GetResource() replacements. That way, it's
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a normal PPC function invocation that can be JIT compiled to native code
instead of nesting execute() calls which may lead to use the interpreter
(this took around 11% of total execution time on boot, downto 3%).
Also, optimize some SheepShaver EmulOps and actually report non-CTI.
2004-01-24 11:28:06 +00:00
cebix
2d5de1af9d
Happy New Year! :)
2004-01-12 15:37:24 +00:00
gbeauche
97ce4fdc75
Match Linux/ppc native version better: jump to ROM with EmulatorData in r4,
...
preserve CR & XER registers on EmulOp.
2003-12-25 23:54:36 +00:00
gbeauche
bbde2a2054
Use an alternate stack base while servicing PowerPC interrupts.
2003-12-05 13:37:56 +00:00
gbeauche
091a219280
Use a unique ExecuteNative() interface in any case, i.e. native & emulated
2003-12-04 23:37:38 +00:00
gbeauche
328bb9f239
Add new thunking system for 64-bit fixes.
2003-12-04 17:26:38 +00:00
gbeauche
7ebe0347bf
Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc &
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max_pc members of block info. Increase -finline-limit to 10000 for older gcc
2003-12-03 10:52:50 +00:00
gbeauche
4a3cd024ed
better handling of static translation cache allocation, handle nested
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execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.
2003-11-30 17:21:53 +00:00
gbeauche
73d51962f6
Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.
...
The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.
Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
2003-11-24 23:45:52 +00:00
gbeauche
b66d8ef433
Fix "ignoresegv" case to actually skip the faulty instruction. Merge
...
conditions to skip instruction on SIGSEGVfrom PowerPC native mode. The
instruction skipper takes care to set the output register to 0.
2003-11-10 16:23:58 +00:00
gbeauche
0260210ddf
- XLM_IRQ_NEST is always in native byte order format since any write to
...
this variable go through {Enable,Disable}Interrupt().
- Add Ether thunks but only for WORDS_BIGENDIAN case since we do need more
complicated translation functions.
2003-11-10 15:11:44 +00:00
gbeauche
8c40d739b6
Add some statistics for interrupt handling, Execute68k/Trap, MacOS & NativeOp
2003-11-04 20:48:29 +00:00
gbeauche
a42281aad1
Implement partial block cache invalidation. Rewrite core cached blocks
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execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.
2003-11-03 21:28:32 +00:00
gbeauche
f0ea192460
Optimized pointers to non virtual member functions. This reduces space
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and overhead since runtime checks are eliminated. Actually, it yields
up to 10% performance improvement with specialized decoders.
2003-11-02 14:48:20 +00:00
gbeauche
89d0f9ca29
Integrate spcflags handling code to kpx_cpu core. We can also remove
...
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.
2003-11-01 15:15:31 +00:00
gbeauche
9ce43c6cf3
Fix ASYNC_IRQ build but locks may still happen. Note that with a predecode
...
cache, checking for pending interrupts may not be the bottle neck nowadays.
2003-10-26 14:16:40 +00:00
gbeauche
60d34a6816
Rewrite interrupts handling code so that the emulator can work with a
...
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.
Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.
2003-10-26 13:59:04 +00:00
gbeauche
d766049d59
- enable multicore cpu emulation with ASYNC_IRQ
...
- move atomic_* operations to main_unix so that they could use spinlocks or
other platform-specific locking mechanisms
2003-10-26 09:14:14 +00:00
gbeauche
ccf89d9efb
Preserve CR in execute_68k(). This enables MacOS 8.6 to work. ;-)
2003-10-19 21:37:43 +00:00
gbeauche
7e0dccc544
- Handle MakeExecutable() replacement
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- Disable predecode cache in CVS for now
- Fix flight recorder ordering in predecode cache mode
2003-10-12 05:44:17 +00:00
gbeauche
ebb67f0421
- Minor optimization to execute_ppc() as we apparently don't need to move
...
target PC into CTR.
- Fix breakage introduced during little endian fixing. We now assume that
MacOS doesn't rely on any PPC register that may have been saved on top
of it stack. i.e. register state is saved onto native stack.
2003-10-11 09:33:27 +00:00
gbeauche
19053d4992
little endian fixes, note that trampolines are still not 64-bit clean either
2003-09-29 22:50:31 +00:00
gbeauche
b8b139faf2
- Share EmulatorData & KernelData struct definitions
...
- Introduce new SheepShaver data area for alternate stacks, thunks, etc.
- Experimental asynchronous interrupts handling. This improves performance
by 30% but some (rare) lockups may occur. To be debugged!
2003-09-29 15:46:09 +00:00
gbeauche
1c2fa89e31
use B2 sigsegv API instead of rewriting yet another sigsegv handler for x86
2003-09-29 07:05:15 +00:00
gbeauche
3851071ecd
Try to handle XLM_IRQ_NEST atomically in emulated PPC views. Fix placement
...
of fake SCSIGlobals (disabled for now). Switch back to mono core emulation
until things are debugged enough. Implement get_resource() et al.
2003-09-28 21:27:34 +00:00