11 Commits

Author	SHA1	Message	Date
Jonas Maebe	a84735d3e9	Add FP fres instruction emulation	2019-12-27 16:58:50 +01:00
Jonas Maebe	75b333f805	Add FP frsqrte instruction emulation ... Also renamed the frsqrt opcode to frsqrte to match the manuals (the vector version is also an estimate)	2019-12-23 18:19:49 +01:00
gbeauche	0a2f9d3f03	Add fsel instruction emulation (VEX's jm-ppc-test -f)	2006-07-04 04:25:02 +00:00
gbeauche	8db2a3ef62	implement lvsl/lvsr instructions	2005-04-15 17:03:49 +00:00
gbeauche	df0d5d2a41	Happy New Year 2005!	2005-01-30 21:48:22 +00:00
gbeauche	a8a235345c	implement mcrxr instruction	2004-12-18 22:13:47 +00:00
gbeauche	ea3c6801ab	Experiment with generic AltiVec optimizations for V4SF, V2DI operands (+60%)	2004-02-16 23:17:27 +00:00
gbeauche	d10a3586f1	Year got increased "recently". ;-)	2004-02-16 10:57:07 +00:00
gbeauche	313cddeeb2	AltiVec emulation! ;-)	2004-02-15 17:17:37 +00:00
gbeauche	82808234fa	Merge in FP exceptions support but disable it for now as it is incomplete ... and slower. Implement mcrfs. Fix and optimize fctiw with native rounding.	2004-01-24 16:43:45 +00:00
gbeauche	73d51962f6	Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC. ... The merge probably got wrong as there are some problems probably due to the experiment begining with CR deferred evaluation. With nbench/ppc, performance improvement was around 2x. With nbench on x86, performance improvement was around 4x on average. Incompatible change: instr_info_t has a new field in the middle. But since insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.	2003-11-24 23:45:52 +00:00