mirror of
https://github.com/kanjitalk755/macemu.git
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268 lines
8.0 KiB
C
268 lines
8.0 KiB
C
/*
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* cpummu.h - MMU emulation
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*
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* Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
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*
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* Inspired by UAE MMU patch
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*
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* This file is part of the ARAnyM project which builds a new and powerful
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* TOS/FreeMiNT compatible virtual machine running on almost any hardware.
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*
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* ARAnyM is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* ARAnyM is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with ARAnyM; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPUMMU_H
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#define CPUMMU_H
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#include "registers.h"
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# include <cstdlib>
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#define MMU_TEST_PTEST 1
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#define MMU_TEST_VERBOSE 2
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#define MMU_TEST_FORCE_TABLE_SEARCH 4
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#define MMU_TEST_NO_BUSERR 8
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extern void mmu_dump_tables(void);
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#define MMU_TTR_LOGICAL_BASE 0xff000000
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#define MMU_TTR_LOGICAL_MASK 0x00ff0000
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#define MMU_TTR_BIT_ENABLED (1 << 15)
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#define MMU_TTR_BIT_SFIELD_ENABLED (1 << 14)
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#define MMU_TTR_BIT_SFIELD_SUPER (1 << 13)
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#define MMU_TTR_SFIELD_SHIFT 13
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#define MMU_TTR_UX_MASK ((1 << 9) | (1 << 8))
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#define MMU_TTR_UX_SHIFT 8
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#define MMU_TTR_CACHE_MASK ((1 << 6) | (1 << 5))
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#define MMU_TTR_CACHE_SHIFT 5
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#define MMU_TTR_BIT_WRITE_PROTECT (1 << 2)
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#define MMU_UDT_MASK 3
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#define MMU_PDT_MASK 3
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#define MMU_DES_WP 4
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#define MMU_DES_USED 8
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/* page descriptors only */
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#define MMU_DES_MODIFIED 16
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#define MMU_DES_SUPER (1 << 7)
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#define MMU_DES_GLOBAL (1 << 10)
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#define MMU_ROOT_PTR_ADDR_MASK 0xfffffe00
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#define MMU_PTR_PAGE_ADDR_MASK_8 0xffffff80
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#define MMU_PTR_PAGE_ADDR_MASK_4 0xffffff00
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#define MMU_PAGE_INDIRECT_MASK 0xfffffffc
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#define MMU_PAGE_ADDR_MASK_8 0xffffe000
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#define MMU_PAGE_ADDR_MASK_4 0xfffff000
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#define MMU_PAGE_UR_MASK_8 ((1 << 12) | (1 << 11))
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#define MMU_PAGE_UR_MASK_4 (1 << 11)
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#define MMU_PAGE_UR_SHIFT 11
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#define MMU_MMUSR_ADDR_MASK 0xfffff000
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#define MMU_MMUSR_B (1 << 11)
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#define MMU_MMUSR_G (1 << 10)
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#define MMU_MMUSR_U1 (1 << 9)
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#define MMU_MMUSR_U0 (1 << 8)
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#define MMU_MMUSR_Ux (MMU_MMUSR_U1 | MMU_MMUSR_U0)
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#define MMU_MMUSR_S (1 << 7)
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#define MMU_MMUSR_CM ((1 << 6) | ( 1 << 5))
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#define MMU_MMUSR_M (1 << 4)
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#define MMU_MMUSR_W (1 << 2)
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#define MMU_MMUSR_T (1 << 1)
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#define MMU_MMUSR_R (1 << 0)
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/* special status word (access error stack frame) */
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#define MMU_SSW_TM 0x0007
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#define MMU_SSW_TT 0x0018
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#define MMU_SSW_SIZE 0x0060
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#define MMU_SSW_SIZE_B 0x0020
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#define MMU_SSW_SIZE_W 0x0040
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#define MMU_SSW_SIZE_L 0x0000
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#define MMU_SSW_RW 0x0100
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#define MMU_SSW_LK 0x0200
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#define MMU_SSW_ATC 0x0400
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#define MMU_SSW_MA 0x0800
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#define TTR_I0 4
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#define TTR_I1 5
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#define TTR_D0 6
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#define TTR_D1 7
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#define TTR_NO_MATCH 0
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#define TTR_NO_WRITE 1
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#define TTR_OK_MATCH 2
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struct mmu_atc_line {
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uae_u16 tag;
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unsigned tt : 1;
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unsigned valid_data : 1;
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unsigned valid_inst : 1;
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unsigned global : 1;
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unsigned modified : 1;
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unsigned write_protect : 1;
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unsigned hw : 1;
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unsigned bus_fault : 1;
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uaecptr phys;
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};
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/*
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* We don't need to store the whole logical address in the atc cache, as part of
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* it is encoded as index into the cache. 14 bits of the address are stored in
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* the tag, this means at least 6 bits must go into the index. The upper two
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* bits of the tag define the type of data in the atc line:
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* - 00: a normal memory address
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* - 11: invalid memory address or hardware access
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* (generated via ~ATC_TAG(addr) in the slow path)
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* - 10: empty atc line
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*/
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#define ATC_TAG_SHIFT 18
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#define ATC_TAG(addr) ((uae_u32)(addr) >> ATC_TAG_SHIFT)
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#define ATC_L1_SIZE_LOG 8
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#define ATC_L1_SIZE (1 << ATC_L1_SIZE_LOG)
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#define ATC_L1_INDEX(addr) (((addr) >> 12) % ATC_L1_SIZE)
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/*
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* first level atc cache
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* indexed by [super][data][rw][idx]
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*/
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typedef struct mmu_atc_line mmu_atc_l1_array[2][2][ATC_L1_SIZE];
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extern mmu_atc_l1_array atc_l1[2];
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extern mmu_atc_l1_array *current_atc;
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#define ATC_L2_SIZE_LOG 12
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#define ATC_L2_SIZE (1 << ATC_L2_SIZE_LOG)
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#define ATC_L2_INDEX(addr) ((((addr) >> 12) ^ ((addr) >> (32 - ATC_L2_SIZE_LOG))) % ATC_L2_SIZE)
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extern struct mmu_atc_line atc_l2[2][ATC_L2_SIZE];
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/*
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* lookup address in the level 1 atc cache,
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* the data and write arguments are constant in the common,
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* thus allows gcc to generate a constant offset.
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*/
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static ALWAYS_INLINE int mmu_lookup(uaecptr addr, bool data, bool write,
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struct mmu_atc_line **cl)
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{
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addr >>= 12;
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*cl = &(*current_atc)[data][write][addr % ATC_L1_SIZE];
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return (*cl)->tag == addr >> (ATC_TAG_SHIFT - 12);
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}
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/*
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* similiar to mmu_user_lookup, but for the use of the moves instruction
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*/
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static ALWAYS_INLINE int mmu_user_lookup(uaecptr addr, bool super, bool data,
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bool write, struct mmu_atc_line **cl)
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{
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addr >>= 12;
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*cl = &atc_l1[super][data][write][addr % ATC_L1_SIZE];
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return (*cl)->tag == addr >> (ATC_TAG_SHIFT - 12);
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}
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extern REGPARAM2 uae_u16 mmu_get_word_unaligned(uaecptr addr, int data);
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extern REGPARAM2 uae_u32 mmu_get_long_unaligned(uaecptr addr, int data);
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extern REGPARAM2 uae_u8 mmu_get_byte_slow(uaecptr addr, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 uae_u16 mmu_get_word_slow(uaecptr addr, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 uae_u32 mmu_get_long_slow(uaecptr addr, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 uae_u64 mmu_get_quad_slow(uaecptr addr, int super, int data,
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struct mmu_atc_line *cl);
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extern REGPARAM2 void mmu_put_word_unaligned(uaecptr addr, uae_u16 val, int data);
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extern REGPARAM2 void mmu_put_long_unaligned(uaecptr addr, uae_u32 val, int data);
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extern REGPARAM2 void mmu_put_byte_slow(uaecptr addr, uae_u8 val, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 void mmu_put_word_slow(uaecptr addr, uae_u16 val, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 void mmu_put_long_slow(uaecptr addr, uae_u32 val, int super, int data,
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int size, struct mmu_atc_line *cl);
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extern REGPARAM2 void mmu_put_quad_slow(uaecptr addr, uae_u64 val, int super, int data,
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struct mmu_atc_line *cl);
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extern void mmu_make_transparent_region(uaecptr baseaddr, uae_u32 size, int datamode);
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static inline void mmu_set_ttr(int regno, uae_u32 val)
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{
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uae_u32 * ttr;
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switch(regno) {
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case TTR_I0: ttr = ®s.itt0; break;
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case TTR_I1: ttr = ®s.itt1; break;
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case TTR_D0: ttr = ®s.dtt0; break;
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case TTR_D1: ttr = ®s.dtt1; break;
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default: abort();
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}
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*ttr = val;
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}
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static inline void mmu_set_mmusr(uae_u32 val)
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{
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regs.mmusr = val;
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}
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#define FC_DATA (regs.s ? 5 : 1)
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#define FC_INST (regs.s ? 6 : 2)
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extern uaecptr REGPARAM2 mmu_translate(uaecptr addr, int super, int data, int write);
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extern uae_u32 REGPARAM2 sfc_get_long(uaecptr addr);
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extern uae_u16 REGPARAM2 sfc_get_word(uaecptr addr);
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extern uae_u8 REGPARAM2 sfc_get_byte(uaecptr addr);
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extern void REGPARAM2 dfc_put_long(uaecptr addr, uae_u32 val);
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extern void REGPARAM2 dfc_put_word(uaecptr addr, uae_u16 val);
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extern void REGPARAM2 dfc_put_byte(uaecptr addr, uae_u8 val);
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extern void REGPARAM2 mmu_flush_atc(uaecptr addr, bool super, bool global);
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extern void REGPARAM2 mmu_flush_atc_all(bool global);
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extern void REGPARAM2 mmu_op(uae_u32 opcode, uae_u16 extra);
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#ifdef FULLMMU
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extern void REGPARAM2 mmu_reset(void);
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extern void REGPARAM2 mmu_set_tc(uae_u16 tc);
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extern void REGPARAM2 mmu_set_super(bool super);
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#else
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static inline void mmu_reset(void)
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{
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}
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static inline void mmu_set_tc(uae_u16 /*tc*/)
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{
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}
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static inline void mmu_set_super(bool /*super*/)
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{
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}
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#endif
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#endif /* CPUMMU_H */
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/*
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vim:ts=4:sw=4:
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*/
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