minivmac4ios/Mini vMac/mnvm_core/PMUEMDEV.c

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/* PMUEMDEV.c Copyright (C) 2008 Paul C. Pratt You can redistribute this file and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. You should have received a copy of the license along with this file; see the file COPYING. This file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the license for more details. */ /* Power Management Unit EMulated DEVice */ #ifndef AllFiles #include "SYSDEPNS.h" #include "MYOSGLUE.h" #include "EMCONFIG.h" #include "GLOBGLUE.h" #include "VIAEMDEV.h" #endif #include "PMUEMDEV.h" /* ReportAbnormalID unused 0x0E0E - 0x0EFF */ enum { kPMUStateReadyForCommand, kPMUStateRecievingLength, kPMUStateRecievingBuffer, kPMUStateRecievedCommand, kPMUStateSendLength, kPMUStateSendBuffer, kPMUStates }; #define PMU_BuffSz 8 LOCALVAR ui3b PMU_BuffA[PMU_BuffSz]; LOCALVAR ui3p PMU_p; LOCALVAR ui3r PMU_rem; LOCALVAR ui3r PMU_i; LOCALVAR int PMUState = kPMUStateReadyForCommand; LOCALVAR ui3r PMU_CurCommand; LOCALVAR ui3r PMU_SendNext; LOCALVAR ui3r PMU_BuffL; LOCALPROC PmuStartSendResult(ui3r ResultCode, ui3r L) { PMU_SendNext = ResultCode; PMU_BuffL = L; PMUState = kPMUStateSendLength; } LOCALVAR ui3b PARAMRAM[128]; LOCALPROC PmuCheckCommandOp(void) { switch (PMU_CurCommand) { case 0x10: /* kPMUpowerCntl - power plane/clock control */ break; case 0x32: /* kPMUxPramWrite - write extended PRAM byte(s) */ if (kPMUStateRecievingBuffer == PMUState) { if (0 == PMU_i) { if (PMU_BuffL >= 2) { PMU_p = PMU_BuffA; PMU_rem = 2; } else { ReportAbnormalID(0x0E01, "PMU_BuffL too small for kPMUxPramWrite"); } } else if (2 == PMU_i) { if ((PMU_BuffA[1] + 2 == PMU_BuffL) && (PMU_BuffA[0] + PMU_BuffA[1] <= 0x80)) { PMU_p = &PARAMRAM[PMU_BuffA[0]]; PMU_rem = PMU_BuffA[1]; } else { ReportAbnormalID(0x0E02, "bad range for kPMUxPramWrite"); } } else { ReportAbnormalID(0x0E03, "Wrong PMU_i for kPMUpramWrite"); } } else if (kPMUStateRecievedCommand == PMUState) { /* already done */ } break; #if 0 case 0xE2: /* kPMUdownloadStatus - PRAM status */ break; #endif case 0xE0: /* kPMUwritePmgrRAM - write to internal PMGR RAM */ break; case 0x21: /* kPMUpMgrADBoff - turn ADB auto-poll off */ if (kPMUStateRecievedCommand == PMUState) { if (0 != PMU_BuffL) { ReportAbnormalID(0x0E04, "kPMUpMgrADBoff nonzero length"); } } break; case 0xEC: /* kPMUPmgrSelfTest - run the PMGR selftest */ if (kPMUStateRecievedCommand == PMUState) { PmuStartSendResult(0, 0); } break; case 0x78: /* kPMUreadINT - get PMGR interrupt data */ case 0x68: /* kPMUbatteryRead - read battery/charger level and status */ case 0x7F: /* kPMUsleepReq - put the system to sleep (sleepSig='MATT') */ if (kPMUStateRecievedCommand == PMUState) { PMU_BuffA[0] = 0; PmuStartSendResult(0, 1); } break; case 0xE8: /* kPMUreadPmgrRAM - read from internal PMGR RAM */ if (kPMUStateRecievedCommand == PMUState) { if ((3 == PMU_BuffL) && (0 == PMU_BuffA[0]) && (0xEE == PMU_BuffA[1]) && (1 == PMU_BuffA[2])) { PMU_BuffA[0] = 1 << 5; PmuStartSendResult(0, 1); } else { PMU_BuffA[0] = 0; PmuStartSendResult(0, 1); /* ReportAbnormal("Unknown kPMUreadPmgrRAM op"); */ } } break; case 0x3A: /* kPMUxPramRead - read extended PRAM byte(s) */ if (kPMUStateRecievedCommand == PMUState) { if ((2 == PMU_BuffL) && (PMU_BuffA[0] + PMU_BuffA[1] <= 0x80)) { PMU_p = &PARAMRAM[PMU_BuffA[0]]; PMU_rem = PMU_BuffA[1]; PmuStartSendResult(0, PMU_rem); } else { ReportAbnormalID(0x0E05, "Unknown kPMUxPramRead op"); } } break; case 0x38: /* kPMUtimeRead - read the time from the clock chip */ if (kPMUStateRecievedCommand == PMUState)