2021-09-30 06:21:11 +00:00
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2023-04-24 01:49:40 +00:00
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use moa_core::{System, Error, ClockTime, ClockDuration, Frequency, Address, Steppable, Addressable, Transmutable, debug};
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2022-09-25 06:14:03 +00:00
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use moa_core::host::Tty;
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2021-09-30 06:21:11 +00:00
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const REG_MR1A_MR2A: Address = 0x01;
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const REG_SRA_RD: Address = 0x03;
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const REG_CSRA_WR: Address = 0x03;
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const REG_CRA_WR: Address = 0x05;
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const REG_TBA_WR: Address = 0x07;
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const REG_RBA_RD: Address = 0x07;
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2021-10-08 17:52:15 +00:00
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2021-10-10 00:35:23 +00:00
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const REG_MR1B_MR2B: Address = 0x11;
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const REG_SRB_RD: Address = 0x13;
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const REG_CSRB_WR: Address = 0x13;
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const REG_CRB_WR: Address = 0x15;
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const REG_TBB_WR: Address = 0x17;
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const REG_RBB_RD: Address = 0x17;
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2021-10-08 17:52:15 +00:00
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2021-09-30 06:21:11 +00:00
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const REG_ACR_WR: Address = 0x09;
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const REG_CTUR_WR: Address = 0x0D;
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const REG_CTLR_WR: Address = 0x0F;
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const REG_START_RD: Address = 0x1D;
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const REG_STOP_RD: Address = 0x1F;
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const REG_IPCR_RD: Address = 0x09;
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const REG_OPCR_WR: Address = 0x1B;
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const REG_INPUT_RD: Address = 0x1B;
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const REG_OUT_SET: Address = 0x1D;
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const REG_OUT_RESET: Address = 0x1F;
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const REG_ISR_RD: Address = 0x0B;
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const REG_IMR_WR: Address = 0x0B;
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const REG_IVR_WR: Address = 0x19;
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2021-10-01 19:25:23 +00:00
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// Status Register Bits (SRA/SRB)
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_RECEIVED_BREAK: u8 = 0x80;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_FRAMING_ERROR: u8 = 0x40;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_PARITY_ERROR: u8 = 0x20;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_OVERRUN_ERROR: u8 = 0x10;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_TX_EMPTY: u8 = 0x08;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_TX_READY: u8 = 0x04;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_RX_FULL: u8 = 0x02;
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2021-10-11 22:16:04 +00:00
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#[allow(dead_code)]
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2021-10-01 19:25:23 +00:00
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const SR_RX_READY: u8 = 0x01;
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2021-10-07 20:57:50 +00:00
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// Interrupt Status/Mask Bits (ISR/IVR)
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2021-12-13 20:00:24 +00:00
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//const ISR_INPUT_CHANGE: u8 = 0x80;
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//const ISR_CH_B_BREAK_CHANGE: u8 = 0x40;
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2021-10-07 20:57:50 +00:00
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const ISR_CH_B_RX_READY_FULL: u8 = 0x20;
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const ISR_CH_B_TX_READY: u8 = 0x10;
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const ISR_TIMER_CHANGE: u8 = 0x08;
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2021-12-13 20:00:24 +00:00
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//const ISR_CH_A_BREAK_CHANGE: u8 = 0x04;
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2021-10-07 20:57:50 +00:00
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const ISR_CH_A_RX_READY_FULL: u8 = 0x02;
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const ISR_CH_A_TX_READY: u8 = 0x01;
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2023-03-06 04:19:49 +00:00
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const DEV_NAME: &str = "mc68681";
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2021-09-30 06:21:11 +00:00
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2023-03-06 04:19:49 +00:00
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#[derive(Default)]
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2021-10-10 00:35:23 +00:00
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pub struct MC68681Port {
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2021-12-13 20:00:24 +00:00
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tty: Option<Box<dyn Tty>>,
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status: u8,
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2021-10-15 05:04:14 +00:00
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2021-12-13 20:00:24 +00:00
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tx_enabled: bool,
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2021-10-15 05:04:14 +00:00
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2021-12-13 20:00:24 +00:00
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rx_enabled: bool,
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input: u8,
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2021-10-10 00:35:23 +00:00
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}
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impl MC68681Port {
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2021-10-23 02:36:05 +00:00
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pub fn connect(&mut self, pty: Box<dyn Tty>) -> Result<String, Error> {
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let name = pty.device_name();
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2021-10-10 00:35:23 +00:00
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println!("{}: opening pts {}", DEV_NAME, name);
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2021-10-16 23:11:50 +00:00
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self.tty = Some(pty);
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2021-10-10 00:35:23 +00:00
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Ok(name)
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}
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2021-10-15 05:04:14 +00:00
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pub fn send_byte(&mut self, data: u8) {
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2021-10-23 02:36:05 +00:00
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self.tty.as_mut().map(|tty| tty.write(data));
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2021-10-15 05:04:14 +00:00
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self.set_tx_status(false);
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}
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pub fn set_tx_status(&mut self, value: bool) {
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match value {
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true => { self.status |= SR_TX_READY | SR_TX_EMPTY; },
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false => { self.status &= !(SR_TX_READY | SR_TX_EMPTY); },
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}
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2021-10-10 00:35:23 +00:00
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}
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2021-10-15 05:04:14 +00:00
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pub fn set_rx_status(&mut self, value: bool) {
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match value {
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true => { self.status |= SR_RX_READY; },
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false => { self.status &= !SR_RX_READY; },
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}
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}
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pub fn check_rx(&mut self) -> Result<bool, Error> {
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if self.rx_enabled && (self.status & SR_RX_READY) == 0 && self.tty.is_some() {
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2021-10-10 00:35:23 +00:00
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let tty = self.tty.as_mut().unwrap();
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2021-10-23 02:36:05 +00:00
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let result = tty.read();
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2023-03-06 04:34:30 +00:00
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if let Some(input) = result {
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self.input = input;
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self.set_rx_status(true);
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return Ok(true);
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2021-10-10 00:35:23 +00:00
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}
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}
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Ok(false)
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}
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2021-10-15 05:04:14 +00:00
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pub fn check_tx(&mut self) -> bool {
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self.set_tx_status(self.tx_enabled);
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self.tx_enabled
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}
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2021-10-10 00:35:23 +00:00
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pub fn handle_command(&mut self, data: u8) -> Option<bool> {
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let rx_cmd = data& 0x03;
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if rx_cmd == 0b01 {
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self.rx_enabled = true;
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} else if rx_cmd == 0b10 {
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self.rx_enabled = false;
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}
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let tx_cmd = (data & 0x0C) >> 2;
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if tx_cmd == 0b01 {
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self.tx_enabled = true;
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2021-10-15 05:04:14 +00:00
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self.set_tx_status(true);
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2021-10-10 00:35:23 +00:00
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return Some(true);
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} else if tx_cmd == 0b10 {
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self.tx_enabled = false;
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2021-10-15 05:04:14 +00:00
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self.set_tx_status(false);
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2021-10-10 00:35:23 +00:00
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return Some(false);
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}
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None
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}
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}
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pub struct MC68681 {
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2023-04-23 22:46:47 +00:00
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frequency: Frequency,
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2021-12-13 20:00:24 +00:00
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acr: u8,
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2021-10-10 00:35:23 +00:00
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pub port_a: MC68681Port,
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pub port_b: MC68681Port,
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2021-12-13 20:00:24 +00:00
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int_mask: u8,
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int_status: u8,
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int_vector: u8,
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2021-10-10 00:35:23 +00:00
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2021-12-13 20:00:24 +00:00
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timer_preload: u16,
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timer_count: u16,
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is_timing: bool,
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timer_divider: u16,
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2021-10-11 22:16:04 +00:00
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2021-12-13 20:00:24 +00:00
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input_pin_change: u8,
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input_state: u8,
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output_conf: u8,
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output_state: u8,
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2021-09-30 06:21:11 +00:00
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}
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2023-03-06 04:19:49 +00:00
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impl Default for MC68681 {
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fn default() -> Self {
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2021-09-30 06:21:11 +00:00
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MC68681 {
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2023-04-23 22:46:47 +00:00
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frequency: Frequency::from_hz(3_686_400),
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2021-10-08 17:52:15 +00:00
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acr: 0,
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2023-03-06 04:19:49 +00:00
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port_a: MC68681Port::default(),
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port_b: MC68681Port::default(),
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2021-10-08 17:52:15 +00:00
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2021-10-07 20:57:50 +00:00
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int_mask: 0,
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int_status: 0,
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2021-10-07 18:35:15 +00:00
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int_vector: 0,
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2021-10-08 17:52:15 +00:00
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timer_preload: 0,
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timer_count: 0,
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is_timing: true,
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2021-10-15 05:04:14 +00:00
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timer_divider: 0,
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2021-10-11 22:16:04 +00:00
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input_pin_change: 0,
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input_state: 0,
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output_conf: 0,
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output_state: 0,
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2021-09-30 06:21:11 +00:00
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}
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}
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2023-03-06 04:19:49 +00:00
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}
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2021-10-01 19:25:23 +00:00
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2023-03-06 04:19:49 +00:00
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impl MC68681 {
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2021-10-24 05:22:02 +00:00
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fn set_interrupt_flag(&mut self, flag: u8, value: bool) {
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self.int_status = (self.int_status & !flag) | (if value { flag } else { 0 });
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}
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fn check_interrupt_state(&mut self, system: &System) -> Result<(), Error> {
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system.get_interrupt_controller().set((self.int_status & self.int_mask) != 0, 4, self.int_vector)
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}
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}
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impl Steppable for MC68681 {
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2023-04-23 22:46:47 +00:00
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fn step(&mut self, system: &System) -> Result<ClockDuration, Error> {
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2021-10-15 05:04:14 +00:00
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if self.port_a.check_rx()? {
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self.set_interrupt_flag(ISR_CH_A_RX_READY_FULL, true);
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2021-10-01 19:25:23 +00:00
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}
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2021-10-09 18:00:32 +00:00
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2021-10-15 05:04:14 +00:00
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if self.port_b.check_rx()? {
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self.set_interrupt_flag(ISR_CH_B_RX_READY_FULL, true);
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2021-10-01 19:25:23 +00:00
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}
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2021-10-08 17:52:15 +00:00
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if self.is_timing {
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2021-10-15 05:04:14 +00:00
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self.timer_divider = self.timer_divider.wrapping_sub(1);
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if self.timer_divider == 0 {
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self.timer_divider = 1;
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self.timer_count = self.timer_count.wrapping_sub(1);
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if self.timer_count == 0 {
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self.set_interrupt_flag(ISR_TIMER_CHANGE, true);
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if (self.acr & 0x40) == 0 {
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self.is_timing = false;
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} else {
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self.timer_count = self.timer_preload;
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}
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2021-10-08 17:52:15 +00:00
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}
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}
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2021-10-07 20:57:50 +00:00
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}
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2021-10-08 17:52:15 +00:00
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self.check_interrupt_state(system)?;
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2021-10-15 05:04:14 +00:00
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if self.port_a.check_tx() {
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self.set_interrupt_flag(ISR_CH_A_TX_READY, true);
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}
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if self.port_b.check_tx() {
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self.set_interrupt_flag(ISR_CH_B_TX_READY, true);
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}
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2023-04-23 22:46:47 +00:00
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Ok(self.frequency.period_duration())
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2021-10-01 19:25:23 +00:00
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}
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2021-09-30 06:21:11 +00:00
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}
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impl Addressable for MC68681 {
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2023-06-08 02:56:00 +00:00
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fn size(&self) -> usize {
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2021-09-30 06:21:11 +00:00
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0x30
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}
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2023-04-24 01:49:40 +00:00
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fn read(&mut self, _clock: ClockTime, addr: Address, data: &mut [u8]) -> Result<(), Error> {
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2021-09-30 06:21:11 +00:00
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match addr {
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2021-10-02 00:53:55 +00:00
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REG_SRA_RD => {
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2021-10-10 00:35:23 +00:00
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data[0] = self.port_a.status
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2021-10-01 19:25:23 +00:00
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},
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REG_RBA_RD => {
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2021-10-10 00:35:23 +00:00
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data[0] = self.port_a.input;
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2021-10-15 05:04:14 +00:00
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self.port_a.set_rx_status(false);
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self.set_interrupt_flag(ISR_CH_A_RX_READY_FULL, false);
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2021-10-08 17:52:15 +00:00
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},
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REG_SRB_RD => {
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2021-10-10 00:35:23 +00:00
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data[0] = self.port_b.status
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2021-10-08 17:52:15 +00:00
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},
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REG_RBB_RD => {
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2021-10-10 00:35:23 +00:00
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data[0] = self.port_b.input;
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2021-10-15 05:04:14 +00:00
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self.port_b.set_rx_status(false);
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self.set_interrupt_flag(ISR_CH_B_RX_READY_FULL, false);
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2021-10-01 19:25:23 +00:00
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},
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2021-10-07 20:57:50 +00:00
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REG_ISR_RD => {
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data[0] = self.int_status;
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},
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2021-10-11 22:16:04 +00:00
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REG_IPCR_RD => {
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data[0] = self.input_pin_change;
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},
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REG_INPUT_RD => {
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data[0] = self.input_state;
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},
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2021-10-08 17:52:15 +00:00
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REG_START_RD => {
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self.timer_count = self.timer_preload;
|
|
|
|
self.is_timing = true;
|
|
|
|
},
|
|
|
|
REG_STOP_RD => {
|
|
|
|
if (self.acr & 0x40) == 0 {
|
|
|
|
// Counter Mode
|
|
|
|
self.is_timing = false;
|
|
|
|
self.timer_count = self.timer_preload;
|
|
|
|
} else {
|
|
|
|
// Timer Mode
|
|
|
|
// Do nothing except reset the ISR bit
|
|
|
|
}
|
2021-10-15 05:04:14 +00:00
|
|
|
self.set_interrupt_flag(ISR_TIMER_CHANGE, false);
|
2021-10-08 17:52:15 +00:00
|
|
|
},
|
|
|
|
_ => { },
|
2021-10-01 19:25:23 +00:00
|
|
|
}
|
2021-10-02 00:53:55 +00:00
|
|
|
|
2021-10-15 21:37:31 +00:00
|
|
|
if addr != REG_SRA_RD && addr != REG_SRB_RD {
|
|
|
|
debug!("{}: read from {:0x} of {:0x}", DEV_NAME, addr, data[0]);
|
|
|
|
}
|
|
|
|
|
2021-10-27 00:33:23 +00:00
|
|
|
Ok(())
|
2021-10-01 19:25:23 +00:00
|
|
|
}
|
|
|
|
|
2023-04-24 01:49:40 +00:00
|
|
|
fn write(&mut self, _clock: ClockTime, addr: Address, data: &[u8]) -> Result<(), Error> {
|
2021-10-15 05:04:14 +00:00
|
|
|
debug!("{}: writing {:0x} to {:0x}", DEV_NAME, data[0], addr);
|
2021-10-01 19:25:23 +00:00
|
|
|
match addr {
|
2021-10-11 22:16:04 +00:00
|
|
|
REG_MR1A_MR2A | REG_MR1B_MR2B | REG_CSRA_WR | REG_CSRB_WR => {
|
|
|
|
// NOTE we aren't simulating the serial speeds, so we aren't doing anything with these settings atm
|
|
|
|
},
|
2021-10-08 17:52:15 +00:00
|
|
|
REG_ACR_WR => {
|
|
|
|
self.acr = data[0];
|
|
|
|
}
|
2021-10-01 19:25:23 +00:00
|
|
|
REG_TBA_WR => {
|
2021-10-15 05:04:14 +00:00
|
|
|
debug!("{}a: write {}", DEV_NAME, data[0] as char);
|
|
|
|
self.port_a.send_byte(data[0]);
|
|
|
|
self.set_interrupt_flag(ISR_CH_A_TX_READY, false);
|
2021-10-01 19:25:23 +00:00
|
|
|
},
|
2021-10-08 17:52:15 +00:00
|
|
|
REG_CRA_WR => {
|
2023-03-06 04:34:30 +00:00
|
|
|
if let Some(value) = self.port_a.handle_command(data[0]) {
|
|
|
|
self.set_interrupt_flag(ISR_CH_A_TX_READY, value);
|
2021-10-08 17:52:15 +00:00
|
|
|
}
|
|
|
|
},
|
|
|
|
REG_TBB_WR => {
|
2021-10-15 05:04:14 +00:00
|
|
|
debug!("{}b: write {:x}", DEV_NAME, data[0]);
|
|
|
|
self.port_b.send_byte(data[0]);
|
|
|
|
self.set_interrupt_flag(ISR_CH_B_TX_READY, false);
|
2021-10-08 17:52:15 +00:00
|
|
|
},
|
|
|
|
REG_CRB_WR => {
|
2023-03-06 04:34:30 +00:00
|
|
|
if let Some(value) = self.port_b.handle_command(data[0]) {
|
|
|
|
self.set_interrupt_flag(ISR_CH_B_TX_READY, value);
|
2021-10-08 17:52:15 +00:00
|
|
|
}
|
|
|
|
},
|
2021-10-07 18:35:15 +00:00
|
|
|
REG_CTUR_WR => {
|
2021-10-08 17:52:15 +00:00
|
|
|
self.timer_preload = (self.timer_preload & 0x00FF) | ((data[0] as u16) << 8);
|
2021-10-07 18:35:15 +00:00
|
|
|
},
|
|
|
|
REG_CTLR_WR => {
|
2021-10-08 17:52:15 +00:00
|
|
|
self.timer_preload = (self.timer_preload & 0xFF00) | (data[0] as u16);
|
2021-10-07 18:35:15 +00:00
|
|
|
},
|
2021-10-07 20:57:50 +00:00
|
|
|
REG_IMR_WR => {
|
|
|
|
self.int_mask = data[0];
|
|
|
|
},
|
2021-10-07 18:35:15 +00:00
|
|
|
REG_IVR_WR => {
|
|
|
|
self.int_vector = data[0];
|
|
|
|
},
|
2021-10-11 22:16:04 +00:00
|
|
|
REG_OPCR_WR => {
|
|
|
|
self.output_conf = data[0];
|
|
|
|
},
|
|
|
|
REG_OUT_SET => {
|
|
|
|
self.output_state |= data[0];
|
|
|
|
},
|
|
|
|
REG_OUT_RESET => {
|
|
|
|
self.output_state &= !data[0];
|
|
|
|
},
|
2021-10-08 17:52:15 +00:00
|
|
|
_ => { },
|
2021-10-01 19:25:23 +00:00
|
|
|
}
|
2021-10-06 02:58:22 +00:00
|
|
|
Ok(())
|
2021-10-01 19:25:23 +00:00
|
|
|
}
|
|
|
|
}
|
2021-10-02 00:53:55 +00:00
|
|
|
|
2021-10-17 17:39:43 +00:00
|
|
|
impl Transmutable for MC68681 {
|
|
|
|
fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
|
|
|
|
Some(self)
|
|
|
|
}
|
|
|
|
|
|
|
|
fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
|
|
|
|
Some(self)
|
|
|
|
}
|
|
|
|
}
|