2021-10-03 16:55:20 +00:00
|
|
|
|
2021-10-16 17:01:14 +00:00
|
|
|
* make IO in mc68681 use a separate thread... will that improve performance of mc68681.step()?
|
2021-10-15 04:16:31 +00:00
|
|
|
|
2021-10-16 17:01:14 +00:00
|
|
|
* make it possible to break out of the current execution, into the debugger, by using a certain keystroke
|
|
|
|
|
* add support for MC68020+ indexing modes
|
|
|
|
|
* add support for MMU
|
|
|
|
|
* add support for FPU
|
2021-10-10 21:26:54 +00:00
|
|
|
* make tests for each instruction
|
|
|
|
|
|
2021-10-11 03:47:51 +00:00
|
|
|
* unimplemented: ABCD, ADDX, BKPT, CHK, EXG, ILLEGAL, MOVEfromCCR, MOVEP, RTR, RTD, SBCD, SUBX
|
|
|
|
|
* undecoded: ADDX, SUBX
|
2021-10-16 17:01:14 +00:00
|
|
|
* modify execution for >=MC68020: DIVSL, DIVUL, LINK, MOVEM, MULSL, MULUL, RTM, TRAPcc, UNPK
|
2021-10-10 21:26:54 +00:00
|
|
|
* implement the full extension word for MC68020+
|
|
|
|
|
|
|
|
|
|
* >=MC68020 instructions: BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CALLM, CAS, CAS2, CHK2, CMP2, PACK
|
|
|
|
|
* Coprocessor instructions: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* should you simulate clock ticks, and only step devices when they next request it
|
2021-10-10 03:35:52 +00:00
|
|
|
* how can you have multple CPUs
|
2021-10-07 16:41:01 +00:00
|
|
|
* should you simulate bus arbitration?
|
2021-10-03 16:55:20 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
* check all instructions in the docs
|
|
|
|
|
|
|
|
|
|
|
