2023-03-26 04:27:02 +00:00
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2024-02-24 21:02:09 +00:00
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use femtos::{Instant, Frequency};
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use moa_core::{System, Error, MemoryBlock, BusPort, Address, Addressable, Device};
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2023-03-26 04:27:02 +00:00
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use moa_m68k::{M68k, M68kType};
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use moa_m68k::instructions::{Instruction, Target, Size};
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use moa_m68k::timing::M68kInstructionTiming;
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2024-03-03 21:26:15 +00:00
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use moa_m68k::execute::M68kCycle;
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2023-03-26 04:27:02 +00:00
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const INIT_STACK: Address = 0x00002000;
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const INIT_ADDR: Address = 0x00000010;
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struct TimingCase {
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cpu: M68kType,
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data: &'static [u16],
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timing: (u16, u16, u16),
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ins: Instruction,
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}
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const TIMING_TESTS: &'static [TimingCase] = &[
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TimingCase { cpu: M68kType::MC68000, data: &[0xD090], timing: ( 14, 14, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) },
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];
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2024-03-03 21:26:15 +00:00
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fn init_decode_test(cputype: M68kType) -> (M68k, M68kCycle, System) {
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2023-03-26 04:27:02 +00:00
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let mut system = System::default();
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// Insert basic initialization
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let data = vec![0; 0x00100000];
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let mem = MemoryBlock::new(data);
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2023-06-11 00:39:20 +00:00
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system.add_addressable_device(0x00000000, Device::new(mem)).unwrap();
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2024-02-24 21:02:09 +00:00
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system.get_bus().write_beu32(Instant::START, 0, INIT_STACK as u32).unwrap();
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system.get_bus().write_beu32(Instant::START, 4, INIT_ADDR as u32).unwrap();
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2023-03-26 04:27:02 +00:00
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// Initialize the CPU and make sure it's in the expected state
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2024-03-03 21:26:15 +00:00
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let cpu = M68k::from_type(cputype, Frequency::from_mhz(10), system.bus.clone(), 0);
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//cpu.reset_cpu().unwrap();
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2023-03-26 04:27:02 +00:00
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assert_eq!(cpu.state.pc, INIT_ADDR as u32);
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assert_eq!(cpu.state.ssp, INIT_STACK as u32);
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2024-03-03 21:26:15 +00:00
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let cycle = M68kCycle::new(&cpu, system.clock);
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assert_eq!(cycle.decoder.start, INIT_ADDR as u32);
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assert_eq!(cycle.decoder.instruction, Instruction::NOP);
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(cpu, cycle, system)
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2023-03-26 04:27:02 +00:00
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}
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fn load_memory(system: &System, data: &[u16]) {
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let mut addr = INIT_ADDR;
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for word in data {
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2023-05-08 03:42:55 +00:00
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system.get_bus().write_beu16(system.clock, addr, *word).unwrap();
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2023-03-26 04:27:02 +00:00
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addr += 2;
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}
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}
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fn run_timing_test(case: &TimingCase) -> Result<(), Error> {
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2024-03-03 21:26:15 +00:00
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let (mut cpu, cycle, system) = init_decode_test(case.cpu);
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let mut executor = cycle.begin(&mut cpu);
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2023-03-26 04:27:02 +00:00
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let mut timing = M68kInstructionTiming::new(case.cpu, 16);
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load_memory(&system, case.data);
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2024-03-03 21:26:15 +00:00
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executor.decode_next().unwrap();
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assert_eq!(executor.cycle.decoder.instruction, case.ins.clone());
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2023-03-26 04:27:02 +00:00
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2024-03-03 21:26:15 +00:00
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timing.add_instruction(&executor.cycle.decoder.instruction);
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2023-03-26 04:27:02 +00:00
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let result = timing.calculate_clocks(false, 1);
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let expected = match case.cpu {
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M68kType::MC68000 => case.timing.0,
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M68kType::MC68010 => case.timing.1,
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_ => case.timing.2,
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};
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//assert_eq!(expected, result);
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if expected == result {
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Ok(())
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} else {
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println!("{:?}", timing);
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2023-06-11 00:39:20 +00:00
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Err(Error::new(format!("expected {} but found {}", expected, result)))
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2023-03-26 04:27:02 +00:00
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}
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}
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#[test]
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pub fn run_timing_tests() {
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let mut errors = 0;
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for case in TIMING_TESTS {
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// NOTE switched to only show the failures rather than all tests
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//print!("Testing for {:?}...", case.ins);
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//match run_timing_test(case) {
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// Ok(()) => println!("ok"),
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// Err(err) => { println!("{}", err.msg); errors += 1 },
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//}
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if let Err(_) = run_timing_test(case) {
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errors += 1;
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}
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}
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if errors > 0 {
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panic!("{} errors", errors);
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}
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}
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