moa/emulator/cpus/m68k/src/lib.rs


pub mod assembler;
pub mod state;
pub mod decode;
pub mod execute;
pub mod debugger;
pub mod instructions;
pub mod memory;
pub mod timing;
pub mod tests;

#[cfg(feature = "moa")]
pub mod moa;

pub use crate::state::{M68k, M68kType, M68kError};
pub use crate::memory::{M68kAddress, M68kAddressSpace};
Reorganized and started working on the execution code 2021-09-30 00:11:48 +00:00
Added an assembler for the m68k It can encode some basic instructions but not the more complicated addressing modes or special instructions. It can keep track of labels and patch the displacement addresses after assembling the output data, but it doesn't check for duplicates or that a label has been declared before it appears. It also doesn't take into account the origin yet. To run it, there is an m68kas command that will take a file and print the data: ``` cargo run -p moa --bin m68kas <filename> ``` It's not yet tied into the rest of the system, but could be used in the debugger to allow insertion of new code into a running system. 2022-05-13 04:53:34 +00:00			`pub mod assembler;`
Added cpu to system, and refactored m68k a bit 2021-10-07 18:35:15 +00:00			`pub mod state;`
Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition flags should not be changed, but the code was changing them, which caused problems. I've fixed it by making the ADD/SUB executions check for an address target and will not update flags in that case. This should only occur when the actual instruction was an ADDA or ADDQ with an address register target 2021-10-03 04:59:28 +00:00			`pub mod decode;`
			`pub mod execute;`
			`pub mod debugger;`
Moved m68k instruction types to their own file 2021-10-18 19:05:10 +00:00			`pub mod instructions;`
Refactored memory access a bit to try to isolate it 2023-05-22 06:14:26 +00:00			`pub mod memory;`
Added timing to m68k implementation 2021-12-15 05:13:01 +00:00			`pub mod timing;`
Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition flags should not be changed, but the code was changing them, which caused problems. I've fixed it by making the ADD/SUB executions check for an address target and will not update flags in that case. This should only occur when the actual instruction was an ADDA or ADDQ with an address register target 2021-10-03 04:59:28 +00:00			`pub mod tests;`
Reorganized and started working on the execution code 2021-09-30 00:11:48 +00:00
Separated moa-core dependency into an optional feature flag 2024-03-14 04:49:04 +00:00			`#[cfg(feature = "moa")]`
			`pub mod moa;`

Fixed some tests 2024-03-16 06:01:41 +00:00			`pub use crate::state::{M68k, M68kType, M68kError};`
			`pub use crate::memory::{M68kAddress, M68kAddressSpace};`
Reorganized and started working on the execution code 2021-09-30 00:11:48 +00:00