2021-09-30 00:11:48 +00:00
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use crate::error::Error;
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use crate::memory::{Address, AddressSpace};
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2021-09-30 04:52:38 +00:00
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use super::decode::{Instruction, Target, Size, Direction, Condition, ControlRegister, RegisterType};
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2021-09-30 00:11:48 +00:00
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pub trait Processor {
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fn reset();
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fn step();
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum State {
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Init,
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Running,
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Halted,
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}
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pub struct MC68010 {
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pub state: State,
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pub pc: u32,
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pub sr: u16,
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pub d_reg: [u32; 8],
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pub a_reg: [u32; 7],
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pub msp: u32,
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pub usp: u32,
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pub vbr: u32,
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pub current_instruction_addr: u32,
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pub current_instruction: Instruction,
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2021-09-30 00:11:48 +00:00
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}
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const FLAGS_ON_RESET: u16 = 0x2700;
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2021-09-30 04:52:38 +00:00
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pub const FLAGS_CARRY: u16 = 0x0001;
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pub const FLAGS_OVERFLOW: u16 = 0x0002;
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pub const FLAGS_ZERO: u16 = 0x0004;
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pub const FLAGS_NEGATIVE: u16 = 0x0008;
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pub const FLAGS_SUPERVISOR: u16 = 0x2000;
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pub const ERR_BUS_ERROR: u32 = 2;
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pub const ERR_ADDRESS_ERROR: u32 = 3;
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pub const ERR_ILLEGAL_INSTRUCTION: u32 = 4;
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impl MC68010 {
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pub fn new() -> MC68010 {
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MC68010 {
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state: State::Init,
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pc: 0,
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sr: FLAGS_ON_RESET,
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d_reg: [0; 8],
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a_reg: [0; 7],
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msp: 0,
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usp: 0,
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vbr: 0,
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2021-09-30 19:58:11 +00:00
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current_instruction_addr: 0,
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current_instruction: Instruction::NOP,
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2021-09-30 00:11:48 +00:00
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}
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}
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pub fn reset(&mut self) {
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self.state = State::Init;
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self.pc = 0;
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self.sr = FLAGS_ON_RESET;
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self.d_reg = [0; 8];
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self.a_reg = [0; 7];
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self.msp = 0;
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self.usp = 0;
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self.vbr = 0;
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self.current_instruction_addr = 0;
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self.current_instruction = Instruction::NOP;
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2021-09-30 00:11:48 +00:00
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}
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pub fn is_running(&self) -> bool {
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self.state != State::Halted
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}
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pub fn init(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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println!("Initializing CPU");
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self.msp = space.read_beu32(0)?;
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self.pc = space.read_beu32(4)?;
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self.state = State::Running;
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Ok(())
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}
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pub fn step(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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match self.state {
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State::Init => self.init(space),
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State::Halted => Err(Error::new("CPU halted")),
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State::Running => {
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self.decode_next(space)?;
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self.execute_current(space)?;
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Ok(())
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},
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}
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}
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2021-09-30 19:58:11 +00:00
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pub fn dump_state(&self, space: &AddressSpace) {
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println!("State: {:?}", self.state);
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println!("PC: {:#010x}", self.pc);
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println!("SR: {:#06x}", self.sr);
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for i in 0..7 {
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println!("D{}: {:#010x} A{}: {:#010x}", i, self.d_reg[i as usize], i, self.a_reg[i as usize]);
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}
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println!("D7: {:#010x}", self.d_reg[7]);
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println!("MSP: {:#010x}", self.msp);
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println!("USP: {:#010x}", self.usp);
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println!("Current Instruction: {:#010x} {:?}", self.current_instruction_addr, self.current_instruction);
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println!("");
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space.dump_memory(self.msp as Address, 0x40);
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println!("");
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}
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2021-09-30 00:11:48 +00:00
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fn is_supervisor(&self) -> bool {
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self.sr & FLAGS_SUPERVISOR != 0
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}
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fn push_long(&mut self, space: &mut AddressSpace, value: u32) -> Result<(), Error> {
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let reg = self.get_stack_pointer_mut();
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*reg -= 4;
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//println!("PUSHING {:08x} at {:08x}", value, *reg);
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space.write_beu32(*reg as Address, value)
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}
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2021-09-30 04:52:38 +00:00
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fn pop_long(&mut self, space: &mut AddressSpace) -> Result<u32, Error> {
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let reg = self.get_stack_pointer_mut();
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let value = space.read_beu32(*reg as Address)?;
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//println!("POPPING {:08x} at {:08x}", value, *reg);
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*reg += 4;
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Ok(value)
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}
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2021-09-30 19:58:11 +00:00
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fn decode_next(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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self.current_instruction_addr = self.pc;
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self.current_instruction = self.decode_one(space)?;
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2021-09-30 00:11:48 +00:00
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2021-09-30 19:58:11 +00:00
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/*
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// Print instruction bytes for debugging
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let ins_data: Result<String, Error> =
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(0..((self.pc - current_ins_addr) / 2)).map(|offset|
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Ok(format!("{:04x} ", space.read_beu16((current_ins_addr + (offset * 2)) as Address)?))
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).collect();
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debug!("{:#010x}: {}\n\t{:?}\n", current_ins_addr, ins_data?, ins);
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2021-09-30 06:21:11 +00:00
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// Single Step
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self.dump_state();
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let mut buffer = String::new();
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std::io::stdin().read_line(&mut buffer).unwrap();
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*/
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Ok(())
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}
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2021-09-30 06:21:11 +00:00
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2021-09-30 19:58:11 +00:00
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fn execute_current(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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match self.current_instruction {
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Instruction::ADD(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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let existing = self.get_target_value(space, dest, size)?;
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let (result, overflow) = match size {
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Size::Byte => {
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let (result, overflow) = (existing as u8).overflowing_add(value as u8);
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(result as u32, overflow)
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},
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Size::Word => {
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let (result, overflow) = (existing as u16).overflowing_add(value as u16);
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(result as u32, overflow)
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},
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Size::Long => existing.overflowing_add(value),
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};
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self.set_compare_flags(result as i32, overflow);
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self.set_target_value(space, dest, result, size)?;
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},
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Instruction::AND(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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let existing = self.get_target_value(space, dest, size)?;
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self.set_target_value(space, dest, existing & value, size)?;
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self.set_logic_flags(value, size);
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},
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Instruction::ANDtoCCR(value) => {
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self.sr = self.sr | value as u16;
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},
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Instruction::ANDtoSR(value) => {
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self.sr = self.sr | value;
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},
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//Instruction::ASd(Target, Target, Size, ShiftDirection) => {
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//},
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Instruction::Bcc(cond, offset) => {
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let should_branch = self.get_current_condition(cond);
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if should_branch {
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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}
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},
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Instruction::BRA(offset) => {
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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},
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Instruction::BSR(offset) => {
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self.push_long(space, self.pc)?;
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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},
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//Instruction::BTST(Target, Target, Size) => {
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//},
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//Instruction::BCHG(Target, Target, Size) => {
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//},
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//Instruction::BCLR(Target, Target, Size) => {
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//},
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//Instruction::BSET(Target, Target, Size) => {
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//},
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Instruction::CLR(target, size) => {
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self.set_target_value(space, target, 0, size)?;
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},
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Instruction::CMP(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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let existing = self.get_target_value(space, dest, size)?;
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let result = self.subtract_sized_with_flags(existing, value, size);
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},
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//Instruction::DBcc(Condition, u16) => {
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//},
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//Instruction::DIV(Target, Target, Size, Sign) => {
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//},
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//Instruction::EOR(Target, Target, Size) => {
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//},
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//Instruction::EORtoCCR(u8) => {
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//},
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//Instruction::EORtoSR(u16) => {
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//},
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//Instruction::EXG(Target, Target) => {
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//},
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//Instruction::EXT(u8, Size) => {
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//},
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//Instruction::ILLEGAL => {
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//},
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Instruction::JMP(target) => {
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self.pc = self.get_target_address(target)? - 2;
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},
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Instruction::JSR(target) => {
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self.push_long(space, self.pc)?;
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self.pc = self.get_target_address(target)? - 2;
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},
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Instruction::LEA(target, reg) => {
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let value = self.get_target_address(target)?;
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let addr = self.get_a_reg_mut(reg);
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*addr = value;
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},
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//Instruction::LINK(u8, u16) => {
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//},
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//Instruction::LSd(Target, Target, Size, ShiftDirection) => {
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//},
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Instruction::MOVE(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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self.set_target_value(space, dest, value, size)?;
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},
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Instruction::MOVEfromSR(target) => {
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self.set_target_value(space, target, self.sr as u32, Size::Word)?;
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},
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Instruction::MOVEtoSR(target) => {
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self.sr = self.get_target_value(space, target, Size::Word)? as u16;
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},
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//Instruction::MOVEtoCCR(Target) => {
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//},
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Instruction::MOVEC(target, control_reg, dir) => {
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match dir {
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Direction::FromTarget => {
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let value = self.get_target_value(space, target, Size::Long)?;
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let addr = self.get_control_reg_mut(control_reg);
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*addr = value;
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},
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Direction::ToTarget => {
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let addr = self.get_control_reg_mut(control_reg);
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let value = *addr;
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self.set_target_value(space, target, value, Size::Long)?;
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},
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}
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},
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//Instruction::MOVEUSP(Target, Direction) => {
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//},
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2021-09-30 19:58:11 +00:00
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Instruction::MOVEM(target, size, dir, mask) => {
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// TODO moving words requires a sign extension to 32 bits
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if size != Size::Long { panic!("Unsupported size in MOVEM instruction"); }
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if dir == Direction::ToTarget {
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let mut mask = mask;
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for i in 0..8 {
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if (mask & 0x01) != 0 {
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self.set_target_value(space, target, self.d_reg[i], size)?;
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}
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mask >>= 1;
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}
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for i in 0..8 {
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if (mask & 0x01) != 0 {
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let value = *self.get_a_reg_mut(i);
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self.set_target_value(space, target, value, size)?;
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}
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mask >>= 1;
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}
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} else {
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let mut mask = mask;
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for i in (0..8).rev() {
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if (mask & 0x01) != 0 {
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let value = *self.get_a_reg_mut(i);
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self.set_target_value(space, target, value, size)?;
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}
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mask >>= 1;
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}
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for i in (0..8).rev() {
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if (mask & 0x01) != 0 {
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self.set_target_value(space, target, self.d_reg[i], size)?;
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}
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mask >>= 1;
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}
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}
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},
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Instruction::MOVEQ(data, reg) => {
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let value = ((data as i8) as i32) as u32;
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self.d_reg[reg as usize] = value;
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},
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2021-09-30 00:11:48 +00:00
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|
|
//Instruction::MUL(Target, Target, Size, Sign) => {
|
|
|
|
//},
|
|
|
|
//Instruction::NBCD(Target) => {
|
|
|
|
//},
|
|
|
|
//Instruction::NEG(Target, Size) => {
|
|
|
|
//},
|
|
|
|
//Instruction::NEGX(Target, Size) => {
|
|
|
|
//},
|
|
|
|
Instruction::NOP => { },
|
2021-09-30 04:52:38 +00:00
|
|
|
//Instruction::NOT(target, size) => {
|
2021-09-30 00:11:48 +00:00
|
|
|
//},
|
2021-09-30 04:52:38 +00:00
|
|
|
Instruction::OR(src, dest, size) => {
|
|
|
|
let value = self.get_target_value(space, src, size)?;
|
|
|
|
let existing = self.get_target_value(space, dest, size)?;
|
|
|
|
self.set_target_value(space, dest, existing | value, size)?;
|
|
|
|
self.set_logic_flags(value, size);
|
|
|
|
},
|
|
|
|
Instruction::ORtoCCR(value) => {
|
|
|
|
self.sr = self.sr | value as u16;
|
|
|
|
},
|
2021-09-30 00:11:48 +00:00
|
|
|
Instruction::ORtoSR(value) => {
|
|
|
|
self.sr = self.sr | value;
|
|
|
|
},
|
2021-09-30 04:52:38 +00:00
|
|
|
Instruction::PEA(target) => {
|
|
|
|
let value = self.get_target_address(target)?;
|
|
|
|
self.push_long(space, value)?;
|
|
|
|
},
|
2021-09-30 00:11:48 +00:00
|
|
|
//Instruction::RESET => {
|
|
|
|
//},
|
|
|
|
//Instruction::ROd(Target, Target, Size, ShiftDirection) => {
|
|
|
|
//},
|
|
|
|
//Instruction::ROXd(Target, Target, Size, ShiftDirection) => {
|
|
|
|
//},
|
|
|
|
//Instruction::RTE => {
|
|
|
|
//},
|
|
|
|
//Instruction::RTR => {
|
|
|
|
//},
|
2021-09-30 04:52:38 +00:00
|
|
|
Instruction::RTS => {
|
|
|
|
self.pc = self.pop_long(space)?;
|
|
|
|
},
|
2021-09-30 00:11:48 +00:00
|
|
|
//Instruction::STOP(u16) => {
|
|
|
|
//},
|
2021-09-30 04:52:38 +00:00
|
|
|
Instruction::SUB(src, dest, size) => {
|
|
|
|
let value = self.get_target_value(space, src, size)?;
|
|
|
|
let existing = self.get_target_value(space, dest, size)?;
|
2021-09-30 19:58:11 +00:00
|
|
|
let result = self.subtract_sized_with_flags(existing, value, size);
|
2021-09-30 04:52:38 +00:00
|
|
|
self.set_target_value(space, dest, result, size)?;
|
|
|
|
},
|
2021-09-30 00:11:48 +00:00
|
|
|
//Instruction::SWAP(u8) => {
|
|
|
|
//},
|
|
|
|
//Instruction::TAS(Target) => {
|
|
|
|
//},
|
2021-09-30 04:52:38 +00:00
|
|
|
Instruction::TST(target, size) => {
|
|
|
|
let value = self.get_target_value(space, target, size)?;
|
|
|
|
self.set_compare_flags(value as i32, false);
|
|
|
|
},
|
2021-09-30 00:11:48 +00:00
|
|
|
//Instruction::TRAP(u8) => {
|
|
|
|
//},
|
|
|
|
//Instruction::TRAPV => {
|
|
|
|
//},
|
|
|
|
//Instruction::UNLK(u8) => {
|
|
|
|
//},
|
|
|
|
_ => { panic!(""); },
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_target_value(&mut self, space: &mut AddressSpace, target: Target, size: Size) -> Result<u32, Error> {
|
|
|
|
match target {
|
|
|
|
Target::Immediate(value) => Ok(value),
|
|
|
|
Target::DirectDReg(reg) => Ok(get_value_sized(self.d_reg[reg as usize], size)),
|
2021-09-30 04:52:38 +00:00
|
|
|
Target::DirectAReg(reg) => Ok(get_value_sized(*self.get_a_reg_mut(reg), size)),
|
|
|
|
Target::IndirectAReg(reg) => get_address_sized(space, *self.get_a_reg_mut(reg) as Address, size),
|
2021-09-30 00:11:48 +00:00
|
|
|
Target::IndirectARegInc(reg) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
|
|
|
let result = get_address_sized(space, *addr as Address, size);
|
2021-09-30 00:11:48 +00:00
|
|
|
*addr += size.in_bytes();
|
2021-09-30 04:52:38 +00:00
|
|
|
result
|
2021-09-30 00:11:48 +00:00
|
|
|
},
|
|
|
|
Target::IndirectARegDec(reg) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
2021-09-30 00:11:48 +00:00
|
|
|
*addr -= size.in_bytes();
|
|
|
|
get_address_sized(space, *addr as Address, size)
|
|
|
|
},
|
|
|
|
Target::IndirectARegOffset(reg, offset) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
2021-09-30 00:11:48 +00:00
|
|
|
get_address_sized(space, (*addr).wrapping_add(offset as u32) as Address, size)
|
|
|
|
},
|
|
|
|
Target::IndirectARegXRegOffset(reg, rtype, xreg, offset, target_size) => {
|
|
|
|
let reg_offset = get_value_sized(self.get_x_reg_value(rtype, xreg), target_size);
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
2021-09-30 00:11:48 +00:00
|
|
|
get_address_sized(space, (*addr).wrapping_add(reg_offset).wrapping_add(offset as u32) as Address, size)
|
|
|
|
},
|
|
|
|
Target::IndirectMemory(addr) => {
|
|
|
|
get_address_sized(space, addr as Address, size)
|
|
|
|
},
|
|
|
|
Target::IndirectPCOffset(offset) => {
|
|
|
|
get_address_sized(space, self.pc.wrapping_add(offset as u32) as Address, size)
|
|
|
|
},
|
|
|
|
Target::IndirectPCXRegOffset(rtype, xreg, offset, target_size) => {
|
|
|
|
let reg_offset = get_value_sized(self.get_x_reg_value(rtype, xreg), target_size);
|
|
|
|
get_address_sized(space, self.pc.wrapping_add(reg_offset).wrapping_add(offset as u32) as Address, size)
|
|
|
|
},
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn set_target_value(&mut self, space: &mut AddressSpace, target: Target, value: u32, size: Size) -> Result<(), Error> {
|
|
|
|
match target {
|
|
|
|
Target::DirectDReg(reg) => {
|
|
|
|
set_value_sized(&mut self.d_reg[reg as usize], value, size);
|
|
|
|
},
|
|
|
|
Target::DirectAReg(reg) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
set_value_sized(self.get_a_reg_mut(reg), value, size);
|
2021-09-30 00:11:48 +00:00
|
|
|
},
|
|
|
|
Target::IndirectAReg(reg) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
set_address_sized(space, *self.get_a_reg_mut(reg) as Address, value, size)?;
|
|
|
|
},
|
|
|
|
Target::IndirectARegInc(reg) => {
|
|
|
|
let addr = self.get_a_reg_mut(reg);
|
|
|
|
set_address_sized(space, *addr as Address, value, size)?;
|
|
|
|
*addr += size.in_bytes();
|
|
|
|
},
|
|
|
|
Target::IndirectARegDec(reg) => {
|
|
|
|
let addr = self.get_a_reg_mut(reg);
|
|
|
|
*addr -= size.in_bytes();
|
|
|
|
set_address_sized(space, *addr as Address, value, size)?;
|
|
|
|
},
|
|
|
|
Target::IndirectARegOffset(reg, offset) => {
|
|
|
|
let addr = self.get_a_reg_mut(reg);
|
|
|
|
set_address_sized(space, (*addr).wrapping_add(offset as u32) as Address, value, size)?;
|
|
|
|
},
|
|
|
|
Target::IndirectARegXRegOffset(reg, rtype, xreg, offset, target_size) => {
|
|
|
|
let reg_offset = get_value_sized(self.get_x_reg_value(rtype, xreg), target_size);
|
|
|
|
let addr = self.get_a_reg_mut(reg);
|
|
|
|
set_address_sized(space, (*addr).wrapping_add(reg_offset).wrapping_add(offset as u32) as Address, value, size)?;
|
|
|
|
},
|
|
|
|
Target::IndirectMemory(addr) => {
|
|
|
|
set_address_sized(space, addr as Address, value, size)?;
|
2021-09-30 00:11:48 +00:00
|
|
|
},
|
|
|
|
_ => return Err(Error::new(&format!("Unimplemented addressing target: {:?}", target))),
|
|
|
|
}
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_target_address(&mut self, target: Target) -> Result<u32, Error> {
|
|
|
|
let addr = match target {
|
2021-09-30 04:52:38 +00:00
|
|
|
Target::IndirectAReg(reg) => *self.get_a_reg_mut(reg),
|
2021-09-30 00:11:48 +00:00
|
|
|
Target::IndirectARegOffset(reg, offset) => {
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
2021-09-30 00:11:48 +00:00
|
|
|
(*addr).wrapping_add(offset as u32)
|
|
|
|
},
|
|
|
|
Target::IndirectARegXRegOffset(reg, rtype, xreg, offset, target_size) => {
|
|
|
|
let reg_offset = get_value_sized(self.get_x_reg_value(rtype, xreg), target_size);
|
2021-09-30 04:52:38 +00:00
|
|
|
let addr = self.get_a_reg_mut(reg);
|
2021-09-30 00:11:48 +00:00
|
|
|
(*addr).wrapping_add(reg_offset).wrapping_add(offset as u32)
|
|
|
|
},
|
|
|
|
Target::IndirectMemory(addr) => {
|
|
|
|
addr
|
|
|
|
},
|
|
|
|
Target::IndirectPCOffset(offset) => {
|
|
|
|
self.pc.wrapping_add(offset as u32)
|
|
|
|
},
|
|
|
|
Target::IndirectPCXRegOffset(rtype, xreg, offset, target_size) => {
|
|
|
|
let reg_offset = get_value_sized(self.get_x_reg_value(rtype, xreg), target_size);
|
|
|
|
self.pc.wrapping_add(reg_offset).wrapping_add(offset as u32)
|
|
|
|
},
|
2021-09-30 04:52:38 +00:00
|
|
|
_ => return Err(Error::new(&format!("Invalid addressing target: {:?}", target))),
|
2021-09-30 00:11:48 +00:00
|
|
|
};
|
|
|
|
Ok(addr)
|
|
|
|
}
|
|
|
|
|
2021-09-30 19:58:11 +00:00
|
|
|
fn subtract_sized_with_flags(&mut self, existing: u32, diff: u32, size: Size) -> u32 {
|
|
|
|
let (result, overflow) = match size {
|
|
|
|
Size::Byte => {
|
|
|
|
let (result, overflow) = (existing as u8).overflowing_sub(diff as u8);
|
|
|
|
(result as u32, overflow)
|
|
|
|
},
|
|
|
|
Size::Word => {
|
|
|
|
let (result, overflow) = (existing as u16).overflowing_sub(diff as u16);
|
|
|
|
(result as u32, overflow)
|
|
|
|
},
|
|
|
|
Size::Long => existing.overflowing_sub(diff),
|
|
|
|
};
|
|
|
|
self.set_compare_flags(result as i32, overflow);
|
|
|
|
result
|
|
|
|
}
|
|
|
|
|
2021-09-30 00:11:48 +00:00
|
|
|
fn get_control_reg_mut(&mut self, control_reg: ControlRegister) -> &mut u32 {
|
|
|
|
match control_reg {
|
|
|
|
ControlRegister::VBR => &mut self.vbr,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[inline(always)]
|
2021-09-30 04:52:38 +00:00
|
|
|
fn get_stack_pointer_mut(&mut self) -> &mut u32 {
|
2021-09-30 00:11:48 +00:00
|
|
|
if self.is_supervisor() { &mut self.msp } else { &mut self.usp }
|
|
|
|
}
|
|
|
|
|
|
|
|
#[inline(always)]
|
2021-09-30 04:52:38 +00:00
|
|
|
fn get_a_reg_mut(&mut self, reg: u8) -> &mut u32 {
|
2021-09-30 00:11:48 +00:00
|
|
|
if reg == 7 {
|
|
|
|
if self.is_supervisor() { &mut self.msp } else { &mut self.usp }
|
|
|
|
} else {
|
|
|
|
&mut self.a_reg[reg as usize]
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_x_reg_value(&self, rtype: RegisterType, reg: u8) -> u32 {
|
|
|
|
match rtype {
|
|
|
|
RegisterType::Data => self.d_reg[reg as usize],
|
|
|
|
RegisterType::Address => self.d_reg[reg as usize],
|
|
|
|
}
|
|
|
|
}
|
2021-09-30 04:52:38 +00:00
|
|
|
|
|
|
|
fn get_flag(&self, flag: u16) -> bool {
|
|
|
|
if (self.sr & flag) == 0 {
|
|
|
|
false
|
|
|
|
} else {
|
|
|
|
true
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn set_compare_flags(&mut self, value: i32, carry: bool) {
|
|
|
|
let mut flags = 0x0000;
|
|
|
|
if value < 0 {
|
|
|
|
flags |= FLAGS_NEGATIVE
|
|
|
|
}
|
|
|
|
if value == 0 {
|
|
|
|
flags |= FLAGS_ZERO
|
|
|
|
}
|
|
|
|
if carry {
|
|
|
|
flags |= FLAGS_CARRY | FLAGS_OVERFLOW;
|
|
|
|
}
|
|
|
|
self.sr |= (self.sr & 0xFFF0) | flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
fn set_logic_flags(&mut self, value: u32, size: Size) {
|
|
|
|
let mut flags = 0x0000;
|
|
|
|
match size {
|
|
|
|
Size::Byte if value & 0x80 != 0 => flags |= FLAGS_NEGATIVE,
|
|
|
|
Size::Word if value & 0x8000 != 0 => flags |= FLAGS_NEGATIVE,
|
|
|
|
Size::Long if value & 0x80000000 != 0 => flags |= FLAGS_NEGATIVE,
|
|
|
|
_ => { },
|
|
|
|
}
|
|
|
|
if value == 0 {
|
|
|
|
flags |= FLAGS_ZERO
|
|
|
|
}
|
|
|
|
self.sr |= (self.sr & 0xFFF0) | flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
fn get_current_condition(&self, cond: Condition) -> bool {
|
|
|
|
match cond {
|
2021-09-30 19:58:11 +00:00
|
|
|
Condition::True => true,
|
|
|
|
Condition::False => false,
|
|
|
|
Condition::High => !self.get_flag(FLAGS_CARRY) && !self.get_flag(FLAGS_ZERO),
|
|
|
|
Condition::LowOrSame => self.get_flag(FLAGS_CARRY) || self.get_flag(FLAGS_ZERO),
|
|
|
|
Condition::CarryClear => !self.get_flag(FLAGS_CARRY),
|
|
|
|
Condition::CarrySet => self.get_flag(FLAGS_CARRY),
|
|
|
|
Condition::NotEqual => !self.get_flag(FLAGS_ZERO),
|
|
|
|
Condition::Equal => self.get_flag(FLAGS_ZERO),
|
|
|
|
Condition::OverflowClear => !self.get_flag(FLAGS_OVERFLOW),
|
|
|
|
Condition::OverflowSet => self.get_flag(FLAGS_OVERFLOW),
|
|
|
|
Condition::Plus => !self.get_flag(FLAGS_NEGATIVE),
|
|
|
|
Condition::Minus => self.get_flag(FLAGS_NEGATIVE),
|
|
|
|
Condition::GreaterThanOrEqual => (self.get_flag(FLAGS_NEGATIVE) && self.get_flag(FLAGS_OVERFLOW)) || (!self.get_flag(FLAGS_NEGATIVE) && !self.get_flag(FLAGS_OVERFLOW)),
|
|
|
|
Condition::LessThan => (self.get_flag(FLAGS_NEGATIVE) && !self.get_flag(FLAGS_OVERFLOW)) || (!self.get_flag(FLAGS_NEGATIVE) && self.get_flag(FLAGS_OVERFLOW)),
|
|
|
|
Condition::GreaterThan =>
|
|
|
|
(self.get_flag(FLAGS_NEGATIVE) && self.get_flag(FLAGS_OVERFLOW) && !self.get_flag(FLAGS_ZERO))
|
|
|
|
|| (!self.get_flag(FLAGS_NEGATIVE) && !self.get_flag(FLAGS_OVERFLOW) && !self.get_flag(FLAGS_ZERO)),
|
|
|
|
Condition::LessThanOrEqual =>
|
2021-09-30 04:52:38 +00:00
|
|
|
self.get_flag(FLAGS_ZERO)
|
2021-09-30 19:58:11 +00:00
|
|
|
|| (self.get_flag(FLAGS_NEGATIVE) && !self.get_flag(FLAGS_OVERFLOW))
|
|
|
|
|| (!self.get_flag(FLAGS_NEGATIVE) && self.get_flag(FLAGS_OVERFLOW)),
|
2021-09-30 04:52:38 +00:00
|
|
|
}
|
|
|
|
}
|
2021-09-30 00:11:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
fn get_value_sized(value: u32, size: Size) -> u32 {
|
|
|
|
match size {
|
|
|
|
Size::Byte => { 0x000000FF & value },
|
|
|
|
Size::Word => { 0x0000FFFF & value },
|
|
|
|
Size::Long => { value },
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_address_sized(space: &mut AddressSpace, addr: Address, size: Size) -> Result<u32, Error> {
|
|
|
|
match size {
|
|
|
|
Size::Byte => space.read_u8(addr).map(|value| value as u32),
|
|
|
|
Size::Word => space.read_beu16(addr).map(|value| value as u32),
|
|
|
|
Size::Long => space.read_beu32(addr),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn set_value_sized(addr: &mut u32, value: u32, size: Size) {
|
|
|
|
match size {
|
|
|
|
Size::Byte => { *addr = (*addr & 0xFFFFFF00) | (0x000000FF & value); }
|
|
|
|
Size::Word => { *addr = (*addr & 0xFFFF0000) | (0x0000FFFF & value); }
|
|
|
|
Size::Long => { *addr = value; }
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn set_address_sized(space: &mut AddressSpace, addr: Address, value: u32, size: Size) -> Result<(), Error> {
|
|
|
|
match size {
|
|
|
|
Size::Byte => space.write_u8(addr, value as u8),
|
|
|
|
Size::Word => space.write_beu16(addr, value as u16),
|
|
|
|
Size::Long => space.write_beu32(addr, value),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
impl Processor for MC68010 {
|
|
|
|
|
|
|
|
}
|
|
|
|
*/
|