2021-09-28 23:09:38 +00:00
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#[macro_use]
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mod error;
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mod memory;
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2021-10-04 03:45:50 +00:00
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mod timers;
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2021-09-30 00:11:48 +00:00
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mod cpus;
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2021-09-30 06:21:11 +00:00
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mod devices;
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2021-09-28 23:09:38 +00:00
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2021-09-30 06:21:11 +00:00
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use crate::memory::{AddressSpace, MemoryBlock};
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2021-09-30 00:11:48 +00:00
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use crate::cpus::m68k::MC68010;
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2021-09-30 06:21:11 +00:00
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use crate::devices::mc68681::MC68681;
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2021-09-28 23:09:38 +00:00
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fn main() {
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let mut space = AddressSpace::new();
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2021-10-03 16:55:20 +00:00
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let monitor = MemoryBlock::load("binaries/monitor.bin").unwrap();
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2021-09-28 23:09:38 +00:00
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for byte in monitor.contents.iter() {
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print!("{:02x} ", byte);
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}
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2021-09-30 06:21:11 +00:00
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space.insert(0x00000000, Box::new(monitor));
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2021-09-28 23:09:38 +00:00
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2021-10-03 16:55:20 +00:00
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let mut ram = MemoryBlock::new(vec![0; 0x00100000]);
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ram.load_at(0, "binaries/kernel.bin").unwrap();
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2021-09-30 06:21:11 +00:00
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space.insert(0x00100000, Box::new(ram));
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2021-09-28 23:09:38 +00:00
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2021-10-01 03:27:01 +00:00
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let mut serial = MC68681::new();
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2021-10-01 19:25:23 +00:00
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serial.open().unwrap();
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2021-09-30 06:21:11 +00:00
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space.insert(0x00700000, Box::new(serial));
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2021-09-30 04:52:38 +00:00
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2021-09-28 23:09:38 +00:00
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let mut cpu = MC68010::new();
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2021-10-04 03:45:50 +00:00
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//cpu.enable_tracing();
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Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags
With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case. This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target
2021-10-03 04:59:28 +00:00
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//cpu.add_breakpoint(0x0c94);
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2021-10-04 18:13:10 +00:00
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//cpu.add_breakpoint(0x103234);
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//cpu.add_breakpoint(0x106e6a);
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2021-10-02 05:06:53 +00:00
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2021-09-28 23:09:38 +00:00
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while cpu.is_running() {
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2021-09-30 04:52:38 +00:00
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match cpu.step(&mut space) {
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Ok(()) => { },
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Err(err) => {
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2021-10-01 19:25:23 +00:00
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cpu.dump_state(&mut space);
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2021-09-30 04:52:38 +00:00
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panic!("{:?}", err);
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},
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}
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2021-10-01 19:25:23 +00:00
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//serial.step();
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2021-09-28 23:09:38 +00:00
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}
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2021-10-02 05:06:53 +00:00
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/*
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Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags
With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case. This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target
2021-10-03 04:59:28 +00:00
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// TODO I need to add a way to decode and dump the assembly for a section of code, in debugger
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2021-10-03 16:55:20 +00:00
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cpu.state.pc = 0x00100000;
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cpu.state.pc = 0x0010c270;
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2021-10-02 05:06:53 +00:00
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while cpu.is_running() {
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2021-10-03 16:55:20 +00:00
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match cpu.decode_next(&mut space) {
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Ok(()) => { },
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Err(err) => {
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cpu.dump_state(&mut space);
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panic!("{:?}", err);
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},
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}
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2021-10-02 05:06:53 +00:00
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}
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*/
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2021-09-28 23:09:38 +00:00
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}
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