diff --git a/emulator/cpus/m68k/src/assembler.rs b/emulator/cpus/m68k/src/assembler.rs index 7526e90..09e3739 100644 --- a/emulator/cpus/m68k/src/assembler.rs +++ b/emulator/cpus/m68k/src/assembler.rs @@ -201,7 +201,6 @@ impl M68kAssembler { fn convert_sized_instruction(&mut self, lineno: usize, mneumonic: &str, args: &[AssemblyOperand]) -> Result<(), Error> { let operation_size = get_size_from_mneumonic(mneumonic).ok_or_else(|| Error::new(&format!("error at line {}: expected a size specifier (b/w/l)", lineno))); match &mneumonic[..mneumonic.len() - 1] { - "addi" => { self.convert_common_immediate_instruction(lineno, 0x0600, args, operation_size?, Disallow::NoARegImmediateOrPC)?; }, @@ -317,18 +316,21 @@ impl M68kAssembler { } fn convert_common_dreg_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow) -> Result<(), Error> { - self.convert_common_reg_instruction(lineno, opcode, args, operation_size, disallow, Disallow::NoAReg) + parser::expect_args(lineno, args, 2)?; + let (direction, reg, operand) = convert_reg_and_other(lineno, args, Disallow::NoAReg)?; + let (effective_address, additional_words) = convert_target(lineno, operand, operation_size, disallow)?; + self.output.push(opcode | encode_size(operation_size) | direction | (reg << 9) | effective_address); + self.output.extend(additional_words); + Ok(()) } fn convert_common_areg_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow) -> Result<(), Error> { - self.convert_common_reg_instruction(lineno, opcode, args, operation_size, disallow, Disallow::NoDReg) - } - - fn convert_common_reg_instruction(&mut self, lineno: usize, opcode: u16, args: &[AssemblyOperand], operation_size: Size, disallow: Disallow, disallow_reg: Disallow) -> Result<(), Error> { + let size_bit = expect_a_instruction_size(lineno, operation_size)?; parser::expect_args(lineno, args, 2)?; - let (direction, reg, operand) = convert_reg_and_other(lineno, args, disallow_reg)?; - let (effective_address, additional_words) = convert_target(lineno, operand, operation_size, disallow)?; - self.output.push(opcode | encode_size(operation_size) | direction | (reg << 9) | effective_address); + //let (_direction, reg, operand) = convert_reg_and_other(lineno, args, Disallow::NoDReg)?; + let reg = expect_address_register(lineno, &args[1])?; + let (effective_address, additional_words) = convert_target(lineno, &args[0], operation_size, disallow)?; + self.output.push(opcode | size_bit | (0b11 << 6) | (reg << 9) | effective_address); self.output.extend(additional_words); Ok(()) } @@ -549,7 +551,7 @@ fn expect_data_register(lineno: usize, operand: &AssemblyOperand) -> Result Result { if let AssemblyOperand::Register(name) = operand { - if name.starts_with('d') { + if name.starts_with('a') { return expect_reg_num(lineno, name); } } @@ -572,6 +574,14 @@ fn expect_reg_num(lineno: usize, name: &str) -> Result { Err(Error::new(&format!("error at line {}: no such register {:?}", lineno, name))) } +fn expect_a_instruction_size(lineno: usize, size: Size) -> Result { + match size { + Size::Word => Ok(0), + Size::Long => Ok(0b1 << 8), + _ => Err(Error::new(&format!("error at line {}: address instructions can only be word or long size", lineno))), + } +} + fn get_size_from_mneumonic(s: &str) -> Option { let size_ch = s.chars().last()?; diff --git a/emulator/cpus/m68k/src/decode.rs b/emulator/cpus/m68k/src/decode.rs index 5ccc0bb..c59ac9c 100644 --- a/emulator/cpus/m68k/src/decode.rs +++ b/emulator/cpus/m68k/src/decode.rs @@ -424,7 +424,7 @@ impl M68kDecoder { } #[inline] - fn decode_group_moveq(&mut self, memory: &mut dyn Addressable, ins: u16) -> Result { + fn decode_group_moveq(&mut self, _memory: &mut dyn Addressable, ins: u16) -> Result { if (ins & 0x0100) != 0 { return Err(Error::processor(Exceptions::IllegalInstruction as u32)); } @@ -731,7 +731,7 @@ impl M68kDecoder { } } - fn get_mode_as_target(&mut self, memory: &mut dyn Addressable, mode: u8, reg: u8, size: Option) -> Result { + pub(super) fn get_mode_as_target(&mut self, memory: &mut dyn Addressable, mode: u8, reg: u8, size: Option) -> Result { let value = match mode { 0b000 => Target::DirectDReg(reg), 0b001 => Target::DirectAReg(reg), diff --git a/emulator/cpus/m68k/src/execute.rs b/emulator/cpus/m68k/src/execute.rs index 305b8dd..00e1050 100644 --- a/emulator/cpus/m68k/src/execute.rs +++ b/emulator/cpus/m68k/src/execute.rs @@ -1399,7 +1399,7 @@ impl M68k { } - fn get_target_value(&mut self, target: Target, size: Size, used: Used) -> Result { + pub(super) fn get_target_value(&mut self, target: Target, size: Size, used: Used) -> Result { match target { Target::Immediate(value) => Ok(value), Target::DirectDReg(reg) => Ok(get_value_sized(self.state.d_reg[reg as usize], size)), @@ -1439,7 +1439,7 @@ impl M68k { } } - fn set_target_value(&mut self, target: Target, value: u32, size: Size, used: Used) -> Result<(), Error> { + pub(super) fn set_target_value(&mut self, target: Target, value: u32, size: Size, used: Used) -> Result<(), Error> { match target { Target::DirectDReg(reg) => { set_value_sized(&mut self.state.d_reg[reg as usize], value, size); diff --git a/emulator/cpus/m68k/src/lib.rs b/emulator/cpus/m68k/src/lib.rs index d6f2c03..033ccac 100644 --- a/emulator/cpus/m68k/src/lib.rs +++ b/emulator/cpus/m68k/src/lib.rs @@ -7,7 +7,6 @@ pub mod debugger; pub mod instructions; pub mod timing; pub mod tests; -//pub mod testcases; pub use self::state::{M68k, M68kType}; diff --git a/emulator/cpus/m68k/src/tests.rs b/emulator/cpus/m68k/src/tests.rs index 092441a..90dc733 100644 --- a/emulator/cpus/m68k/src/tests.rs +++ b/emulator/cpus/m68k/src/tests.rs @@ -1,258 +1,29 @@ #[cfg(test)] -mod decode_tests { - use moa_core::{System, Error, ErrorType, MemoryBlock, BusPort, Address, Addressable, wrap_transmutable}; +mod decode_unit_tests { + use std::rc::Rc; + use std::cell::RefCell; - use crate::{M68k, M68kType}; - use crate::state::Exceptions; - use crate::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, Direction, ShiftDirection}; - use crate::timing::M68kInstructionTiming; - use crate::assembler::M68kAssembler; + use moa_core::{Bus, BusPort, Address, Addressable, MemoryBlock, wrap_transmutable}; - const INIT_STACK: Address = 0x00002000; - const INIT_ADDR: Address = 0x00000010; + use crate::M68kType; + use crate::instructions::{Target, Size, XRegister, BaseRegister, IndexRegister}; + use crate::decode::M68kDecoder; - struct TestCase { - cpu: M68kType, - data: &'static [u16], - ins: Option, - } + const INIT_ADDR: Address = 0x00000000; - const DECODE_TESTS: &'static [TestCase] = &[ - // MC68000 - TestCase { cpu: M68kType::MC68000, data: &[0x4e71], ins: Some(Instruction::NOP) }, - // TODO I think this one is illegal (which is causing problems for the assembler) - //TestCase { cpu: M68kType::MC68000, data: &[0x0008, 0x00FF], ins: Some(Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x003C, 0x00FF], ins: Some(Instruction::ORtoCCR(0xFF)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x007C, 0x1234], ins: Some(Instruction::ORtoSR(0x1234)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0263, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::IndirectARegDec(3), Size::Word)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0240, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::DirectDReg(0), Size::Word)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x02A3, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::IndirectARegDec(3), Size::Long)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0280, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::DirectDReg(0), Size::Long)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x023C, 0x1234], ins: Some(Instruction::ANDtoCCR(0x34)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x027C, 0xF8FF], ins: Some(Instruction::ANDtoSR(0xF8FF)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x4240], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Word)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x4280], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Long)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x4250], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Word)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x4290], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Long)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0487, 0x1234, 0x5678], ins: Some(Instruction::SUB(Target::Immediate(0x12345678), Target::DirectDReg(7), Size::Long)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x063A, 0x1234, 0x0055], ins: Some(Instruction::ADD(Target::Immediate(0x34), Target::IndirectRegOffset(BaseRegister::PC, None, 0x55), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0A23, 0x1234], ins: Some(Instruction::EOR(Target::Immediate(0x34), Target::IndirectARegDec(3), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0A3C, 0x1234], ins: Some(Instruction::EORtoCCR(0x34)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0A7C, 0xF8FF], ins: Some(Instruction::EORtoSR(0xF8FF)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0020], ins: Some(Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0030], ins: Some(Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0010], ins: Some(Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x81FC, 0x0003], ins: Some(Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xC1FC, 0x0276], ins: Some(Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xCDC5], ins: Some(Instruction::MULW(Target::DirectDReg(5), 6, Sign::Signed)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0108, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::FromTarget)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0148, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::FromTarget)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x0188, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::ToTarget)) }, - TestCase { cpu: M68kType::MC68000, data: &[0x01C8, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::ToTarget)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xE300], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xE200], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xE318], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xE218], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xA000], ins: Some(Instruction::UnimplementedA(0xA000)) }, - TestCase { cpu: M68kType::MC68000, data: &[0xFFFF], ins: Some(Instruction::UnimplementedF(0xFFFF)) }, + fn init_decode_test(cputype: M68kType) -> (BusPort, M68kDecoder) { + let bus = Rc::new(RefCell::new(Bus::default())); + let mem = MemoryBlock::new(vec![0; 0x0000100]); + bus.borrow_mut().insert(0x00000000, wrap_transmutable(mem)); - // MC68030 - TestCase { cpu: M68kType::MC68030, data: &[0x4C3C, 0x0800, 0x0000, 0x0097], ins: Some(Instruction::MULL(Target::Immediate(0x97), None, 0, Sign::Signed)) }, - TestCase { cpu: M68kType::MC68030, data: &[0x21BC, 0x0010, 0x14C4, 0x09B0, 0x0010, 0xDF40], ins: Some(Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long)) }, - - // Should Fail - TestCase { cpu: M68kType::MC68000, data: &[0x21BC, 0x0010, 0x14C4, 0x09B0, 0x0010, 0xDF40], ins: None }, - ]; - - - fn init_decode_test(cputype: M68kType) -> (M68k, System) { - let mut system = System::new(); - - // Insert basic initialization - let data = vec![0; 0x00100000]; - let mem = MemoryBlock::new(data); - system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap(); - system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap(); - system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap(); - - // Initialize the CPU and make sure it's in the expected state let port = if cputype <= M68kType::MC68010 { - BusPort::new(0, 24, 16, system.bus.clone()) + BusPort::new(0, 24, 16, bus) } else { - BusPort::new(0, 24, 16, system.bus.clone()) + BusPort::new(0, 32, 32, bus) }; - let mut cpu = M68k::new(cputype, 10_000_000, port); - cpu.init().unwrap(); - assert_eq!(cpu.state.pc, INIT_ADDR as u32); - assert_eq!(cpu.state.ssp, INIT_STACK as u32); - - cpu.decoder.init(INIT_ADDR as u32); - assert_eq!(cpu.decoder.start, INIT_ADDR as u32); - assert_eq!(cpu.decoder.instruction, Instruction::NOP); - (cpu, system) - } - - fn load_memory(system: &System, data: &[u16]) { - let mut addr = INIT_ADDR; - for word in data { - system.get_bus().write_beu16(addr, *word).unwrap(); - addr += 2; - } - } - - fn run_decode_test(case: &TestCase) { - let (mut cpu, system) = init_decode_test(case.cpu); - load_memory(&system, case.data); - match &case.ins { - Some(ins) => { - cpu.decode_next().unwrap(); - assert_eq!(cpu.decoder.instruction, ins.clone()); - }, - None => { - assert!(cpu.decode_next().is_err()); - }, - } - } - - #[test] - pub fn run_decode_tests() { - for case in DECODE_TESTS { - println!("Testing for {:?}", case.ins); - run_decode_test(case); - } - } - - #[test] - pub fn run_assembler_tests() { - let mut tests = 0; - let mut errors = 0; - - for case in DECODE_TESTS { - if case.ins.is_some() { - tests += 1; - let assembly_text = format!("{}", case.ins.as_ref().unwrap()); - print!("Testing assembling of {:?} ", assembly_text); - let mut assembler = M68kAssembler::new(M68kType::MC68000); - match assembler.assemble_words(&assembly_text) { - Ok(data) => { - if data == case.data { - print!("pass"); - } else { - errors += 1; - print!("FAILED"); - print!("\nleft: {:?}, right: {:?}", data, case.data); - } - println!(); - }, - Err(err) => { - println!("FAILED\n{:?}", err); - errors += 1; - }, - } - } - } - - if errors > 0 { - panic!("{} errors out of {} tests", errors, tests); - } - } - - - /* - #[test] - pub fn run_assembler_opcode_tests() { - let mut tests = 0; - let mut errors = 0; - - use super::super::testcases::{TimingCase, TIMING_TESTS}; - for case in TIMING_TESTS { - tests += 1; - let assembly_text = format!("{}", case.ins); - print!("Testing assembling of {:?} from {:?}", assembly_text, case.ins); - - let mut assembler = M68kAssembler::new(M68kType::MC68000); - match assembler.assemble_words(&assembly_text) { - Ok(data) => { - if data[0] == case.data[0] { - print!("pass"); - } else { - errors += 1; - print!("FAILED"); - print!("\nleft: {:#06x}, right: {:#06x}", data[0], case.data[0]); - } - println!(); - }, - Err(err) => { - println!("FAILED\n{:?}", err); - errors += 1; - }, - } - } - - if errors > 0 { - panic!("{} errors out of {} tests", errors, tests); - } - } - */ - - //use super::super::testcases::{TimingCase, TIMING_TESTS}; - - struct TimingCase { - cpu: M68kType, - data: &'static [u16], - timing: (u16, u16, u16), - ins: Instruction, - } - - const TIMING_TESTS: &'static [TimingCase] = &[ - TimingCase { cpu: M68kType::MC68000, data: &[0xD090], timing: ( 14, 14, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, - ]; - - fn run_timing_test(case: &TimingCase) -> Result<(), Error> { - let (mut cpu, system) = init_decode_test(case.cpu); - let mut timing = M68kInstructionTiming::new(case.cpu, 16); - - load_memory(&system, case.data); - cpu.decode_next().unwrap(); - assert_eq!(cpu.decoder.instruction, case.ins.clone()); - - timing.add_instruction(&cpu.decoder.instruction); - let result = timing.calculate_clocks(false, 1); - let expected = match case.cpu { - M68kType::MC68000 => case.timing.0, - M68kType::MC68010 => case.timing.1, - _ => case.timing.2, - }; - - //assert_eq!(expected, result); - if expected == result { - Ok(()) - } else { - println!("{:?}", timing); - Err(Error::new(&format!("expected {} but found {}", expected, result))) - } - } - - #[test] - pub fn run_timing_tests() { - let mut errors = 0; - for case in TIMING_TESTS { - // NOTE switched to only show the failures rather than all tests - //print!("Testing for {:?}...", case.ins); - //match run_timing_test(case) { - // Ok(()) => println!("ok"), - // Err(err) => { println!("{}", err.msg); errors += 1 }, - //} - - if let Err(_) = run_timing_test(case) { - errors += 1; - } - } - - if errors > 0 { - panic!("{} errors", errors); - } + let decoder = M68kDecoder::new(cputype, 0); + (port, decoder) } // @@ -261,274 +32,234 @@ mod decode_tests { #[test] fn target_direct_d() { - let (mut cpu, _) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b000, 0b001, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b000, 0b001, Some(size)).unwrap(); assert_eq!(target, Target::DirectDReg(1)); } #[test] fn target_direct_a() { - let (mut cpu, _) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b001, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b001, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::DirectAReg(2)); } #[test] fn target_indirect_a() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let expected = 0x12345678; - system.get_bus().write_beu32(INIT_ADDR, expected).unwrap(); + port.write_beu32(INIT_ADDR, expected).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b010, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b010, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectAReg(2)); } #[test] fn target_indirect_a_inc() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let expected = 0x12345678; - system.get_bus().write_beu32(INIT_ADDR, expected).unwrap(); + port.write_beu32(INIT_ADDR, expected).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b011, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b011, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectARegInc(2)); } #[test] fn target_indirect_a_dec() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let expected = 0x12345678; - system.get_bus().write_beu32(INIT_ADDR, expected).unwrap(); + port.write_beu32(INIT_ADDR, expected).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b100, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b100, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectARegDec(2)); } #[test] fn target_indirect_a_reg_offset() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let offset = -8; - system.get_bus().write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap(); + port.write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b101, 0b100, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b101, 0b100, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(4), None, offset)); } #[test] fn target_indirect_a_reg_brief_extension_word() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let offset = -8; let brief_extension = 0x3800 | (((offset as i8) as u8) as u16); - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b110, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b110, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset)); } #[test] fn target_indirect_a_reg_full_extension_word() { - let (mut cpu, system) = init_decode_test(M68kType::MC68020); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68020); let size = Size::Word; let offset = -1843235 as i32; let brief_extension = 0xF330; - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b110, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b110, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset)); } #[test] fn target_indirect_a_reg_full_extension_word_no_base() { - let (mut cpu, system) = init_decode_test(M68kType::MC68020); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68020); let size = Size::Word; let offset = -1843235 as i32; let brief_extension = 0xF3B0; - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b110, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b110, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset)); } #[test] fn target_indirect_a_reg_full_extension_word_no_index() { - let (mut cpu, system) = init_decode_test(M68kType::MC68020); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68020); let size = Size::Word; let offset = -1843235 as i32; let brief_extension = 0xF370; - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b110, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b110, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), None, offset)); } #[test] fn target_indirect_pc_offset() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Long; let offset = -8; - system.get_bus().write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap(); + port.write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b010, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b010, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, None, offset)); } #[test] fn target_indirect_pc_brief_extension_word() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; let offset = -8; let brief_extension = 0x3000 | (((offset as i8) as u8) as u16); - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b011, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b011, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset)); } #[test] fn target_indirect_pc_full_extension_word() { - let (mut cpu, system) = init_decode_test(M68kType::MC68020); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68020); let size = Size::Word; let offset = -1843235 as i32; let brief_extension = 0xF330; - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); + port.write_beu16(INIT_ADDR, brief_extension).unwrap(); + port.write_beu32(INIT_ADDR + 2, offset as u32).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b011, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b011, Some(size)).unwrap(); assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset)); } #[test] fn target_indirect_immediate_word() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; let expected = 0x1234; - system.get_bus().write_beu16(INIT_ADDR, expected as u16).unwrap(); + port.write_beu16(INIT_ADDR, expected as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b000, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b000, Some(size)).unwrap(); assert_eq!(target, Target::IndirectMemory(expected, Size::Word)); } #[test] fn target_indirect_immediate_long() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; let expected = 0x12345678; - system.get_bus().write_beu32(INIT_ADDR, expected).unwrap(); + port.write_beu32(INIT_ADDR, expected).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b001, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b001, Some(size)).unwrap(); assert_eq!(target, Target::IndirectMemory(expected, Size::Long)); } #[test] fn target_immediate() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); + let (mut port, mut decoder) = init_decode_test(M68kType::MC68010); let size = Size::Word; let expected = 0x1234; - system.get_bus().write_beu16(INIT_ADDR, expected as u16).unwrap(); + port.write_beu16(INIT_ADDR, expected as u16).unwrap(); - let target = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b111, 0b100, Some(size)).unwrap(); + let target = decoder.get_mode_as_target(&mut port, 0b111, 0b100, Some(size)).unwrap(); assert_eq!(target, Target::Immediate(expected)); } - - #[test] - fn target_full_extension_word_unsupported_on_mc68010() { - let (mut cpu, system) = init_decode_test(M68kType::MC68010); - - let brief_extension = 0x0100; - - system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap(); - - let result = cpu.decoder.get_mode_as_target(&mut cpu.port, 0b110, 0b010, Some(Size::Long)); - match result { - Err(Error { err: ErrorType::Processor, native, .. }) if native == Exceptions::IllegalInstruction as u32 => { }, - result => panic!("Expected illegal instruction but found: {:?}", result), - } - } } #[cfg(test)] -mod execute_tests { +mod execute_unit_tests { use moa_core::{System, MemoryBlock, BusPort, Address, Addressable, Steppable, wrap_transmutable}; use crate::{M68k, M68kType}; - use crate::state::M68kState; use crate::execute::Used; - use crate::instructions::{Instruction, Target, Size, Sign, ShiftDirection, Direction, Condition}; + use crate::instructions::{Instruction, Target, Size}; const INIT_STACK: Address = 0x00002000; const INIT_ADDR: Address = 0x00000010; - const MEM_ADDR: u32 = 0x00001234; - - struct TestState { - pc: u32, - ssp: u32, - usp: u32, - d0: u32, - d1: u32, - a0: u32, - a1: u32, - sr: u16, - mem: u32, - } - - struct TestCase { - name: &'static str, - ins: Instruction, - data: &'static [u16], - cputype: M68kType, - init: TestState, - fini: TestState, - } - - fn init_execute_test(cputype: M68kType) -> (M68k, System) { - let mut system = System::new(); + let mut system = System::default(); // Insert basic initialization let data = vec![0; 0x00100000]; @@ -551,621 +282,6 @@ mod execute_tests { (cpu, system) } - fn build_state(state: &TestState) -> M68kState { - let mut new_state = M68kState::new(); - new_state.pc = state.pc; - new_state.ssp = state.ssp; - new_state.usp = state.usp; - new_state.d_reg[0] = state.d0; - new_state.d_reg[1] = state.d1; - new_state.a_reg[0] = state.a0; - new_state.a_reg[1] = state.a1; - new_state.sr = state.sr; - new_state - } - - fn load_memory(system: &System, data: &[u16]) { - for i in 0..data.len() { - system.get_bus().write_beu16((i << 1) as Address, data[i]).unwrap(); - } - } - - fn run_test(case: &TestCase) { - let (mut cpu, system) = init_execute_test(case.cputype); - - let init_state = build_state(&case.init); - let expected_state = build_state(&case.fini); - system.get_bus().write_beu32(MEM_ADDR as Address, case.init.mem).unwrap(); - - load_memory(&system, case.data); - cpu.state = init_state; - - cpu.decode_next().unwrap(); - assert_eq!(cpu.decoder.instruction, case.ins); - - cpu.execute_current().unwrap(); - assert_eq!(cpu.state, expected_state); - - let mem = system.get_bus().read_beu32(MEM_ADDR as Address).unwrap(); - assert_eq!(mem, case.fini.mem); - } - - #[test] - pub fn run_execute_tests() { - for case in TEST_CASES { - println!("Running test {}", case.name); - run_test(case); - } - } - - #[test] - pub fn run_assembler_tests() { - use crate::cpus::m68k::assembler::M68kAssembler; - - let mut tests = 0; - let mut errors = 0; - - for case in TEST_CASES { - tests += 1; - let assembly_text = format!("{}", case.ins); - print!("Testing assembling of {:?} ", assembly_text); - let mut assembler = M68kAssembler::new(M68kType::MC68000); - match assembler.assemble_words(&assembly_text) { - Ok(data) => { - if data == case.data { - print!("pass"); - } else { - errors += 1; - print!("FAILED"); - print!("\nleft: {:?}, right: {:?}", data, case.data); - } - println!(); - }, - Err(err) => { - println!("FAILED\n{:?}", err); - errors += 1; - }, - } - } - - if errors > 0 { - panic!("{} errors out of {} tests", errors, tests); - } - } - - - const TEST_CASES: &'static [TestCase] = &[ - TestCase { - name: "nop", - ins: Instruction::NOP, - data: &[ 0x4e71 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "addi with no overflow or carry", - ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0600, 0x007F ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007f, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "addi with no overflow but negative", - ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0600, 0x0080 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "addi with overflow", - ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0600, 0x007F ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, - }, - TestCase { - name: "addi with carry", - ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0600, 0x0080 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2717, mem: 0x00000000 }, - }, - TestCase { - name: "adda immediate", - ins: Instruction::ADDA(Target::Immediate(0xF800), 0, Size::Word), - data: &[ 0xD0FC, 0xF800 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - }, - TestCase { - name: "adda register", - ins: Instruction::ADDA(Target::DirectDReg(0), 0, Size::Word), - data: &[ 0xD0C0 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - }, - TestCase { - name: "addx", - ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0xD101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FE, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, - }, - TestCase { - name: "addx with extend", - ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0xD101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, - }, - TestCase { - name: "addx with extend and carry", - ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0xD101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, - }, - TestCase { - name: "andi with sr", - ins: Instruction::ANDtoSR(0xF8FF), - data: &[ 0x027C, 0xF8FF ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7AA, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA0AA, mem: 0x00000000 }, - }, - TestCase { - name: "asl", - ins: Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE300 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "asr", - ins: Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), - data: &[ 0xE200 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000C0, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, - }, - TestCase { - name: "blt with jump", - ins: Instruction::Bcc(Condition::LessThan, 8), - data: &[ 0x6D08 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, - fini: TestState { pc: 0x0000000A, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, - }, - TestCase { - name: "blt with jump", - ins: Instruction::Bcc(Condition::LessThan, 8), - data: &[ 0x6D08 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "bchg not zero", - ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long), - data: &[ 0x0841, 0x0007 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x000000FF, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "bchg zero", - ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long), - data: &[ 0x0841, 0x0007 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000080, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 }, - }, - TestCase { - name: "bra 8-bit", - ins: Instruction::BRA(-32), - data: &[ 0x60E0 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0xFFFFFFE2, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi equal", - ins: Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x0020 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi greater than", - ins: Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x0030 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi less than", - ins: Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x0010 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi no overflow", - ins: Instruction::CMP(Target::Immediate(0x7F), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x007F ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi no overflow, already negative", - ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word), - data: &[ 0x0C40, 0x8001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi with overflow", - ins: Instruction::CMP(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x0080 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi with overflow 2", - ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word), - data: &[ 0x0C40, 0x8001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi no carry", - ins: Instruction::CMP(Target::Immediate(0x01), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "cmpi with carry", - ins: Instruction::CMP(Target::Immediate(0xFF), Target::DirectDReg(0), Size::Byte), - data: &[ 0x0C00, 0x00FF ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, - }, - TestCase { - name: "divu", - ins: Instruction::DIVW(Target::Immediate(0x0245), 0, Sign::Unsigned), - data: &[ 0x80FC, 0x0245 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00040000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x007101C3, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "divs", - ins: Instruction::DIVW(Target::Immediate(48), 0, Sign::Signed), - data: &[ 0x81FC, 0x0030 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFEB00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF90, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "eori", - ins: Instruction::EOR(Target::DirectDReg(1), Target::DirectDReg(0), Size::Long), - data: &[ 0xB380 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAAAA5555, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFF0000FF, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "exg", - ins: Instruction::EXG(Target::DirectDReg(0), Target::DirectAReg(1)), - data: &[ 0xC189 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x12345678, d1: 0x00000000, a0: 0x00000000, a1: 0x87654321, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x87654321, d1: 0x00000000, a0: 0x00000000, a1: 0x12345678, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "ext", - ins: Instruction::EXT(0, Size::Byte, Size::Word), - data: &[ 0x4880 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FFCB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F8, mem: 0x00000000 }, - }, - TestCase { - name: "ext", - ins: Instruction::EXT(0, Size::Word, Size::Long), - data: &[ 0x48C0 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F0, mem: 0x00000000 }, - }, - - TestCase { - name: "lsl", - ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE308 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x271F, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "lsl with bit out", - ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE308 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 }, - }, - TestCase { - name: "lsr", - ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), - data: &[ 0xE208 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000040, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 }, - }, - - TestCase { - name: "muls", - ins: Instruction::MULW(Target::Immediate(0x0276), 0, Sign::Signed), - data: &[ 0xC1FC, 0x0276 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000200, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0004ec00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "movel", - ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(1), Size::Long), - data: &[ 0x2200 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0xFEDCBA98, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "movea", - ins: Instruction::MOVEA(Target::DirectDReg(0), 0, Size::Long), - data: &[ 0x2040 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0xFEDCBA98, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - }, - - // MOVEM - TestCase { - name: "movem word to target", - ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Word, Direction::ToTarget, 0x0003), - data: &[ 0x4890, 0x0003 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x12345678 }, - }, - TestCase { - name: "movem long to target", - ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::ToTarget, 0x0001), - data: &[ 0x48D0, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - }, - TestCase { - name: "movem long from target", - ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::FromTarget, 0x0001), - data: &[ 0x4CD0, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - }, - TestCase { - name: "movem word from target inc", - ins: Instruction::MOVEM(Target::IndirectARegInc(0), Size::Word, Direction::FromTarget, 0x0001), - data: &[ 0x4C98, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFFFFF, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFABCD, d1: 0x00000000, a0: MEM_ADDR+2, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - }, - TestCase { - name: "movem long to target dec", - ins: Instruction::MOVEM(Target::IndirectARegDec(0), Size::Long, Direction::ToTarget, 0x8000), - data: &[ 0x48E0, 0x8000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR+4, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, - }, - - - // MOVEP - TestCase { - name: "movep word to even memory", - ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::ToTarget), - data: &[ 0x0188, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, - }, - TestCase { - name: "movep word to odd memory", - ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::ToTarget), - data: &[ 0x0188, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, - }, - TestCase { - name: "movep long to even memory upper", - ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget), - data: &[ 0x01C8, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, - }, - TestCase { - name: "movep long to even memory lower", - ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget), - data: &[ 0x01C8, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, - }, - TestCase { - name: "movep word from even memory", - ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::FromTarget), - data: &[ 0x0108, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, - }, - TestCase { - name: "movep word from odd memory", - ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::FromTarget), - data: &[ 0x0108, 0x0001 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, - }, - TestCase { - name: "movep long from even memory upper", - ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget), - data: &[ 0x0148, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABB0000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, - }, - TestCase { - name: "movep long from even memory lower", - ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget), - data: &[ 0x0148, 0x0000 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000CCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, - }, - - - // NEG - TestCase { - name: "neg", - ins: Instruction::NEG(Target::DirectDReg(0), Size::Word), - data: &[ 0x4440 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF80, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, - }, - - - TestCase { - name: "ori", - ins: Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte), - data: &[ 0x0008, 0x00FF ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x000000FF, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "ori with sr", - ins: Instruction::ORtoSR(0x00AA), - data: &[ 0x007C, 0x00AA ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA755, mem: 0x00000000 }, - fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7FF, mem: 0x00000000 }, - }, - - - - TestCase { - name: "rol", - ins: Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE318 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, - }, - TestCase { - name: "ror", - ins: Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), - data: &[ 0xE218 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, - }, - TestCase { - name: "roxl", - ins: Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE310 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, - }, - TestCase { - name: "roxr", - ins: Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), - data: &[ 0xE210 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, - }, - TestCase { - name: "roxl two bits", - ins: Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), - data: &[ 0xE510 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - }, - TestCase { - name: "roxr two bits", - ins: Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), - data: &[ 0xE410 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - - TestCase { - name: "subx", - ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0x9101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, - }, - TestCase { - name: "subx with extend", - ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0x9101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2702, mem: 0x00000000 }, - }, - TestCase { - name: "subx with extend and carry", - ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), - data: &[ 0x9101 ], - cputype: M68kType::MC68010, - init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, - fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, - }, - ]; - - // // Addressing Mode Target Tests // diff --git a/emulator/cpus/m68k/tests/decode_tests.rs b/emulator/cpus/m68k/tests/decode_tests.rs new file mode 100644 index 0000000..e60028d --- /dev/null +++ b/emulator/cpus/m68k/tests/decode_tests.rs @@ -0,0 +1,195 @@ + +use moa_core::{System, MemoryBlock, BusPort, Address, Addressable, wrap_transmutable}; + +use moa_m68k::{M68k, M68kType}; +use moa_m68k::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, Direction, ShiftDirection}; +use moa_m68k::assembler::M68kAssembler; + +const INIT_STACK: Address = 0x00002000; +const INIT_ADDR: Address = 0x00000010; + +struct TestCase { + cpu: M68kType, + data: &'static [u16], + ins: Option, +} + +const DECODE_TESTS: &'static [TestCase] = &[ + // MC68000 + TestCase { cpu: M68kType::MC68000, data: &[0x4e71], ins: Some(Instruction::NOP) }, + // TODO I think this one is illegal (which is causing problems for the assembler) + //TestCase { cpu: M68kType::MC68000, data: &[0x0008, 0x00FF], ins: Some(Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x003C, 0x00FF], ins: Some(Instruction::ORtoCCR(0xFF)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x007C, 0x1234], ins: Some(Instruction::ORtoSR(0x1234)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0263, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::IndirectARegDec(3), Size::Word)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0240, 0x1234], ins: Some(Instruction::AND(Target::Immediate(0x1234), Target::DirectDReg(0), Size::Word)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x02A3, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::IndirectARegDec(3), Size::Long)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0280, 0x1234, 0x5678], ins: Some(Instruction::AND(Target::Immediate(0x12345678), Target::DirectDReg(0), Size::Long)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x023C, 0x1234], ins: Some(Instruction::ANDtoCCR(0x34)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x027C, 0xF8FF], ins: Some(Instruction::ANDtoSR(0xF8FF)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x4240], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Word)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x4280], ins: Some(Instruction::CLR(Target::DirectDReg(0), Size::Long)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x4250], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Word)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x4290], ins: Some(Instruction::CLR(Target::IndirectAReg(0), Size::Long)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0487, 0x1234, 0x5678], ins: Some(Instruction::SUB(Target::Immediate(0x12345678), Target::DirectDReg(7), Size::Long)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x063A, 0x1234, 0x0055], ins: Some(Instruction::ADD(Target::Immediate(0x34), Target::IndirectRegOffset(BaseRegister::PC, None, 0x55), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0A23, 0x1234], ins: Some(Instruction::EOR(Target::Immediate(0x34), Target::IndirectARegDec(3), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0A3C, 0x1234], ins: Some(Instruction::EORtoCCR(0x34)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0A7C, 0xF8FF], ins: Some(Instruction::EORtoSR(0xF8FF)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0020], ins: Some(Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0030], ins: Some(Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0010], ins: Some(Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x81FC, 0x0003], ins: Some(Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xC1FC, 0x0276], ins: Some(Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xCDC5], ins: Some(Instruction::MULW(Target::DirectDReg(5), 6, Sign::Signed)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0108, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::FromTarget)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0148, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::FromTarget)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x0188, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::ToTarget)) }, + TestCase { cpu: M68kType::MC68000, data: &[0x01C8, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::ToTarget)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xE300], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xE200], ins: Some(Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xE318], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xE218], ins: Some(Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xA000], ins: Some(Instruction::UnimplementedA(0xA000)) }, + TestCase { cpu: M68kType::MC68000, data: &[0xFFFF], ins: Some(Instruction::UnimplementedF(0xFFFF)) }, + + // MC68030 + TestCase { cpu: M68kType::MC68030, data: &[0x4C3C, 0x0800, 0x0000, 0x0097], ins: Some(Instruction::MULL(Target::Immediate(0x97), None, 0, Sign::Signed)) }, + TestCase { cpu: M68kType::MC68030, data: &[0x21BC, 0x0010, 0x14C4, 0x09B0, 0x0010, 0xDF40], ins: Some(Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long)) }, + + // Should Fail +]; + + +fn init_decode_test(cputype: M68kType) -> (M68k, System) { + let mut system = System::default(); + + // Insert basic initialization + let data = vec![0; 0x00100000]; + let mem = MemoryBlock::new(data); + system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap(); + system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap(); + system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap(); + + // Initialize the CPU and make sure it's in the expected state + let port = if cputype <= M68kType::MC68010 { + BusPort::new(0, 24, 16, system.bus.clone()) + } else { + BusPort::new(0, 24, 16, system.bus.clone()) + }; + let mut cpu = M68k::new(cputype, 10_000_000, port); + cpu.init().unwrap(); + assert_eq!(cpu.state.pc, INIT_ADDR as u32); + assert_eq!(cpu.state.ssp, INIT_STACK as u32); + + cpu.decoder.init(INIT_ADDR as u32); + assert_eq!(cpu.decoder.start, INIT_ADDR as u32); + assert_eq!(cpu.decoder.instruction, Instruction::NOP); + (cpu, system) +} + +fn load_memory(system: &System, data: &[u16]) { + let mut addr = INIT_ADDR; + for word in data { + system.get_bus().write_beu16(addr, *word).unwrap(); + addr += 2; + } +} + +fn run_decode_test(case: &TestCase) { + let (mut cpu, system) = init_decode_test(case.cpu); + load_memory(&system, case.data); + match &case.ins { + Some(ins) => { + cpu.decode_next().unwrap(); + assert_eq!(cpu.decoder.instruction, ins.clone()); + }, + None => { + let next = cpu.decode_next(); + println!("{:?}", cpu.decoder.instruction); + assert!(next.is_err()); + }, + } +} + +#[test] +pub fn run_decode_tests() { + for case in DECODE_TESTS { + println!("Testing for {:?}", case.ins); + run_decode_test(case); + } +} + +#[test] +pub fn run_assembler_tests() { + let mut tests = 0; + let mut errors = 0; + + for case in DECODE_TESTS { + if case.ins.is_some() { + tests += 1; + let assembly_text = format!("{}", case.ins.as_ref().unwrap()); + print!("Testing assembling of {:?} ", assembly_text); + let mut assembler = M68kAssembler::new(M68kType::MC68000); + match assembler.assemble_words(&assembly_text) { + Ok(data) => { + if data == case.data { + print!("pass"); + } else { + errors += 1; + print!("FAILED"); + print!("\nleft: {:?}, right: {:?}", data, case.data); + } + println!(); + }, + Err(err) => { + println!("FAILED\n{:?}", err); + errors += 1; + }, + } + } + } + + if errors > 0 { + panic!("{} errors out of {} tests", errors, tests); + } +} + + +/* +#[test] +pub fn run_assembler_opcode_tests() { + let mut tests = 0; + let mut errors = 0; + + use super::super::testcases::{TimingCase, TIMING_TESTS}; + for case in TIMING_TESTS { + tests += 1; + let assembly_text = format!("{}", case.ins); + print!("Testing assembling of {:?} from {:?}", assembly_text, case.ins); + + let mut assembler = M68kAssembler::new(M68kType::MC68000); + match assembler.assemble_words(&assembly_text) { + Ok(data) => { + if data[0] == case.data[0] { + print!("pass"); + } else { + errors += 1; + print!("FAILED"); + print!("\nleft: {:#06x}, right: {:#06x}", data[0], case.data[0]); + } + println!(); + }, + Err(err) => { + println!("FAILED\n{:?}", err); + errors += 1; + }, + } + } + + if errors > 0 { + panic!("{} errors out of {} tests", errors, tests); + } +} +*/ + diff --git a/emulator/cpus/m68k/tests/execute_tests.rs b/emulator/cpus/m68k/tests/execute_tests.rs new file mode 100644 index 0000000..a9eb0b3 --- /dev/null +++ b/emulator/cpus/m68k/tests/execute_tests.rs @@ -0,0 +1,679 @@ + +use moa_core::{System, MemoryBlock, BusPort, Address, Addressable, Steppable, wrap_transmutable}; + +use moa_m68k::{M68k, M68kType}; +use moa_m68k::state::M68kState; +use moa_m68k::instructions::{Instruction, Target, Size, Sign, ShiftDirection, Direction, Condition}; + +const INIT_STACK: Address = 0x00002000; +const INIT_ADDR: Address = 0x00000010; + +const MEM_ADDR: u32 = 0x00001234; + +struct TestState { + pc: u32, + ssp: u32, + usp: u32, + d0: u32, + d1: u32, + a0: u32, + a1: u32, + sr: u16, + mem: u32, +} + +struct TestCase { + name: &'static str, + ins: Instruction, + data: &'static [u16], + cputype: M68kType, + init: TestState, + fini: TestState, +} + + +fn init_execute_test(cputype: M68kType) -> (M68k, System) { + let mut system = System::default(); + + // Insert basic initialization + let data = vec![0; 0x00100000]; + let mem = MemoryBlock::new(data); + system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap(); + system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap(); + system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap(); + + let port = if cputype <= M68kType::MC68010 { + BusPort::new(0, 24, 16, system.bus.clone()) + } else { + BusPort::new(0, 24, 16, system.bus.clone()) + }; + let mut cpu = M68k::new(cputype, 10_000_000, port); + cpu.step(&system).unwrap(); + cpu.decoder.init(cpu.state.pc); + assert_eq!(cpu.state.pc, INIT_ADDR as u32); + assert_eq!(cpu.state.ssp, INIT_STACK as u32); + assert_eq!(cpu.decoder.instruction, Instruction::NOP); + (cpu, system) +} + +fn build_state(state: &TestState) -> M68kState { + let mut new_state = M68kState::default(); + new_state.pc = state.pc; + new_state.ssp = state.ssp; + new_state.usp = state.usp; + new_state.d_reg[0] = state.d0; + new_state.d_reg[1] = state.d1; + new_state.a_reg[0] = state.a0; + new_state.a_reg[1] = state.a1; + new_state.sr = state.sr; + new_state +} + +fn load_memory(system: &System, data: &[u16]) { + for i in 0..data.len() { + system.get_bus().write_beu16((i << 1) as Address, data[i]).unwrap(); + } +} + +fn run_test(case: &TestCase) { + let (mut cpu, system) = init_execute_test(case.cputype); + + let init_state = build_state(&case.init); + let mut expected_state = build_state(&case.fini); + system.get_bus().write_beu32(MEM_ADDR as Address, case.init.mem).unwrap(); + + load_memory(&system, case.data); + cpu.state = init_state; + + cpu.decode_next().unwrap(); + assert_eq!(cpu.decoder.instruction, case.ins); + + cpu.execute_current().unwrap(); + expected_state.request = cpu.state.request.clone(); + assert_eq!(cpu.state, expected_state); + + let mem = system.get_bus().read_beu32(MEM_ADDR as Address).unwrap(); + assert_eq!(mem, case.fini.mem); +} + +#[test] +pub fn run_execute_tests() { + for case in TEST_CASES { + println!("Running test {}", case.name); + run_test(case); + } +} + +#[test] +pub fn run_assembler_tests() { + use moa_m68k::assembler::M68kAssembler; + + let mut tests = 0; + let mut errors = 0; + + for case in TEST_CASES { + tests += 1; + let assembly_text = format!("{}", case.ins); + print!("Testing assembling of {:?} ", assembly_text); + let mut assembler = M68kAssembler::new(M68kType::MC68000); + match assembler.assemble_words(&assembly_text) { + Ok(data) => { + if data == case.data { + print!("pass"); + } else { + errors += 1; + print!("FAILED"); + print!("\ngot: [{}], but expected: [{}]", format_hex(&data), format_hex(case.data)); + } + println!(); + }, + Err(err) => { + println!("FAILED\n{:?}", err); + errors += 1; + }, + } + } + + if errors > 0 { + panic!("{} errors out of {} tests", errors, tests); + } +} + +fn format_hex(data: &[u16]) -> String { + data.iter() + .map(|word| format!("{:#06x}", word)) + .collect::>() + .join(", ") +} + +const TEST_CASES: &'static [TestCase] = &[ + TestCase { + name: "nop", + ins: Instruction::NOP, + data: &[ 0x4e71 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "addi with no overflow or carry", + ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0600, 0x007F ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007f, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "addi with no overflow but negative", + ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0600, 0x0080 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "addi with overflow", + ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0600, 0x007F ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, + }, + TestCase { + name: "addi with carry", + ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0600, 0x0080 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2717, mem: 0x00000000 }, + }, + TestCase { + name: "adda immediate", + ins: Instruction::ADDA(Target::Immediate(0xF800), 0, Size::Word), + data: &[ 0xD0FC, 0xF800 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + }, + TestCase { + name: "adda register", + ins: Instruction::ADDA(Target::DirectDReg(0), 0, Size::Word), + data: &[ 0xD0C0 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + }, + TestCase { + name: "addx", + ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0xD101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FE, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, + }, + TestCase { + name: "addx with extend", + ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0xD101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 }, + }, + TestCase { + name: "addx with extend and carry", + ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0xD101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, + }, + TestCase { + name: "andi with sr", + ins: Instruction::ANDtoSR(0xF8FF), + data: &[ 0x027C, 0xF8FF ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7AA, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA0AA, mem: 0x00000000 }, + }, + TestCase { + name: "asl", + ins: Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE300 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "asr", + ins: Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), + data: &[ 0xE200 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000C0, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, + }, + TestCase { + name: "blt with jump", + ins: Instruction::Bcc(Condition::LessThan, 8), + data: &[ 0x6D08 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, + fini: TestState { pc: 0x0000000A, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, + }, + TestCase { + name: "blt with jump", + ins: Instruction::Bcc(Condition::LessThan, 8), + data: &[ 0x6D08 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "bchg not zero", + ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long), + data: &[ 0x0841, 0x0007 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x000000FF, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "bchg zero", + ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long), + data: &[ 0x0841, 0x0007 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000080, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 }, + }, + TestCase { + name: "bra 8-bit", + ins: Instruction::BRA(-32), + data: &[ 0x60E0 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0xFFFFFFE2, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi equal", + ins: Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x0020 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi greater than", + ins: Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x0030 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi less than", + ins: Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x0010 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi no overflow", + ins: Instruction::CMP(Target::Immediate(0x7F), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x007F ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi no overflow, already negative", + ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word), + data: &[ 0x0C40, 0x8001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi with overflow", + ins: Instruction::CMP(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x0080 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi with overflow 2", + ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word), + data: &[ 0x0C40, 0x8001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi no carry", + ins: Instruction::CMP(Target::Immediate(0x01), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "cmpi with carry", + ins: Instruction::CMP(Target::Immediate(0xFF), Target::DirectDReg(0), Size::Byte), + data: &[ 0x0C00, 0x00FF ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, + }, + TestCase { + name: "divu", + ins: Instruction::DIVW(Target::Immediate(0x0245), 0, Sign::Unsigned), + data: &[ 0x80FC, 0x0245 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00040000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x007101C3, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "divs", + ins: Instruction::DIVW(Target::Immediate(48), 0, Sign::Signed), + data: &[ 0x81FC, 0x0030 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFEB00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF90, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "eori", + ins: Instruction::EOR(Target::DirectDReg(1), Target::DirectDReg(0), Size::Long), + data: &[ 0xB380 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAAAA5555, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFF0000FF, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "exg", + ins: Instruction::EXG(Target::DirectDReg(0), Target::DirectAReg(1)), + data: &[ 0xC189 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x12345678, d1: 0x00000000, a0: 0x00000000, a1: 0x87654321, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x87654321, d1: 0x00000000, a0: 0x00000000, a1: 0x12345678, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "ext", + ins: Instruction::EXT(0, Size::Byte, Size::Word), + data: &[ 0x4880 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FFCB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F8, mem: 0x00000000 }, + }, + TestCase { + name: "ext", + ins: Instruction::EXT(0, Size::Word, Size::Long), + data: &[ 0x48C0 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F0, mem: 0x00000000 }, + }, + + TestCase { + name: "lsl", + ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE308 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x271F, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "lsl with bit out", + ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE308 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 }, + }, + TestCase { + name: "lsr", + ins: Instruction::LSd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), + data: &[ 0xE208 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000040, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 }, + }, + + TestCase { + name: "muls", + ins: Instruction::MULW(Target::Immediate(0x0276), 0, Sign::Signed), + data: &[ 0xC1FC, 0x0276 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000200, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0004ec00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "movel", + ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(1), Size::Long), + data: &[ 0x2200 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0xFEDCBA98, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "movea", + ins: Instruction::MOVEA(Target::DirectDReg(0), 0, Size::Long), + data: &[ 0x2040 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0xFEDCBA98, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + }, + + // MOVEM + TestCase { + name: "movem word to target", + ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Word, Direction::ToTarget, 0x0003), + data: &[ 0x4890, 0x0003 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x12345678 }, + }, + TestCase { + name: "movem long to target", + ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::ToTarget, 0x0001), + data: &[ 0x48D0, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + }, + TestCase { + name: "movem long from target", + ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::FromTarget, 0x0001), + data: &[ 0x4CD0, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + }, + TestCase { + name: "movem word from target inc", + ins: Instruction::MOVEM(Target::IndirectARegInc(0), Size::Word, Direction::FromTarget, 0x0001), + data: &[ 0x4C98, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFFFFF, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFABCD, d1: 0x00000000, a0: MEM_ADDR+2, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + }, + TestCase { + name: "movem long to target dec", + ins: Instruction::MOVEM(Target::IndirectARegDec(0), Size::Long, Direction::ToTarget, 0x8000), + data: &[ 0x48E0, 0x8000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR+4, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 }, + }, + + + // MOVEP + TestCase { + name: "movep word to even memory", + ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::ToTarget), + data: &[ 0x0188, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, + }, + TestCase { + name: "movep word to odd memory", + ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::ToTarget), + data: &[ 0x0188, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, + }, + TestCase { + name: "movep long to even memory upper", + ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget), + data: &[ 0x01C8, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, + }, + TestCase { + name: "movep long to even memory lower", + ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget), + data: &[ 0x01C8, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, + }, + TestCase { + name: "movep word from even memory", + ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::FromTarget), + data: &[ 0x0108, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF }, + }, + TestCase { + name: "movep word from odd memory", + ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::FromTarget), + data: &[ 0x0108, 0x0001 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA }, + }, + TestCase { + name: "movep long from even memory upper", + ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget), + data: &[ 0x0148, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABB0000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF }, + }, + TestCase { + name: "movep long from even memory lower", + ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget), + data: &[ 0x0148, 0x0000 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000CCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF }, + }, + + + // NEG + TestCase { + name: "neg", + ins: Instruction::NEG(Target::DirectDReg(0), Size::Word), + data: &[ 0x4440 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF80, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, + }, + + + TestCase { + name: "ori", + ins: Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte), + data: &[ 0x0008, 0x00FF ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x000000FF, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "ori with sr", + ins: Instruction::ORtoSR(0x00AA), + data: &[ 0x007C, 0x00AA ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA755, mem: 0x00000000 }, + fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7FF, mem: 0x00000000 }, + }, + + + + TestCase { + name: "rol", + ins: Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE318 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 }, + }, + TestCase { + name: "ror", + ins: Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), + data: &[ 0xE218 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 }, + }, + TestCase { + name: "roxl", + ins: Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE310 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, + }, + TestCase { + name: "roxr", + ins: Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), + data: &[ 0xE210 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 }, + }, + TestCase { + name: "roxl two bits", + ins: Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left), + data: &[ 0xE510 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + }, + TestCase { + name: "roxr two bits", + ins: Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right), + data: &[ 0xE410 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + + TestCase { + name: "subx", + ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0x9101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 }, + }, + TestCase { + name: "subx with extend", + ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0x9101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2702, mem: 0x00000000 }, + }, + TestCase { + name: "subx with extend and carry", + ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte), + data: &[ 0x9101 ], + cputype: M68kType::MC68010, + init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 }, + fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 }, + }, +]; + diff --git a/emulator/cpus/m68k/tests/musashi_timing_tests.rs b/emulator/cpus/m68k/tests/musashi_timing_tests.rs new file mode 100644 index 0000000..3674ecf --- /dev/null +++ b/emulator/cpus/m68k/tests/musashi_timing_tests.rs @@ -0,0 +1,1628 @@ + +use moa_core::{System, Error, MemoryBlock, BusPort, Address, Addressable, wrap_transmutable}; + +use moa_m68k::{M68k, M68kType}; +use moa_m68k::instructions::{Instruction, Target, Size, Sign, Condition, XRegister, BaseRegister, IndexRegister, Direction, ShiftDirection}; +use moa_m68k::timing::M68kInstructionTiming; + + +const INIT_STACK: Address = 0x00002000; +const INIT_ADDR: Address = 0x00000010; + +fn init_decode_test(cputype: M68kType) -> (M68k, System) { + let mut system = System::default(); + + // Insert basic initialization + let data = vec![0; 0x00100000]; + let mem = MemoryBlock::new(data); + system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap(); + system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap(); + system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap(); + + // Initialize the CPU and make sure it's in the expected state + let port = if cputype <= M68kType::MC68010 { + BusPort::new(0, 24, 16, system.bus.clone()) + } else { + BusPort::new(0, 24, 16, system.bus.clone()) + }; + let mut cpu = M68k::new(cputype, 10_000_000, port); + cpu.init().unwrap(); + assert_eq!(cpu.state.pc, INIT_ADDR as u32); + assert_eq!(cpu.state.ssp, INIT_STACK as u32); + + cpu.decoder.init(INIT_ADDR as u32); + assert_eq!(cpu.decoder.start, INIT_ADDR as u32); + assert_eq!(cpu.decoder.instruction, Instruction::NOP); + (cpu, system) +} + +fn load_memory(system: &System, data: &[u16]) { + let mut addr = INIT_ADDR; + for word in data { + system.get_bus().write_beu16(addr, *word).unwrap(); + addr += 2; + } +} + +fn run_timing_test(case: &TimingCase) -> Result<(), Error> { + let (mut cpu, system) = init_decode_test(case.cpu); + let mut timing = M68kInstructionTiming::new(case.cpu, 16); + + load_memory(&system, case.data); + cpu.decode_next().unwrap(); + assert_eq!(cpu.decoder.instruction, case.ins.clone()); + + timing.add_instruction(&cpu.decoder.instruction); + let result = timing.calculate_clocks(false, 1); + let expected = match case.cpu { + M68kType::MC68000 => case.timing.0, + M68kType::MC68010 => case.timing.1, + _ => case.timing.2, + }; + + //assert_eq!(expected, result); + if expected == result { + Ok(()) + } else { + println!("{:?}", timing); + Err(Error::new(&format!("expected {} but found {}", expected, result))) + } +} + +#[test] +pub fn run_timing_tests() { + let mut errors = 0; + for case in TIMING_TESTS { + // NOTE switched to only show the failures rather than all tests + //print!("Testing for {:?}...", case.ins); + //match run_timing_test(case) { + // Ok(()) => println!("ok"), + // Err(err) => { println!("{}", err.msg); errors += 1 }, + //} + + if let Err(_) = run_timing_test(case) { + errors += 1; + } + } + + if errors > 0 { + panic!("{} errors", errors); + } +} + +pub struct TimingCase { + pub cpu: M68kType, + pub data: &'static [u16], + pub timing: (u16, u16, u16), + pub ins: Instruction, +} + +pub const TIMING_TESTS: &'static [TimingCase] = &[ + TimingCase { cpu: M68kType::MC68000, data: &[0xA000], timing: ( 4, 4, 4), ins: Instruction::UnimplementedA(0xA000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xF000], timing: ( 4, 4, 4), ins: Instruction::UnimplementedF(0xF000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC108], timing: ( 18, 18, 16), ins: Instruction::ABCD(Target::IndirectARegDec(0), Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC100], timing: ( 6, 6, 4), ins: Instruction::ABCD(Target::DirectDReg(0), Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD010], timing: ( 8, 8, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD039], timing: ( 16, 16, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD038], timing: ( 12, 12, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD000], timing: ( 4, 4, 2), ins: Instruction::ADD(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD028], timing: ( 12, 12, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD03C], timing: ( 10, 8, 4), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD030], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD03A], timing: ( 12, 12, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD03B], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD020], timing: ( 10, 10, 7), ins: Instruction::ADD(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD018], timing: ( 8, 8, 6), ins: Instruction::ADD(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD110], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD139], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD138], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD128], timing: ( 16, 16, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD130], timing: ( 18, 18, 11), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD120], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD118], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD048], timing: ( 4, 4, 2), ins: Instruction::ADD(Target::DirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD050], timing: ( 8, 8, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD079], timing: ( 16, 16, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD078], timing: ( 12, 12, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD040], timing: ( 4, 4, 2), ins: Instruction::ADD(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD068], timing: ( 12, 12, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD07C], timing: ( 10, 8, 4), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD070], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD07A], timing: ( 12, 12, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD07B], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD060], timing: ( 10, 10, 7), ins: Instruction::ADD(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD058], timing: ( 8, 8, 6), ins: Instruction::ADD(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD150], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD179], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD178], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD168], timing: ( 16, 16, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD170], timing: ( 18, 18, 11), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD160], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD158], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD088], timing: ( 6, 6, 2), ins: Instruction::ADD(Target::DirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD090], timing: ( 14, 14, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0B9], timing: ( 22, 22, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0B8], timing: ( 18, 18, 6), ins: Instruction::ADD(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD080], timing: ( 6, 6, 2), ins: Instruction::ADD(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0A8], timing: ( 18, 18, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0BC], timing: ( 16, 14, 6), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0B0], timing: ( 20, 20, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0BA], timing: ( 18, 18, 7), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0BB], timing: ( 20, 20, 9), ins: Instruction::ADD(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0A0], timing: ( 16, 16, 7), ins: Instruction::ADD(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD098], timing: ( 14, 14, 6), ins: Instruction::ADD(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD190], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1B9], timing: ( 28, 28, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1B8], timing: ( 24, 24, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1A8], timing: ( 24, 24, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1B0], timing: ( 26, 26, 11), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1A0], timing: ( 22, 22, 9), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD198], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0C8], timing: ( 8, 8, 2), ins: Instruction::ADDA(Target::DirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0D0], timing: ( 12, 12, 6), ins: Instruction::ADDA(Target::IndirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0F9], timing: ( 20, 20, 6), ins: Instruction::ADDA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0F8], timing: ( 16, 16, 6), ins: Instruction::ADDA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0C0], timing: ( 8, 8, 2), ins: Instruction::ADDA(Target::DirectDReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0E8], timing: ( 16, 16, 7), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0FC], timing: ( 14, 12, 4), ins: Instruction::ADDA(Target::Immediate(00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0F0], timing: ( 18, 18, 9), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0FA], timing: ( 16, 16, 7), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0FB], timing: ( 18, 18, 9), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0E0], timing: ( 14, 14, 7), ins: Instruction::ADDA(Target::IndirectARegDec(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD0D8], timing: ( 12, 12, 6), ins: Instruction::ADDA(Target::IndirectARegInc(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1C8], timing: ( 6, 6, 2), ins: Instruction::ADDA(Target::DirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1D0], timing: ( 14, 14, 6), ins: Instruction::ADDA(Target::IndirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1F9], timing: ( 22, 22, 6), ins: Instruction::ADDA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1F8], timing: ( 18, 18, 6), ins: Instruction::ADDA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1C0], timing: ( 6, 6, 2), ins: Instruction::ADDA(Target::DirectDReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1E8], timing: ( 18, 18, 7), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1FC], timing: ( 16, 14, 6), ins: Instruction::ADDA(Target::Immediate(00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1F0], timing: ( 20, 20, 9), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1FA], timing: ( 18, 18, 7), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1FB], timing: ( 20, 20, 9), ins: Instruction::ADDA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1E0], timing: ( 16, 16, 7), ins: Instruction::ADDA(Target::IndirectARegDec(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD1D8], timing: ( 14, 14, 6), ins: Instruction::ADDA(Target::IndirectARegInc(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0610], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0639], timing: ( 24, 24, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0638], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0600], timing: ( 8, 8, 2), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0628], timing: ( 20, 20, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0630], timing: ( 22, 22, 11), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0620], timing: ( 18, 18, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0618], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0650], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0679], timing: ( 24, 24, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0678], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0640], timing: ( 8, 8, 2), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0668], timing: ( 20, 20, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0670], timing: ( 22, 22, 11), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0660], timing: ( 18, 18, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0658], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0690], timing: ( 28, 28, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x06B9], timing: ( 36, 36, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x06B8], timing: ( 32, 32, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0680], timing: ( 16, 14, 2), ins: Instruction::ADD(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x06A8], timing: ( 32, 32, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x06B0], timing: ( 34, 34, 11), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x06A0], timing: ( 30, 30, 9), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0698], timing: ( 28, 28, 8), ins: Instruction::ADD(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5010], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5039], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5038], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5000], timing: ( 4, 4, 2), ins: Instruction::ADD(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5028], timing: ( 16, 16, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5030], timing: ( 18, 18, 11), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5020], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5018], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5048], timing: ( 4, 4, 2), ins: Instruction::ADDA(Target::Immediate(00000008), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5050], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5079], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5078], timing: ( 16, 16, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5040], timing: ( 4, 4, 2), ins: Instruction::ADD(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5068], timing: ( 16, 16, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5070], timing: ( 18, 18, 11), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5060], timing: ( 14, 14, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5058], timing: ( 12, 12, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5088], timing: ( 8, 8, 2), ins: Instruction::ADDA(Target::Immediate(00000008), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5090], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50B9], timing: ( 28, 28, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50B8], timing: ( 24, 24, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5080], timing: ( 8, 8, 2), ins: Instruction::ADD(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50A8], timing: ( 24, 24, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50B0], timing: ( 26, 26, 11), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50A0], timing: ( 22, 22, 9), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5098], timing: ( 20, 20, 8), ins: Instruction::ADD(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD108], timing: ( 18, 18, 12), ins: Instruction::ADDX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD100], timing: ( 4, 4, 2), ins: Instruction::ADDX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD148], timing: ( 18, 18, 12), ins: Instruction::ADDX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD140], timing: ( 4, 4, 2), ins: Instruction::ADDX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD188], timing: ( 30, 30, 12), ins: Instruction::ADDX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xD180], timing: ( 8, 6, 2), ins: Instruction::ADDX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC010], timing: ( 8, 8, 6), ins: Instruction::AND(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC039], timing: ( 16, 16, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC038], timing: ( 12, 12, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC000], timing: ( 4, 4, 2), ins: Instruction::AND(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC028], timing: ( 12, 12, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC03C], timing: ( 10, 8, 4), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC030], timing: ( 14, 14, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC03A], timing: ( 12, 12, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC03B], timing: ( 14, 14, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC020], timing: ( 10, 10, 7), ins: Instruction::AND(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC018], timing: ( 8, 8, 6), ins: Instruction::AND(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC110], timing: ( 12, 12, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC139], timing: ( 20, 20, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC138], timing: ( 16, 16, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC128], timing: ( 16, 16, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC130], timing: ( 18, 18, 11), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC120], timing: ( 14, 14, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC118], timing: ( 12, 12, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC050], timing: ( 8, 8, 6), ins: Instruction::AND(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC079], timing: ( 16, 16, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC078], timing: ( 12, 12, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC040], timing: ( 4, 4, 2), ins: Instruction::AND(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC068], timing: ( 12, 12, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC07C], timing: ( 10, 8, 4), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC070], timing: ( 14, 14, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC07A], timing: ( 12, 12, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC07B], timing: ( 14, 14, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC060], timing: ( 10, 10, 7), ins: Instruction::AND(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC058], timing: ( 8, 8, 6), ins: Instruction::AND(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC150], timing: ( 12, 12, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC179], timing: ( 20, 20, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC178], timing: ( 16, 16, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC168], timing: ( 16, 16, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC170], timing: ( 18, 18, 11), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC160], timing: ( 14, 14, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC158], timing: ( 12, 12, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC090], timing: ( 14, 14, 6), ins: Instruction::AND(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0B9], timing: ( 22, 22, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0B8], timing: ( 18, 18, 6), ins: Instruction::AND(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC080], timing: ( 6, 6, 2), ins: Instruction::AND(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0A8], timing: ( 18, 18, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0BC], timing: ( 16, 14, 6), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0B0], timing: ( 20, 20, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0BA], timing: ( 18, 18, 7), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0BB], timing: ( 20, 20, 9), ins: Instruction::AND(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0A0], timing: ( 16, 16, 7), ins: Instruction::AND(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC098], timing: ( 14, 14, 6), ins: Instruction::AND(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC190], timing: ( 20, 20, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1B9], timing: ( 28, 28, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1B8], timing: ( 24, 24, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1A8], timing: ( 24, 24, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1B0], timing: ( 26, 26, 11), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1A0], timing: ( 22, 22, 9), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC198], timing: ( 20, 20, 8), ins: Instruction::AND(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0210], timing: ( 16, 16, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0239], timing: ( 24, 24, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0238], timing: ( 20, 20, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0200], timing: ( 8, 8, 2), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0228], timing: ( 20, 20, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0230], timing: ( 22, 22, 11), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0220], timing: ( 18, 18, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0218], timing: ( 16, 16, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0250], timing: ( 16, 16, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0279], timing: ( 24, 24, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0278], timing: ( 20, 20, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0240], timing: ( 8, 8, 2), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0268], timing: ( 20, 20, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0270], timing: ( 22, 22, 11), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0260], timing: ( 18, 18, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0258], timing: ( 16, 16, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x023C], timing: ( 20, 16, 12), ins: Instruction::ANDtoCCR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x027C], timing: ( 20, 16, 12), ins: Instruction::ANDtoSR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0290], timing: ( 28, 28, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x02B9], timing: ( 36, 36, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x02B8], timing: ( 32, 32, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0280], timing: ( 14, 14, 2), ins: Instruction::AND(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x02A8], timing: ( 32, 32, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x02B0], timing: ( 34, 34, 11), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x02A0], timing: ( 30, 30, 9), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0298], timing: ( 28, 28, 8), ins: Instruction::AND(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE120], timing: ( 6, 6, 8), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE100], timing: ( 6, 6, 8), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1D0], timing: ( 12, 12, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1F9], timing: ( 20, 20, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1F8], timing: ( 16, 16, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1E8], timing: ( 16, 16, 11), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1F0], timing: ( 18, 18, 13), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1E0], timing: ( 14, 14, 11), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1D8], timing: ( 12, 12, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE160], timing: ( 6, 6, 8), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE140], timing: ( 6, 6, 8), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1A0], timing: ( 8, 8, 8), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE180], timing: ( 8, 8, 8), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE020], timing: ( 6, 6, 6), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE000], timing: ( 6, 6, 6), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0D0], timing: ( 12, 12, 9), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0F9], timing: ( 20, 20, 9), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0F8], timing: ( 16, 16, 9), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0E8], timing: ( 16, 16, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0F0], timing: ( 18, 18, 12), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0E0], timing: ( 14, 14, 10), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0D8], timing: ( 12, 12, 9), ins: Instruction::ASd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE060], timing: ( 6, 6, 6), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE040], timing: ( 6, 6, 6), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0A0], timing: ( 8, 8, 6), ins: Instruction::ASd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE080], timing: ( 8, 8, 6), ins: Instruction::ASd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6400], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::CarryClear, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6400], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::CarryClear, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0150], timing: ( 12, 12, 8), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0179], timing: ( 20, 20, 8), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0178], timing: ( 16, 16, 8), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0168], timing: ( 16, 16, 9), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0170], timing: ( 18, 18, 11), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0160], timing: ( 14, 14, 9), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0158], timing: ( 12, 12, 8), ins: Instruction::BCHG(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0850], timing: ( 16, 16, 8), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0879], timing: ( 24, 24, 8), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0878], timing: ( 20, 20, 8), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0868], timing: ( 20, 20, 9), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0870], timing: ( 22, 22, 11), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0860], timing: ( 18, 18, 9), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0858], timing: ( 16, 16, 8), ins: Instruction::BCHG(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0140], timing: ( 8, 8, 4), ins: Instruction::BCHG(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0840], timing: ( 12, 12, 4), ins: Instruction::BCHG(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0190], timing: ( 12, 14, 8), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01B9], timing: ( 20, 22, 8), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01B8], timing: ( 16, 18, 8), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01A8], timing: ( 16, 18, 9), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01B0], timing: ( 18, 20, 11), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01A0], timing: ( 14, 16, 9), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0198], timing: ( 12, 14, 8), ins: Instruction::BCLR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0890], timing: ( 16, 16, 8), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08B9], timing: ( 24, 24, 8), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08B8], timing: ( 20, 20, 8), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08A8], timing: ( 20, 20, 9), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08B0], timing: ( 22, 22, 11), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08A0], timing: ( 18, 18, 9), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0898], timing: ( 16, 16, 8), ins: Instruction::BCLR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0180], timing: ( 10, 10, 4), ins: Instruction::BCLR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0880], timing: ( 14, 14, 4), ins: Instruction::BCLR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6500], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::CarrySet, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6500], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::CarrySet, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6700], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::Equal, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6700], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::Equal, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6C00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::GreaterThanOrEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6C00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::GreaterThanOrEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6E00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::GreaterThan, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6E00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::GreaterThan, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6200], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::High, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6200], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::High, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6F00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::LessThanOrEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6F00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::LessThanOrEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6300], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::LowOrSame, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6300], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::LowOrSame, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6D00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::LessThan, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6D00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::LessThan, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6B00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::Minus, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6B00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::Minus, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6600], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::NotEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6600], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::NotEqual, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6A00], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::Plus, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6A00], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::Plus, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6000], timing: ( 10, 10, 10), ins: Instruction::BRA(0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6000], timing: ( 10, 10, 10), ins: Instruction::BRA(0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01D0], timing: ( 12, 12, 8), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01F9], timing: ( 20, 20, 8), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01F8], timing: ( 16, 16, 8), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01E8], timing: ( 16, 16, 9), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01F0], timing: ( 18, 18, 11), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01E0], timing: ( 14, 14, 9), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01D8], timing: ( 12, 12, 8), ins: Instruction::BSET(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08D0], timing: ( 16, 16, 8), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08F9], timing: ( 24, 24, 8), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08F8], timing: ( 20, 20, 8), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08E8], timing: ( 20, 20, 9), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08F0], timing: ( 22, 22, 11), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08E0], timing: ( 18, 18, 9), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08D8], timing: ( 16, 16, 8), ins: Instruction::BSET(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01C0], timing: ( 8, 8, 4), ins: Instruction::BSET(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x08C0], timing: ( 12, 12, 4), ins: Instruction::BSET(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6100], timing: ( 18, 18, 7), ins: Instruction::BSR(0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0110], timing: ( 8, 8, 8), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0139], timing: ( 16, 16, 8), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0138], timing: ( 12, 12, 8), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0128], timing: ( 12, 12, 9), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x013C], timing: ( 8, 8, 6), ins: Instruction::BTST(Target::DirectDReg(0), Target::Immediate(00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0130], timing: ( 14, 14, 11), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x013A], timing: ( 12, 12, 9), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x013B], timing: ( 14, 14, 11), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0120], timing: ( 10, 10, 9), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0118], timing: ( 8, 8, 8), ins: Instruction::BTST(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0810], timing: ( 12, 12, 8), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0839], timing: ( 20, 20, 8), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0838], timing: ( 16, 16, 8), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0828], timing: ( 16, 16, 9), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0830], timing: ( 18, 18, 11), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x083A], timing: ( 16, 16, 9), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x083B], timing: ( 18, 18, 11), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0820], timing: ( 14, 14, 9), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0818], timing: ( 12, 12, 8), ins: Instruction::BTST(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0100], timing: ( 6, 6, 4), ins: Instruction::BTST(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0800], timing: ( 10, 10, 4), ins: Instruction::BTST(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6800], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::OverflowClear, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6800], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::OverflowClear, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6900], timing: ( 8, 8, 6), ins: Instruction::Bcc(Condition::OverflowSet, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x6900], timing: ( 10, 10, 6), ins: Instruction::Bcc(Condition::OverflowSet, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4190], timing: ( 14, 12, 12), ins: Instruction::CHK(Target::IndirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41B9], timing: ( 22, 20, 12), ins: Instruction::CHK(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41B8], timing: ( 18, 16, 12), ins: Instruction::CHK(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4180], timing: ( 10, 8, 8), ins: Instruction::CHK(Target::DirectDReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41A8], timing: ( 18, 16, 13), ins: Instruction::CHK(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41BC], timing: ( 14, 12, 10), ins: Instruction::CHK(Target::Immediate(00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41B0], timing: ( 20, 18, 15), ins: Instruction::CHK(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41BA], timing: ( 18, 16, 13), ins: Instruction::CHK(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41BB], timing: ( 20, 18, 15), ins: Instruction::CHK(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41A0], timing: ( 16, 14, 13), ins: Instruction::CHK(Target::IndirectARegDec(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4198], timing: ( 14, 12, 12), ins: Instruction::CHK(Target::IndirectARegInc(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4210], timing: ( 12, 8, 8), ins: Instruction::CLR(Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4239], timing: ( 20, 14, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4238], timing: ( 16, 12, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4200], timing: ( 4, 4, 2), ins: Instruction::CLR(Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4228], timing: ( 16, 12, 9), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4230], timing: ( 18, 14, 11), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4220], timing: ( 14, 10, 9), ins: Instruction::CLR(Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4218], timing: ( 12, 8, 8), ins: Instruction::CLR(Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4250], timing: ( 12, 8, 8), ins: Instruction::CLR(Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4279], timing: ( 20, 14, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4278], timing: ( 16, 12, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4240], timing: ( 4, 4, 2), ins: Instruction::CLR(Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4268], timing: ( 16, 12, 9), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4270], timing: ( 18, 14, 11), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4260], timing: ( 14, 10, 9), ins: Instruction::CLR(Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4258], timing: ( 12, 8, 8), ins: Instruction::CLR(Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4290], timing: ( 20, 12, 8), ins: Instruction::CLR(Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x42B9], timing: ( 28, 20, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x42B8], timing: ( 24, 16, 8), ins: Instruction::CLR(Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4280], timing: ( 6, 6, 2), ins: Instruction::CLR(Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x42A8], timing: ( 24, 16, 9), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x42B0], timing: ( 26, 20, 11), ins: Instruction::CLR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x42A0], timing: ( 22, 14, 9), ins: Instruction::CLR(Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4298], timing: ( 20, 12, 8), ins: Instruction::CLR(Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB010], timing: ( 8, 8, 6), ins: Instruction::CMP(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB039], timing: ( 16, 16, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB038], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB000], timing: ( 4, 4, 2), ins: Instruction::CMP(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB028], timing: ( 12, 12, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB03C], timing: ( 8, 8, 4), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB030], timing: ( 14, 14, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB03A], timing: ( 12, 12, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB03B], timing: ( 14, 14, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB020], timing: ( 10, 10, 7), ins: Instruction::CMP(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB018], timing: ( 8, 8, 6), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB048], timing: ( 4, 4, 2), ins: Instruction::CMP(Target::DirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB050], timing: ( 8, 8, 6), ins: Instruction::CMP(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB079], timing: ( 16, 16, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB078], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB040], timing: ( 4, 4, 2), ins: Instruction::CMP(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB068], timing: ( 12, 12, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB07C], timing: ( 8, 8, 4), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB070], timing: ( 14, 14, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB07A], timing: ( 12, 12, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB07B], timing: ( 14, 14, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB060], timing: ( 10, 10, 7), ins: Instruction::CMP(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB058], timing: ( 8, 8, 6), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB088], timing: ( 6, 6, 2), ins: Instruction::CMP(Target::DirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB090], timing: ( 14, 14, 6), ins: Instruction::CMP(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0B9], timing: ( 22, 22, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0B8], timing: ( 18, 18, 6), ins: Instruction::CMP(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB080], timing: ( 6, 6, 2), ins: Instruction::CMP(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0A8], timing: ( 18, 18, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0BC], timing: ( 14, 14, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0B0], timing: ( 20, 20, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0BA], timing: ( 18, 18, 7), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0BB], timing: ( 20, 20, 9), ins: Instruction::CMP(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0A0], timing: ( 16, 16, 7), ins: Instruction::CMP(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB098], timing: ( 14, 14, 6), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0C8], timing: ( 6, 6, 4), ins: Instruction::CMPA(Target::DirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0D0], timing: ( 10, 10, 8), ins: Instruction::CMPA(Target::IndirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0F9], timing: ( 18, 18, 8), ins: Instruction::CMPA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0F8], timing: ( 14, 14, 8), ins: Instruction::CMPA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0C0], timing: ( 6, 6, 4), ins: Instruction::CMPA(Target::DirectDReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0E8], timing: ( 14, 14, 9), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0FC], timing: ( 10, 10, 6), ins: Instruction::CMPA(Target::Immediate(00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0F0], timing: ( 16, 16, 11), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0FA], timing: ( 14, 14, 9), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0FB], timing: ( 16, 16, 11), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0E0], timing: ( 12, 12, 9), ins: Instruction::CMPA(Target::IndirectARegDec(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB0D8], timing: ( 10, 10, 8), ins: Instruction::CMPA(Target::IndirectARegInc(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1C8], timing: ( 6, 6, 4), ins: Instruction::CMPA(Target::DirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1D0], timing: ( 14, 14, 8), ins: Instruction::CMPA(Target::IndirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1F9], timing: ( 22, 22, 8), ins: Instruction::CMPA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1F8], timing: ( 18, 18, 8), ins: Instruction::CMPA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1C0], timing: ( 6, 6, 4), ins: Instruction::CMPA(Target::DirectDReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1E8], timing: ( 18, 18, 9), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1FC], timing: ( 14, 14, 8), ins: Instruction::CMPA(Target::Immediate(00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1F0], timing: ( 20, 20, 11), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1FA], timing: ( 18, 18, 9), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1FB], timing: ( 20, 20, 11), ins: Instruction::CMPA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1E0], timing: ( 16, 16, 9), ins: Instruction::CMPA(Target::IndirectARegDec(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1D8], timing: ( 14, 14, 8), ins: Instruction::CMPA(Target::IndirectARegInc(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C10], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C39], timing: ( 20, 20, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C38], timing: ( 16, 16, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C00], timing: ( 8, 8, 2), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C28], timing: ( 16, 16, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C30], timing: ( 18, 18, 9), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C20], timing: ( 14, 14, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C18], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C50], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C79], timing: ( 20, 20, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C78], timing: ( 16, 16, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C40], timing: ( 8, 8, 2), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C68], timing: ( 16, 16, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C70], timing: ( 18, 18, 9), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C60], timing: ( 14, 14, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C58], timing: ( 12, 12, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C90], timing: ( 20, 20, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0CB9], timing: ( 28, 28, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0CB8], timing: ( 24, 24, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C80], timing: ( 14, 12, 2), ins: Instruction::CMP(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0CA8], timing: ( 24, 24, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0CB0], timing: ( 26, 26, 9), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0CA0], timing: ( 22, 22, 7), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0C98], timing: ( 20, 20, 6), ins: Instruction::CMP(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB108], timing: ( 12, 12, 9), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB148], timing: ( 12, 12, 9), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB188], timing: ( 20, 20, 9), ins: Instruction::CMP(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::CarryClear, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::CarrySet, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::Equal, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51C8], timing: ( 14, 14, 6), ins: Instruction::DBcc(Condition::False, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::GreaterThanOrEqual, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::GreaterThan, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::High, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::LessThanOrEqual, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::LowOrSame, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::LessThan, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::Minus, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::NotEqual, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AC8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::Plus, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::True, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::OverflowClear, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59C8], timing: ( 12, 12, 6), ins: Instruction::DBcc(Condition::OverflowSet, 0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81D0], timing: (162, 126, 60), ins: Instruction::DIVW(Target::IndirectAReg(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81F9], timing: (170, 134, 60), ins: Instruction::DIVW(Target::IndirectMemory(0x00000000, Size::Long), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81F8], timing: (166, 130, 60), ins: Instruction::DIVW(Target::IndirectMemory(0x00000000, Size::Word), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81C0], timing: (158, 122, 56), ins: Instruction::DIVW(Target::DirectDReg(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81E8], timing: (166, 130, 61), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81FC], timing: (162, 126, 58), ins: Instruction::DIVW(Target::Immediate(00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81F0], timing: (168, 132, 63), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81FA], timing: (166, 130, 61), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81FB], timing: (168, 132, 63), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81E0], timing: (164, 128, 61), ins: Instruction::DIVW(Target::IndirectARegDec(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81D8], timing: (162, 126, 60), ins: Instruction::DIVW(Target::IndirectARegInc(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80D0], timing: (144, 112, 48), ins: Instruction::DIVW(Target::IndirectAReg(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80F9], timing: (152, 120, 48), ins: Instruction::DIVW(Target::IndirectMemory(0x00000000, Size::Long), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80F8], timing: (148, 116, 48), ins: Instruction::DIVW(Target::IndirectMemory(0x00000000, Size::Word), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80C0], timing: (140, 108, 44), ins: Instruction::DIVW(Target::DirectDReg(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80E8], timing: (148, 116, 49), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80FC], timing: (144, 112, 46), ins: Instruction::DIVW(Target::Immediate(00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80F0], timing: (150, 118, 51), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80FA], timing: (148, 116, 49), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80FB], timing: (150, 118, 51), ins: Instruction::DIVW(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80E0], timing: (146, 114, 49), ins: Instruction::DIVW(Target::IndirectARegDec(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80D8], timing: (144, 112, 48), ins: Instruction::DIVW(Target::IndirectARegInc(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB110], timing: ( 12, 12, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB139], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB138], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB100], timing: ( 4, 4, 2), ins: Instruction::EOR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB128], timing: ( 16, 16, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB130], timing: ( 18, 18, 11), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB120], timing: ( 14, 14, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB118], timing: ( 12, 12, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB150], timing: ( 12, 12, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB179], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB178], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB140], timing: ( 4, 4, 2), ins: Instruction::EOR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB168], timing: ( 16, 16, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB170], timing: ( 18, 18, 11), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB160], timing: ( 14, 14, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB158], timing: ( 12, 12, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB190], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1B9], timing: ( 28, 28, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1B8], timing: ( 24, 24, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB180], timing: ( 8, 6, 2), ins: Instruction::EOR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1A8], timing: ( 24, 24, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1B0], timing: ( 26, 26, 11), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB1A0], timing: ( 22, 22, 9), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xB198], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A10], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A39], timing: ( 24, 24, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A38], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A00], timing: ( 8, 8, 2), ins: Instruction::EOR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A28], timing: ( 20, 20, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A30], timing: ( 22, 22, 11), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A20], timing: ( 18, 18, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A18], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A50], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A79], timing: ( 24, 24, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A78], timing: ( 20, 20, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A40], timing: ( 8, 8, 2), ins: Instruction::EOR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A68], timing: ( 20, 20, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A70], timing: ( 22, 22, 11), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A60], timing: ( 18, 18, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A58], timing: ( 16, 16, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A3C], timing: ( 20, 16, 12), ins: Instruction::EORtoCCR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A7C], timing: ( 20, 16, 12), ins: Instruction::EORtoSR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A90], timing: ( 28, 28, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0AB9], timing: ( 36, 36, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0AB8], timing: ( 32, 32, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A80], timing: ( 16, 14, 2), ins: Instruction::EOR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0AA8], timing: ( 32, 32, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0AB0], timing: ( 34, 34, 11), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0AA0], timing: ( 30, 30, 9), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0A98], timing: ( 28, 28, 8), ins: Instruction::EOR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC148], timing: ( 6, 6, 2), ins: Instruction::EXG(Target::DirectAReg(0), Target::DirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC188], timing: ( 6, 6, 2), ins: Instruction::EXG(Target::DirectDReg(0), Target::DirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC140], timing: ( 6, 6, 2), ins: Instruction::EXG(Target::DirectDReg(0), Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4880], timing: ( 4, 4, 4), ins: Instruction::EXT(0, Size::Byte, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48C0], timing: ( 4, 4, 4), ins: Instruction::EXT(0, Size::Word, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AFC], timing: ( 4, 4, 4), ins: Instruction::ILLEGAL }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4ED0], timing: ( 8, 8, 4), ins: Instruction::JMP(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EF9], timing: ( 12, 12, 4), ins: Instruction::JMP(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EF8], timing: ( 10, 10, 4), ins: Instruction::JMP(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EE8], timing: ( 10, 10, 5), ins: Instruction::JMP(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EF0], timing: ( 12, 12, 0), ins: Instruction::JMP(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EFA], timing: ( 10, 10, 5), ins: Instruction::JMP(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EFB], timing: ( 14, 14, 7), ins: Instruction::JMP(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E90], timing: ( 16, 16, 4), ins: Instruction::JSR(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EB9], timing: ( 20, 20, 4), ins: Instruction::JSR(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EB8], timing: ( 18, 18, 4), ins: Instruction::JSR(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EA8], timing: ( 18, 18, 5), ins: Instruction::JSR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EB0], timing: ( 22, 22, 7), ins: Instruction::JSR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EBA], timing: ( 18, 18, 5), ins: Instruction::JSR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4EBB], timing: ( 22, 22, 7), ins: Instruction::JSR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41D0], timing: ( 4, 4, 6), ins: Instruction::LEA(Target::IndirectAReg(0), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41F9], timing: ( 12, 12, 6), ins: Instruction::LEA(Target::IndirectMemory(0x00000000, Size::Long), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41F8], timing: ( 8, 8, 6), ins: Instruction::LEA(Target::IndirectMemory(0x00000000, Size::Word), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41E8], timing: ( 8, 8, 7), ins: Instruction::LEA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41F0], timing: ( 12, 12, 9), ins: Instruction::LEA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41FA], timing: ( 8, 8, 7), ins: Instruction::LEA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x41FB], timing: ( 12, 12, 9), ins: Instruction::LEA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E50], timing: ( 16, 16, 5), ins: Instruction::LINK(0, 0x00000000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE128], timing: ( 6, 6, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE108], timing: ( 6, 6, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3D0], timing: ( 12, 12, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3F9], timing: ( 20, 20, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3F8], timing: ( 16, 16, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3E8], timing: ( 16, 16, 10), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3F0], timing: ( 18, 18, 12), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3E0], timing: ( 14, 14, 10), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE3D8], timing: ( 12, 12, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE168], timing: ( 6, 6, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE148], timing: ( 6, 6, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1A8], timing: ( 8, 8, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE188], timing: ( 8, 8, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE028], timing: ( 6, 6, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE008], timing: ( 6, 6, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2D0], timing: ( 12, 12, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2F9], timing: ( 20, 20, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2F8], timing: ( 16, 16, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2E8], timing: ( 16, 16, 10), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2F0], timing: ( 18, 18, 12), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2E0], timing: ( 14, 14, 10), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE2D8], timing: ( 12, 12, 9), ins: Instruction::LSd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE068], timing: ( 6, 6, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE048], timing: ( 6, 6, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0A8], timing: ( 8, 8, 6), ins: Instruction::LSd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE088], timing: ( 8, 8, 4), ins: Instruction::LSd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1090], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10B9], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10B8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1080], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10A8], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10BC], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10B0], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10BA], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10BB], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10A0], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1098], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13D0], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13F9], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13F8], timing: ( 24, 24, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13C0], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13E8], timing: ( 24, 24, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13FC], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13F0], timing: ( 26, 26, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13FA], timing: ( 24, 24, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13FB], timing: ( 26, 26, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13E0], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x13D8], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11D0], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11F9], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11F8], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11C0], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11E8], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11FC], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11F0], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11FA], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11FB], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11E0], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11D8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1010], timing: ( 8, 8, 6), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1039], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1038], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1000], timing: ( 4, 4, 2), ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1028], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x103C], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1030], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x103A], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x103B], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1020], timing: ( 10, 10, 7), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1018], timing: ( 8, 8, 6), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1150], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1179], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1178], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1140], timing: ( 12, 12, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1168], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x117C], timing: ( 16, 16, 7), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1170], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x117A], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x117B], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1160], timing: ( 18, 18, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1158], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1190], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11B9], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11B8], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1180], timing: ( 14, 14, 7), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11A8], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11BC], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11B0], timing: ( 24, 24, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11BA], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11BB], timing: ( 24, 24, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x11A0], timing: ( 20, 20, 12), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1198], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1110], timing: ( 12, 12, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1139], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1138], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1100], timing: ( 8, 8, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1128], timing: ( 16, 16, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x113C], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1130], timing: ( 18, 18, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x113A], timing: ( 16, 16, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x113B], timing: ( 18, 18, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1120], timing: ( 14, 14, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x1118], timing: ( 12, 12, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10D0], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10F9], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10F8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10C0], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10E8], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10FC], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10F0], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10FA], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10FB], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10E0], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x10D8], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3088], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3090], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30B9], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30B8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3080], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30A8], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30BC], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30B0], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30BA], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30BB], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30A0], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3098], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33C8], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33D0], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33F9], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33F8], timing: ( 24, 24, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33C0], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33E8], timing: ( 24, 24, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33FC], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33F0], timing: ( 26, 26, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33FA], timing: ( 24, 24, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33FB], timing: ( 26, 26, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33E0], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x33D8], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31C8], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31D0], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31F9], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31F8], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31C0], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31E8], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31FC], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31F0], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31FA], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31FB], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31E0], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31D8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3008], timing: ( 4, 4, 2), ins: Instruction::MOVE(Target::DirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3010], timing: ( 8, 8, 6), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3039], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3038], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3000], timing: ( 4, 4, 2), ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3028], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x303C], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3030], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x303A], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x303B], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3020], timing: ( 10, 10, 7), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3018], timing: ( 8, 8, 6), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3148], timing: ( 12, 12, 5), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3150], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3179], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3178], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3140], timing: ( 12, 12, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3168], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x317C], timing: ( 16, 16, 7), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3170], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x317A], timing: ( 20, 20, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x317B], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3160], timing: ( 18, 18, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3158], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40D0], timing: ( 12, 12, 12), ins: Instruction::MOVEfromSR(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40F9], timing: ( 20, 20, 12), ins: Instruction::MOVEfromSR(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40F8], timing: ( 16, 16, 12), ins: Instruction::MOVEfromSR(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40C0], timing: ( 6, 4, 8), ins: Instruction::MOVEfromSR(Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40E8], timing: ( 16, 16, 13), ins: Instruction::MOVEfromSR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40F0], timing: ( 18, 18, 15), ins: Instruction::MOVEfromSR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40E0], timing: ( 14, 14, 13), ins: Instruction::MOVEfromSR(Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40D8], timing: ( 12, 12, 12), ins: Instruction::MOVEfromSR(Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3188], timing: ( 14, 14, 7), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3190], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31B9], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31B8], timing: ( 22, 22, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3180], timing: ( 14, 14, 7), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31A8], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31BC], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31B0], timing: ( 24, 24, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31BA], timing: ( 22, 22, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31BB], timing: ( 24, 24, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x31A0], timing: ( 20, 20, 12), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3198], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3108], timing: ( 8, 8, 5), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3110], timing: ( 12, 12, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3139], timing: ( 20, 20, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3138], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3100], timing: ( 8, 8, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3128], timing: ( 16, 16, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x313C], timing: ( 12, 12, 7), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3130], timing: ( 18, 18, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x313A], timing: ( 16, 16, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x313B], timing: ( 18, 18, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3120], timing: ( 14, 14, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3118], timing: ( 12, 12, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30C8], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30D0], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30F9], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30F8], timing: ( 16, 16, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30C0], timing: ( 8, 8, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30E8], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30FC], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30F0], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30FA], timing: ( 16, 16, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30FB], timing: ( 18, 18, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30E0], timing: ( 14, 14, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x30D8], timing: ( 12, 12, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44D0], timing: ( 16, 16, 8), ins: Instruction::MOVEtoCCR(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44F9], timing: ( 24, 24, 8), ins: Instruction::MOVEtoCCR(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44F8], timing: ( 20, 20, 8), ins: Instruction::MOVEtoCCR(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44C0], timing: ( 12, 12, 4), ins: Instruction::MOVEtoCCR(Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44E8], timing: ( 20, 20, 9), ins: Instruction::MOVEtoCCR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44FC], timing: ( 16, 16, 6), ins: Instruction::MOVEtoCCR(Target::Immediate(00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44F0], timing: ( 22, 22, 11), ins: Instruction::MOVEtoCCR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44FA], timing: ( 20, 20, 9), ins: Instruction::MOVEtoCCR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44FB], timing: ( 22, 22, 11), ins: Instruction::MOVEtoCCR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44E0], timing: ( 18, 18, 9), ins: Instruction::MOVEtoCCR(Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44D8], timing: ( 16, 16, 8), ins: Instruction::MOVEtoCCR(Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46D0], timing: ( 16, 16, 12), ins: Instruction::MOVEtoSR(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46F9], timing: ( 24, 24, 12), ins: Instruction::MOVEtoSR(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46F8], timing: ( 20, 20, 12), ins: Instruction::MOVEtoSR(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46C0], timing: ( 12, 12, 8), ins: Instruction::MOVEtoSR(Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46E8], timing: ( 20, 20, 13), ins: Instruction::MOVEtoSR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46FC], timing: ( 16, 16, 10), ins: Instruction::MOVEtoSR(Target::Immediate(00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46F0], timing: ( 22, 22, 15), ins: Instruction::MOVEtoSR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46FA], timing: ( 20, 20, 13), ins: Instruction::MOVEtoSR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46FB], timing: ( 22, 22, 15), ins: Instruction::MOVEtoSR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46E0], timing: ( 18, 18, 13), ins: Instruction::MOVEtoSR(Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46D8], timing: ( 16, 16, 12), ins: Instruction::MOVEtoSR(Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2088], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2090], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20B9], timing: ( 28, 28, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20B8], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2080], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20A8], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20BC], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20B0], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20BA], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20BB], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20A0], timing: ( 22, 22, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2098], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23C8], timing: ( 20, 20, 6), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23D0], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23F9], timing: ( 36, 36, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23F8], timing: ( 32, 32, 10), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23C0], timing: ( 20, 20, 6), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23E8], timing: ( 32, 32, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23FC], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23F0], timing: ( 34, 34, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23FA], timing: ( 32, 32, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23FB], timing: ( 34, 34, 13), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23E0], timing: ( 30, 30, 11), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x23D8], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21C8], timing: ( 16, 16, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21D0], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21F9], timing: ( 32, 32, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21F8], timing: ( 28, 28, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21C0], timing: ( 16, 16, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21E8], timing: ( 28, 28, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21FC], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21F0], timing: ( 30, 30, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21FA], timing: ( 28, 28, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21FB], timing: ( 30, 30, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21E0], timing: ( 26, 26, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21D8], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2008], timing: ( 4, 4, 2), ins: Instruction::MOVE(Target::DirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2010], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2039], timing: ( 20, 20, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2038], timing: ( 16, 16, 6), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2000], timing: ( 4, 4, 2), ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2028], timing: ( 16, 16, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x203C], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2030], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x203A], timing: ( 16, 16, 7), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x203B], timing: ( 18, 18, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2020], timing: ( 14, 14, 7), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2018], timing: ( 12, 12, 6), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2148], timing: ( 16, 16, 5), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2150], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2179], timing: ( 32, 32, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2178], timing: ( 28, 28, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2140], timing: ( 16, 16, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2168], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x217C], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2170], timing: ( 30, 30, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x217A], timing: ( 28, 28, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x217B], timing: ( 30, 30, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2160], timing: ( 26, 26, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2158], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E68], timing: ( 4, 6, 2), ins: Instruction::MOVEUSP(Target::DirectAReg(0), Direction::ToTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2188], timing: ( 18, 18, 7), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2190], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21B9], timing: ( 34, 34, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21B8], timing: ( 30, 30, 11), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2180], timing: ( 18, 18, 7), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21A8], timing: ( 30, 30, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21BC], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21B0], timing: ( 32, 32, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21BA], timing: ( 30, 30, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21BB], timing: ( 32, 32, 14), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x21A0], timing: ( 28, 28, 12), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2198], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2108], timing: ( 12, 14, 5), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2110], timing: ( 20, 22, 9), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2139], timing: ( 28, 30, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2138], timing: ( 24, 26, 9), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2100], timing: ( 12, 14, 5), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2128], timing: ( 24, 26, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x213C], timing: ( 20, 22, 9), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2130], timing: ( 26, 28, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x213A], timing: ( 24, 26, 10), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x213B], timing: ( 26, 28, 12), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2120], timing: ( 22, 24, 10), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2118], timing: ( 20, 22, 9), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20C8], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectAReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20D0], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectAReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20F9], timing: ( 28, 28, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Long), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20F8], timing: ( 24, 24, 8), ins: Instruction::MOVE(Target::IndirectMemory(0x00000000, Size::Word), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20C0], timing: ( 12, 12, 4), ins: Instruction::MOVE(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20E8], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20FC], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20F0], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20FA], timing: ( 24, 24, 9), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20FB], timing: ( 26, 26, 11), ins: Instruction::MOVE(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20E0], timing: ( 22, 22, 9), ins: Instruction::MOVE(Target::IndirectARegDec(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x20D8], timing: ( 20, 20, 8), ins: Instruction::MOVE(Target::IndirectARegInc(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E60], timing: ( 4, 6, 2), ins: Instruction::MOVEUSP(Target::DirectAReg(0), Direction::FromTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3048], timing: ( 4, 4, 2), ins: Instruction::MOVEA(Target::DirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3050], timing: ( 8, 8, 6), ins: Instruction::MOVEA(Target::IndirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3079], timing: ( 16, 16, 6), ins: Instruction::MOVEA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3078], timing: ( 12, 12, 6), ins: Instruction::MOVEA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3040], timing: ( 4, 4, 2), ins: Instruction::MOVEA(Target::DirectDReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3068], timing: ( 12, 12, 7), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x307C], timing: ( 8, 8, 4), ins: Instruction::MOVEA(Target::Immediate(00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3070], timing: ( 14, 14, 9), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x307A], timing: ( 12, 12, 7), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x307B], timing: ( 14, 14, 9), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3060], timing: ( 10, 10, 7), ins: Instruction::MOVEA(Target::IndirectARegDec(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x3058], timing: ( 8, 8, 6), ins: Instruction::MOVEA(Target::IndirectARegInc(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2048], timing: ( 4, 4, 2), ins: Instruction::MOVEA(Target::DirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2050], timing: ( 12, 12, 6), ins: Instruction::MOVEA(Target::IndirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2079], timing: ( 20, 20, 6), ins: Instruction::MOVEA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2078], timing: ( 16, 16, 6), ins: Instruction::MOVEA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2040], timing: ( 4, 4, 2), ins: Instruction::MOVEA(Target::DirectDReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2068], timing: ( 16, 16, 7), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x207C], timing: ( 12, 12, 6), ins: Instruction::MOVEA(Target::Immediate(00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2070], timing: ( 18, 18, 9), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x207A], timing: ( 16, 16, 7), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x207B], timing: ( 18, 18, 9), ins: Instruction::MOVEA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2060], timing: ( 14, 14, 7), ins: Instruction::MOVEA(Target::IndirectARegDec(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x2058], timing: ( 12, 12, 6), ins: Instruction::MOVEA(Target::IndirectARegInc(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4C90], timing: ( 16, 16, 12), ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CB9], timing: ( 24, 24, 12), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Long), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CB8], timing: ( 20, 20, 12), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Word), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CA8], timing: ( 20, 20, 13), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CB0], timing: ( 22, 22, 15), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CBA], timing: ( 16, 16, 0), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CBB], timing: ( 18, 18, 0), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4C98], timing: ( 12, 12, 8), ins: Instruction::MOVEM(Target::IndirectARegInc(0), Size::Word, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4890], timing: ( 12, 12, 8), ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48B9], timing: ( 20, 20, 8), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Long), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48B8], timing: ( 16, 16, 8), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Word), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48A8], timing: ( 16, 16, 9), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48B0], timing: ( 18, 18, 11), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48A0], timing: ( 8, 8, 4), ins: Instruction::MOVEM(Target::IndirectARegDec(0), Size::Word, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CD0], timing: ( 20, 20, 12), ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CF9], timing: ( 28, 28, 12), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Long), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CF8], timing: ( 24, 24, 12), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Word), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CE8], timing: ( 24, 24, 13), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CF0], timing: ( 26, 26, 15), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CFA], timing: ( 20, 20, 9), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CFB], timing: ( 22, 22, 11), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4CD8], timing: ( 12, 12, 8), ins: Instruction::MOVEM(Target::IndirectARegInc(0), Size::Long, Direction::FromTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48D0], timing: ( 16, 16, 8), ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48F9], timing: ( 24, 24, 8), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Long), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48F8], timing: ( 20, 20, 8), ins: Instruction::MOVEM(Target::IndirectMemory(0x00000000, Size::Word), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48E8], timing: ( 20, 20, 9), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48F0], timing: ( 22, 22, 11), ins: Instruction::MOVEM(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x48E0], timing: ( 8, 8, 4), ins: Instruction::MOVEM(Target::IndirectARegDec(0), Size::Long, Direction::ToTarget, 0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0108], timing: ( 16, 16, 12), ins: Instruction::MOVEP(0, 0, 0x00000000, Size::Word, Direction::FromTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0188], timing: ( 16, 16, 11), ins: Instruction::MOVEP(0, 0, 0x00000000, Size::Word, Direction::ToTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0148], timing: ( 24, 24, 18), ins: Instruction::MOVEP(0, 0, 0x00000000, Size::Long, Direction::FromTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x01C8], timing: ( 24, 24, 17), ins: Instruction::MOVEP(0, 0, 0x00000000, Size::Long, Direction::ToTarget) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x7000], timing: ( 4, 4, 2), ins: Instruction::MOVEQ(0, 0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1D0], timing: ( 58, 36, 31), ins: Instruction::MULW(Target::IndirectAReg(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1F9], timing: ( 66, 44, 31), ins: Instruction::MULW(Target::IndirectMemory(0x00000000, Size::Long), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1F8], timing: ( 62, 40, 31), ins: Instruction::MULW(Target::IndirectMemory(0x00000000, Size::Word), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1C0], timing: ( 54, 32, 27), ins: Instruction::MULW(Target::DirectDReg(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1E8], timing: ( 62, 40, 32), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1FC], timing: ( 58, 36, 29), ins: Instruction::MULW(Target::Immediate(00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1F0], timing: ( 64, 42, 34), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1FA], timing: ( 62, 40, 32), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1FB], timing: ( 64, 42, 34), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1E0], timing: ( 60, 38, 32), ins: Instruction::MULW(Target::IndirectARegDec(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC1D8], timing: ( 58, 36, 31), ins: Instruction::MULW(Target::IndirectARegInc(0), 0, Sign::Signed) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0D0], timing: ( 58, 34, 31), ins: Instruction::MULW(Target::IndirectAReg(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0F9], timing: ( 66, 42, 31), ins: Instruction::MULW(Target::IndirectMemory(0x00000000, Size::Long), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0F8], timing: ( 62, 38, 31), ins: Instruction::MULW(Target::IndirectMemory(0x00000000, Size::Word), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0C0], timing: ( 54, 30, 27), ins: Instruction::MULW(Target::DirectDReg(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0E8], timing: ( 62, 38, 32), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0FC], timing: ( 58, 34, 29), ins: Instruction::MULW(Target::Immediate(00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0F0], timing: ( 64, 40, 34), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0FA], timing: ( 62, 38, 32), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0FB], timing: ( 64, 40, 34), ins: Instruction::MULW(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0E0], timing: ( 60, 36, 32), ins: Instruction::MULW(Target::IndirectARegDec(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xC0D8], timing: ( 58, 34, 31), ins: Instruction::MULW(Target::IndirectARegInc(0), 0, Sign::Unsigned) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4810], timing: ( 12, 12, 10), ins: Instruction::NBCD(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4839], timing: ( 20, 20, 10), ins: Instruction::NBCD(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4838], timing: ( 16, 16, 10), ins: Instruction::NBCD(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4800], timing: ( 6, 6, 6), ins: Instruction::NBCD(Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4828], timing: ( 16, 16, 11), ins: Instruction::NBCD(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4830], timing: ( 18, 18, 13), ins: Instruction::NBCD(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4820], timing: ( 14, 14, 11), ins: Instruction::NBCD(Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4818], timing: ( 12, 12, 10), ins: Instruction::NBCD(Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4410], timing: ( 12, 12, 8), ins: Instruction::NEG(Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4439], timing: ( 20, 20, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4438], timing: ( 16, 16, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4400], timing: ( 4, 4, 2), ins: Instruction::NEG(Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4428], timing: ( 16, 16, 9), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4430], timing: ( 18, 18, 11), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4420], timing: ( 14, 14, 9), ins: Instruction::NEG(Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4418], timing: ( 12, 12, 8), ins: Instruction::NEG(Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4450], timing: ( 12, 12, 8), ins: Instruction::NEG(Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4479], timing: ( 20, 20, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4478], timing: ( 16, 16, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4440], timing: ( 4, 4, 2), ins: Instruction::NEG(Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4468], timing: ( 16, 16, 9), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4470], timing: ( 18, 18, 11), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4460], timing: ( 14, 14, 9), ins: Instruction::NEG(Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4458], timing: ( 12, 12, 8), ins: Instruction::NEG(Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4490], timing: ( 20, 20, 8), ins: Instruction::NEG(Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44B9], timing: ( 28, 28, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44B8], timing: ( 24, 24, 8), ins: Instruction::NEG(Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4480], timing: ( 6, 6, 2), ins: Instruction::NEG(Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44A8], timing: ( 24, 24, 9), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44B0], timing: ( 26, 26, 11), ins: Instruction::NEG(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x44A0], timing: ( 22, 22, 9), ins: Instruction::NEG(Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4498], timing: ( 20, 20, 8), ins: Instruction::NEG(Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4010], timing: ( 12, 12, 8), ins: Instruction::NEGX(Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4039], timing: ( 20, 20, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4038], timing: ( 16, 16, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4000], timing: ( 4, 4, 2), ins: Instruction::NEGX(Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4028], timing: ( 16, 16, 9), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4030], timing: ( 18, 18, 11), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4020], timing: ( 14, 14, 9), ins: Instruction::NEGX(Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4018], timing: ( 12, 12, 8), ins: Instruction::NEGX(Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4050], timing: ( 12, 12, 8), ins: Instruction::NEGX(Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4079], timing: ( 20, 20, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4078], timing: ( 16, 16, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4040], timing: ( 4, 4, 2), ins: Instruction::NEGX(Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4068], timing: ( 16, 16, 9), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4070], timing: ( 18, 18, 11), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4060], timing: ( 14, 14, 9), ins: Instruction::NEGX(Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4058], timing: ( 12, 12, 8), ins: Instruction::NEGX(Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4090], timing: ( 20, 20, 8), ins: Instruction::NEGX(Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40B9], timing: ( 28, 28, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40B8], timing: ( 24, 24, 8), ins: Instruction::NEGX(Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4080], timing: ( 6, 6, 2), ins: Instruction::NEGX(Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40A8], timing: ( 24, 24, 9), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40B0], timing: ( 26, 26, 11), ins: Instruction::NEGX(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x40A0], timing: ( 22, 22, 9), ins: Instruction::NEGX(Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4098], timing: ( 20, 20, 8), ins: Instruction::NEGX(Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E71], timing: ( 4, 4, 2), ins: Instruction::NOP }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4610], timing: ( 12, 12, 8), ins: Instruction::NOT(Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4639], timing: ( 20, 20, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4638], timing: ( 16, 16, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4600], timing: ( 4, 4, 2), ins: Instruction::NOT(Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4628], timing: ( 16, 16, 9), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4630], timing: ( 18, 18, 11), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4620], timing: ( 14, 14, 9), ins: Instruction::NOT(Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4618], timing: ( 12, 12, 8), ins: Instruction::NOT(Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4650], timing: ( 12, 12, 8), ins: Instruction::NOT(Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4679], timing: ( 20, 20, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4678], timing: ( 16, 16, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4640], timing: ( 4, 4, 2), ins: Instruction::NOT(Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4668], timing: ( 16, 16, 9), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4670], timing: ( 18, 18, 11), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4660], timing: ( 14, 14, 9), ins: Instruction::NOT(Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4658], timing: ( 12, 12, 8), ins: Instruction::NOT(Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4690], timing: ( 20, 20, 8), ins: Instruction::NOT(Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46B9], timing: ( 28, 28, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46B8], timing: ( 24, 24, 8), ins: Instruction::NOT(Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4680], timing: ( 6, 6, 2), ins: Instruction::NOT(Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46A8], timing: ( 24, 24, 9), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46B0], timing: ( 26, 26, 11), ins: Instruction::NOT(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x46A0], timing: ( 22, 22, 9), ins: Instruction::NOT(Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4698], timing: ( 20, 20, 8), ins: Instruction::NOT(Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8010], timing: ( 8, 8, 6), ins: Instruction::OR(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8039], timing: ( 16, 16, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8038], timing: ( 12, 12, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8000], timing: ( 4, 4, 2), ins: Instruction::OR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8028], timing: ( 12, 12, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x803C], timing: ( 10, 8, 4), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8030], timing: ( 14, 14, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x803A], timing: ( 12, 12, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x803B], timing: ( 14, 14, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8020], timing: ( 10, 10, 7), ins: Instruction::OR(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8018], timing: ( 8, 8, 6), ins: Instruction::OR(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8110], timing: ( 12, 12, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8139], timing: ( 20, 20, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8138], timing: ( 16, 16, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8128], timing: ( 16, 16, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8130], timing: ( 18, 18, 11), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8120], timing: ( 14, 14, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8118], timing: ( 12, 12, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8050], timing: ( 8, 8, 6), ins: Instruction::OR(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8079], timing: ( 16, 16, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8078], timing: ( 12, 12, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8040], timing: ( 4, 4, 2), ins: Instruction::OR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8068], timing: ( 12, 12, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x807C], timing: ( 10, 8, 4), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8070], timing: ( 14, 14, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x807A], timing: ( 12, 12, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x807B], timing: ( 14, 14, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8060], timing: ( 10, 10, 7), ins: Instruction::OR(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8058], timing: ( 8, 8, 6), ins: Instruction::OR(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8150], timing: ( 12, 12, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8179], timing: ( 20, 20, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8178], timing: ( 16, 16, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8168], timing: ( 16, 16, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8170], timing: ( 18, 18, 11), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8160], timing: ( 14, 14, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8158], timing: ( 12, 12, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8090], timing: ( 14, 14, 6), ins: Instruction::OR(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80B9], timing: ( 22, 22, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80B8], timing: ( 18, 18, 6), ins: Instruction::OR(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8080], timing: ( 6, 6, 2), ins: Instruction::OR(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80A8], timing: ( 18, 18, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80BC], timing: ( 16, 14, 6), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80B0], timing: ( 20, 20, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80BA], timing: ( 18, 18, 7), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80BB], timing: ( 20, 20, 9), ins: Instruction::OR(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x80A0], timing: ( 16, 16, 7), ins: Instruction::OR(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8098], timing: ( 14, 14, 6), ins: Instruction::OR(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8190], timing: ( 20, 20, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81B9], timing: ( 28, 28, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81B8], timing: ( 24, 24, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81A8], timing: ( 24, 24, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81B0], timing: ( 26, 26, 11), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x81A0], timing: ( 22, 22, 9), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8198], timing: ( 20, 20, 8), ins: Instruction::OR(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0010], timing: ( 16, 16, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0039], timing: ( 24, 24, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0038], timing: ( 20, 20, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0000], timing: ( 8, 8, 2), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0028], timing: ( 20, 20, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0030], timing: ( 22, 22, 11), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0020], timing: ( 18, 18, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0018], timing: ( 16, 16, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0050], timing: ( 16, 16, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0079], timing: ( 24, 24, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0078], timing: ( 20, 20, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0040], timing: ( 8, 8, 2), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0068], timing: ( 20, 20, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0070], timing: ( 22, 22, 11), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0060], timing: ( 18, 18, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0058], timing: ( 16, 16, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x003C], timing: ( 20, 16, 12), ins: Instruction::ORtoCCR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x007C], timing: ( 20, 16, 12), ins: Instruction::ORtoSR(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0090], timing: ( 28, 28, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x00B9], timing: ( 36, 36, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x00B8], timing: ( 32, 32, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0080], timing: ( 16, 14, 2), ins: Instruction::OR(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x00A8], timing: ( 32, 32, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x00B0], timing: ( 34, 34, 11), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x00A0], timing: ( 30, 30, 9), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0098], timing: ( 28, 28, 8), ins: Instruction::OR(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4850], timing: ( 10, 10, 9), ins: Instruction::PEA(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4879], timing: ( 20, 20, 9), ins: Instruction::PEA(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4878], timing: ( 16, 16, 9), ins: Instruction::PEA(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4868], timing: ( 16, 16, 10), ins: Instruction::PEA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4870], timing: ( 20, 20, 12), ins: Instruction::PEA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x487A], timing: ( 16, 16, 10), ins: Instruction::PEA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x487B], timing: ( 20, 20, 12), ins: Instruction::PEA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE138], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE118], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7D0], timing: ( 12, 12, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7F9], timing: ( 20, 20, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7F8], timing: ( 16, 16, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7E8], timing: ( 16, 16, 12), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7F0], timing: ( 18, 18, 14), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7E0], timing: ( 14, 14, 12), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE7D8], timing: ( 12, 12, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE178], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE158], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1B8], timing: ( 8, 8, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE198], timing: ( 8, 8, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE038], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE018], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6D0], timing: ( 12, 12, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6F9], timing: ( 20, 20, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6F8], timing: ( 16, 16, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6E8], timing: ( 16, 16, 12), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6F0], timing: ( 18, 18, 14), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6E0], timing: ( 14, 14, 12), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE6D8], timing: ( 12, 12, 11), ins: Instruction::ROd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE078], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE058], timing: ( 6, 6, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0B8], timing: ( 8, 8, 8), ins: Instruction::ROd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE098], timing: ( 8, 8, 8), ins: Instruction::ROd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE130], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE110], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5D0], timing: ( 12, 12, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5F9], timing: ( 20, 20, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5F8], timing: ( 16, 16, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5E8], timing: ( 16, 16, 10), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5F0], timing: ( 18, 18, 12), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5E0], timing: ( 14, 14, 10), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE5D8], timing: ( 12, 12, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE170], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE150], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE1B0], timing: ( 8, 8, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE190], timing: ( 8, 8, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Left) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE030], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE010], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4D0], timing: ( 12, 12, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectAReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4F9], timing: ( 20, 20, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Long), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4F8], timing: ( 16, 16, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectMemory(0x00000000, Size::Word), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4E8], timing: ( 16, 16, 10), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4F0], timing: ( 18, 18, 12), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4E0], timing: ( 14, 14, 10), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectARegDec(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE4D8], timing: ( 12, 12, 9), ins: Instruction::ROXd(Target::Immediate(00000001), Target::IndirectARegInc(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE070], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE050], timing: ( 6, 6, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE0B0], timing: ( 8, 8, 12), ins: Instruction::ROXd(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0xE090], timing: ( 8, 8, 12), ins: Instruction::ROXd(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long, ShiftDirection::Right) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E73], timing: ( 20, 24, 20), ins: Instruction::RTE }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E77], timing: ( 20, 20, 14), ins: Instruction::RTR }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E75], timing: ( 16, 16, 10), ins: Instruction::RTS }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8108], timing: ( 18, 18, 16), ins: Instruction::SBCD(Target::IndirectARegDec(0), Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x8100], timing: ( 6, 6, 4), ins: Instruction::SBCD(Target::DirectDReg(0), Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::CarryClear, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x54D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::CarryClear, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::CarrySet, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x55D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::CarrySet, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Equal, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::Equal, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::Equal, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::Equal, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::Equal, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::Equal, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::Equal, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x57D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Equal, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::False, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::False, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::False, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::False, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::False, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::False, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::False, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::False, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CD0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5CD8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::GreaterThanOrEqual, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5ED0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::GreaterThan, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5EE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5ED8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::GreaterThan, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::High, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::High, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::High, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::High, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::High, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::High, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::High, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x52D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::High, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FD0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5FD8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LessThanOrEqual, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::LowOrSame, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x53D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LowOrSame, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DD0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LessThan, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::LessThan, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::LessThan, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::LessThan, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::LessThan, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::LessThan, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::LessThan, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5DD8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::LessThan, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BD0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Minus, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::Minus, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::Minus, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::Minus, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::Minus, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::Minus, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::Minus, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5BD8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Minus, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::NotEqual, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x56D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::NotEqual, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AD0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Plus, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AF9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::Plus, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AF8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::Plus, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AC0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::Plus, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AE8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::Plus, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AF0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::Plus, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AE0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::Plus, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5AD8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::Plus, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::True, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::True, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::True, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50C0], timing: ( 6, 4, 4), ins: Instruction::Scc(Condition::True, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::True, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::True, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::True, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x50D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::True, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E72], timing: ( 4, 4, 8), ins: Instruction::STOP(0x0000) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9010], timing: ( 8, 8, 6), ins: Instruction::SUB(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9039], timing: ( 16, 16, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9038], timing: ( 12, 12, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9000], timing: ( 4, 4, 2), ins: Instruction::SUB(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9028], timing: ( 12, 12, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x903C], timing: ( 10, 8, 4), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9030], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x903A], timing: ( 12, 12, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x903B], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9020], timing: ( 10, 10, 7), ins: Instruction::SUB(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9018], timing: ( 8, 8, 6), ins: Instruction::SUB(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9110], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9139], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9138], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9128], timing: ( 16, 16, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9130], timing: ( 18, 18, 11), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9120], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9118], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9048], timing: ( 4, 4, 2), ins: Instruction::SUB(Target::DirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9050], timing: ( 8, 8, 6), ins: Instruction::SUB(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9079], timing: ( 16, 16, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9078], timing: ( 12, 12, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9040], timing: ( 4, 4, 2), ins: Instruction::SUB(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9068], timing: ( 12, 12, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x907C], timing: ( 10, 8, 4), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9070], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x907A], timing: ( 12, 12, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x907B], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9060], timing: ( 10, 10, 7), ins: Instruction::SUB(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9058], timing: ( 8, 8, 6), ins: Instruction::SUB(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9150], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9179], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9178], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9168], timing: ( 16, 16, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9170], timing: ( 18, 18, 11), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9160], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9158], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9088], timing: ( 6, 6, 2), ins: Instruction::SUB(Target::DirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9090], timing: ( 14, 14, 6), ins: Instruction::SUB(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90B9], timing: ( 22, 22, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Long), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90B8], timing: ( 18, 18, 6), ins: Instruction::SUB(Target::IndirectMemory(0x00000000, Size::Word), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9080], timing: ( 6, 6, 2), ins: Instruction::SUB(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90A8], timing: ( 18, 18, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90BC], timing: ( 16, 14, 6), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90B0], timing: ( 20, 20, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90BA], timing: ( 18, 18, 7), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90BB], timing: ( 20, 20, 9), ins: Instruction::SUB(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90A0], timing: ( 16, 16, 7), ins: Instruction::SUB(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9098], timing: ( 14, 14, 6), ins: Instruction::SUB(Target::IndirectARegInc(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9190], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91B9], timing: ( 28, 28, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91B8], timing: ( 24, 24, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91A8], timing: ( 24, 24, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91B0], timing: ( 26, 26, 11), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91A0], timing: ( 22, 22, 9), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9198], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::DirectDReg(0), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90C8], timing: ( 8, 8, 2), ins: Instruction::SUBA(Target::DirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90D0], timing: ( 12, 12, 6), ins: Instruction::SUBA(Target::IndirectAReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90F9], timing: ( 20, 20, 6), ins: Instruction::SUBA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90F8], timing: ( 16, 16, 6), ins: Instruction::SUBA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90C0], timing: ( 8, 8, 2), ins: Instruction::SUBA(Target::DirectDReg(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90E8], timing: ( 16, 16, 7), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90FC], timing: ( 14, 12, 4), ins: Instruction::SUBA(Target::Immediate(00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90F0], timing: ( 18, 18, 9), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90FA], timing: ( 16, 16, 7), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90FB], timing: ( 18, 18, 9), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90E0], timing: ( 14, 14, 7), ins: Instruction::SUBA(Target::IndirectARegDec(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x90D8], timing: ( 12, 12, 6), ins: Instruction::SUBA(Target::IndirectARegInc(0), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91C8], timing: ( 6, 6, 2), ins: Instruction::SUBA(Target::DirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91D0], timing: ( 14, 14, 6), ins: Instruction::SUBA(Target::IndirectAReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91F9], timing: ( 22, 22, 6), ins: Instruction::SUBA(Target::IndirectMemory(0x00000000, Size::Long), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91F8], timing: ( 18, 18, 6), ins: Instruction::SUBA(Target::IndirectMemory(0x00000000, Size::Word), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91C0], timing: ( 6, 6, 2), ins: Instruction::SUBA(Target::DirectDReg(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91E8], timing: ( 18, 18, 7), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91FC], timing: ( 16, 14, 6), ins: Instruction::SUBA(Target::Immediate(00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91F0], timing: ( 20, 20, 9), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91FA], timing: ( 18, 18, 7), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::PC, None, 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91FB], timing: ( 20, 20, 9), ins: Instruction::SUBA(Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91E0], timing: ( 16, 16, 7), ins: Instruction::SUBA(Target::IndirectARegDec(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x91D8], timing: ( 14, 14, 6), ins: Instruction::SUBA(Target::IndirectARegInc(0), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0410], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0439], timing: ( 24, 24, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0438], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0400], timing: ( 8, 8, 2), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0428], timing: ( 20, 20, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0430], timing: ( 22, 22, 11), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0420], timing: ( 18, 18, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0418], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0450], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0479], timing: ( 24, 24, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0478], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0440], timing: ( 8, 8, 2), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0468], timing: ( 20, 20, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0470], timing: ( 22, 22, 11), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0460], timing: ( 18, 18, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0458], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0490], timing: ( 28, 28, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x04B9], timing: ( 36, 36, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x04B8], timing: ( 32, 32, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0480], timing: ( 16, 14, 2), ins: Instruction::SUB(Target::Immediate(00000000), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x04A8], timing: ( 32, 32, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x04B0], timing: ( 34, 34, 11), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x04A0], timing: ( 30, 30, 9), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x0498], timing: ( 28, 28, 8), ins: Instruction::SUB(Target::Immediate(00000000), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5110], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5139], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5138], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5100], timing: ( 4, 4, 2), ins: Instruction::SUB(Target::Immediate(00000008), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5128], timing: ( 16, 16, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5130], timing: ( 18, 18, 11), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5120], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5118], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5148], timing: ( 8, 4, 2), ins: Instruction::SUBA(Target::Immediate(00000008), 0, Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5150], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5179], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5178], timing: ( 16, 16, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5140], timing: ( 4, 4, 2), ins: Instruction::SUB(Target::Immediate(00000008), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5168], timing: ( 16, 16, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5170], timing: ( 18, 18, 11), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5160], timing: ( 14, 14, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5158], timing: ( 12, 12, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5188], timing: ( 8, 8, 2), ins: Instruction::SUBA(Target::Immediate(00000008), 0, Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5190], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51B9], timing: ( 28, 28, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51B8], timing: ( 24, 24, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5180], timing: ( 8, 8, 2), ins: Instruction::SUB(Target::Immediate(00000008), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51A8], timing: ( 24, 24, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51B0], timing: ( 26, 26, 11), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x51A0], timing: ( 22, 22, 9), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x5198], timing: ( 20, 20, 8), ins: Instruction::SUB(Target::Immediate(00000008), Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9108], timing: ( 18, 18, 12), ins: Instruction::SUBX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9100], timing: ( 4, 4, 2), ins: Instruction::SUBX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9148], timing: ( 18, 18, 12), ins: Instruction::SUBX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9140], timing: ( 4, 4, 2), ins: Instruction::SUBX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9188], timing: ( 30, 30, 12), ins: Instruction::SUBX(Target::IndirectARegDec(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x9180], timing: ( 8, 6, 2), ins: Instruction::SUBX(Target::DirectDReg(0), Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::OverflowClear, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x58D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::OverflowClear, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59D0], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59F9], timing: ( 20, 20, 10), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59F8], timing: ( 16, 16, 10), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59C0], timing: ( 4, 4, 4), ins: Instruction::Scc(Condition::OverflowSet, Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59E8], timing: ( 16, 16, 11), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59F0], timing: ( 18, 18, 13), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59E0], timing: ( 14, 14, 11), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x59D8], timing: ( 12, 12, 10), ins: Instruction::Scc(Condition::OverflowSet, Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4840], timing: ( 4, 4, 4), ins: Instruction::SWAP(0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AD0], timing: ( 18, 18, 16), ins: Instruction::TAS(Target::IndirectAReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AF9], timing: ( 26, 26, 16), ins: Instruction::TAS(Target::IndirectMemory(0x00000000, Size::Long)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AF8], timing: ( 22, 22, 16), ins: Instruction::TAS(Target::IndirectMemory(0x00000000, Size::Word)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AC0], timing: ( 4, 4, 4), ins: Instruction::TAS(Target::DirectDReg(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AE8], timing: ( 22, 22, 17), ins: Instruction::TAS(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AF0], timing: ( 24, 24, 19), ins: Instruction::TAS(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AE0], timing: ( 20, 20, 17), ins: Instruction::TAS(Target::IndirectARegDec(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AD8], timing: ( 18, 18, 16), ins: Instruction::TAS(Target::IndirectARegInc(0)) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E40], timing: ( 4, 4, 4), ins: Instruction::TRAP(0) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E76], timing: ( 4, 4, 4), ins: Instruction::TRAPV }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A10], timing: ( 8, 8, 6), ins: Instruction::TST(Target::IndirectAReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A39], timing: ( 16, 16, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Long), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A38], timing: ( 12, 12, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Word), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A00], timing: ( 4, 4, 2), ins: Instruction::TST(Target::DirectDReg(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A28], timing: ( 12, 12, 7), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A30], timing: ( 14, 14, 9), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A20], timing: ( 10, 10, 7), ins: Instruction::TST(Target::IndirectARegDec(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A18], timing: ( 8, 8, 6), ins: Instruction::TST(Target::IndirectARegInc(0), Size::Byte) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A50], timing: ( 8, 8, 6), ins: Instruction::TST(Target::IndirectAReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A79], timing: ( 16, 16, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Long), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A78], timing: ( 12, 12, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Word), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A40], timing: ( 4, 4, 2), ins: Instruction::TST(Target::DirectDReg(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A68], timing: ( 12, 12, 7), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A70], timing: ( 14, 14, 9), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A60], timing: ( 10, 10, 7), ins: Instruction::TST(Target::IndirectARegDec(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A58], timing: ( 8, 8, 6), ins: Instruction::TST(Target::IndirectARegInc(0), Size::Word) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A90], timing: ( 12, 12, 6), ins: Instruction::TST(Target::IndirectAReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AB9], timing: ( 20, 20, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Long), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AB8], timing: ( 16, 16, 6), ins: Instruction::TST(Target::IndirectMemory(0x00000000, Size::Word), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A80], timing: ( 4, 4, 2), ins: Instruction::TST(Target::DirectDReg(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AA8], timing: ( 16, 16, 7), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), None, 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AB0], timing: ( 18, 18, 9), ins: Instruction::TST(Target::IndirectRegOffset(BaseRegister::AReg(0), Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Word }), 0x00000000), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4AA0], timing: ( 14, 14, 7), ins: Instruction::TST(Target::IndirectARegDec(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4A98], timing: ( 12, 12, 6), ins: Instruction::TST(Target::IndirectARegInc(0), Size::Long) }, + TimingCase { cpu: M68kType::MC68000, data: &[0x4E58], timing: ( 12, 12, 6), ins: Instruction::UNLK(0) }, +]; + diff --git a/emulator/cpus/m68k/tests/timing_tests.rs b/emulator/cpus/m68k/tests/timing_tests.rs new file mode 100644 index 0000000..7cedc01 --- /dev/null +++ b/emulator/cpus/m68k/tests/timing_tests.rs @@ -0,0 +1,104 @@ + +use moa_core::{System, Error, MemoryBlock, BusPort, Address, Addressable, wrap_transmutable}; + +use moa_m68k::{M68k, M68kType}; +use moa_m68k::instructions::{Instruction, Target, Size}; +use moa_m68k::timing::M68kInstructionTiming; + +const INIT_STACK: Address = 0x00002000; +const INIT_ADDR: Address = 0x00000010; + + +struct TimingCase { + cpu: M68kType, + data: &'static [u16], + timing: (u16, u16, u16), + ins: Instruction, +} + +const TIMING_TESTS: &'static [TimingCase] = &[ + TimingCase { cpu: M68kType::MC68000, data: &[0xD090], timing: ( 14, 14, 6), ins: Instruction::ADD(Target::IndirectAReg(0), Target::DirectDReg(0), Size::Long) }, +]; + + +fn init_decode_test(cputype: M68kType) -> (M68k, System) { + let mut system = System::default(); + + // Insert basic initialization + let data = vec![0; 0x00100000]; + let mem = MemoryBlock::new(data); + system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap(); + system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap(); + system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap(); + + // Initialize the CPU and make sure it's in the expected state + let port = if cputype <= M68kType::MC68010 { + BusPort::new(0, 24, 16, system.bus.clone()) + } else { + BusPort::new(0, 24, 16, system.bus.clone()) + }; + let mut cpu = M68k::new(cputype, 10_000_000, port); + cpu.init().unwrap(); + assert_eq!(cpu.state.pc, INIT_ADDR as u32); + assert_eq!(cpu.state.ssp, INIT_STACK as u32); + + cpu.decoder.init(INIT_ADDR as u32); + assert_eq!(cpu.decoder.start, INIT_ADDR as u32); + assert_eq!(cpu.decoder.instruction, Instruction::NOP); + (cpu, system) +} + +fn load_memory(system: &System, data: &[u16]) { + let mut addr = INIT_ADDR; + for word in data { + system.get_bus().write_beu16(addr, *word).unwrap(); + addr += 2; + } +} + +fn run_timing_test(case: &TimingCase) -> Result<(), Error> { + let (mut cpu, system) = init_decode_test(case.cpu); + let mut timing = M68kInstructionTiming::new(case.cpu, 16); + + load_memory(&system, case.data); + cpu.decode_next().unwrap(); + assert_eq!(cpu.decoder.instruction, case.ins.clone()); + + timing.add_instruction(&cpu.decoder.instruction); + let result = timing.calculate_clocks(false, 1); + let expected = match case.cpu { + M68kType::MC68000 => case.timing.0, + M68kType::MC68010 => case.timing.1, + _ => case.timing.2, + }; + + //assert_eq!(expected, result); + if expected == result { + Ok(()) + } else { + println!("{:?}", timing); + Err(Error::new(&format!("expected {} but found {}", expected, result))) + } +} + +#[test] +pub fn run_timing_tests() { + let mut errors = 0; + for case in TIMING_TESTS { + // NOTE switched to only show the failures rather than all tests + //print!("Testing for {:?}...", case.ins); + //match run_timing_test(case) { + // Ok(()) => println!("ok"), + // Err(err) => { println!("{}", err.msg); errors += 1 }, + //} + + if let Err(_) = run_timing_test(case) { + errors += 1; + } + } + + if errors > 0 { + panic!("{} errors", errors); + } +} + diff --git a/tests/harte_tests/src/main.rs b/tests/harte_tests/src/main.rs index dc07933..0ab2ede 100644 --- a/tests/harte_tests/src/main.rs +++ b/tests/harte_tests/src/main.rs @@ -137,7 +137,7 @@ impl TestCase { fn init_execute_test(cputype: M68kType, state: &TestState) -> Result<(M68k, System), Error> { - let mut system = System::new(); + let mut system = System::default(); // Insert basic initialization let data = vec![0; 0x01000000];