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Added address mask to memory accesses from the tests

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transistor 2022-09-11 14:51:58 -07:00
parent aa39b4b11f
commit 34bdd86772
2 changed files with 9 additions and 3 deletions
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4
src/memory.rs
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@ -267,6 +267,10 @@ impl BusPort {
self.subdevice.borrow_mut().dump_memory(self.offset + (addr & self.address_mask), count)
}
pub fn address_mask(&self) -> Address {
self.address_mask
}
pub fn data_width(&self) -> u8 {
self.data_width
}

8
tests/harte_tests/src/main.rs
View File

@ -14,7 +14,7 @@ use serde_derive::Deserialize;
use moa::error::Error;
use moa::system::System;
use moa::memory::{MemoryBlock, BusPort};
use moa::devices::{Addressable, Steppable, wrap_transmutable};
use moa::devices::{Address, Addressable, Steppable, wrap_transmutable};
use moa::cpus::m68k::{M68k, M68kType};
use moa::cpus::m68k::state::Status;
@ -205,16 +205,18 @@ fn assert_state(cpu: &M68k, system: &System, expected: &TestState) -> Result<(),
assert_value(cpu.state.sr, expected.sr, "sr")?;
assert_value(cpu.state.pc, expected.pc, "pc")?;
let addr_mask = cpu.port.address_mask();
// Load instructions into memory
for (i, ins) in expected.prefetch.iter().enumerate() {
let addr = expected.pc + (i as u32 * 2);
let actual = system.get_bus().read_beu16(addr as u64)?;
let actual = system.get_bus().read_beu16(addr as Address & addr_mask)?;
assert_value(actual, *ins, &format!("prefetch at {}", addr))?;
}
// Load data bytes into memory
for (addr, byte) in expected.ram.iter() {
let actual = system.get_bus().read_u8(*addr as u64)?;
let actual = system.get_bus().read_u8(*addr as Address & addr_mask)?;
assert_value(actual, *byte, &format!("ram at {}", addr))?;
}