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Fixed bug in m68k decode with MUL

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This commit is contained in:
transistor 2021-11-29 11:12:20 -08:00
parent 31ff828f15
commit 364c51524f
2 changed files with 3 additions and 2 deletions
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4
src/cpus/m68k/decode.rs
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@ -473,7 +473,7 @@ impl M68kDecoder {
OPCG_MUL_AND => { OPCG_MUL_AND => {
let size = get_size(ins); let size = get_size(ins);
if (ins & 0b000111110000) == 0b000100000000 { if (ins & 0b0001_1111_0000) == 0b0001_0000_0000 {
let regx = get_high_reg(ins); let regx = get_high_reg(ins);
let regy = get_low_reg(ins); let regy = get_low_reg(ins);
@ -481,7 +481,7 @@ impl M68kDecoder {
false => Ok(Instruction::ABCD(Target::DirectDReg(regy), Target::DirectDReg(regx))), false => Ok(Instruction::ABCD(Target::DirectDReg(regy), Target::DirectDReg(regx))),
true => Ok(Instruction::ABCD(Target::IndirectARegDec(regy), Target::IndirectARegDec(regx))), true => Ok(Instruction::ABCD(Target::IndirectARegDec(regy), Target::IndirectARegDec(regx))),
} }
} else if (ins & 0b000100110000) == 0b000100000000 { } else if (ins & 0b0001_0011_0000) == 0b0001_0000_0000 && !size.is_none() {
let regx = get_high_reg(ins); let regx = get_high_reg(ins);
let regy = get_low_reg(ins); let regy = get_low_reg(ins);
match (ins & 0x00F8) >> 3 { match (ins & 0x00F8) >> 3 {

1
src/cpus/m68k/tests.rs
View File

@ -38,6 +38,7 @@ mod decode_tests {
TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0010], ins: Some(Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte)) }, TestCase { cpu: M68kType::MC68000, data: &[0x0C00, 0x0010], ins: Some(Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte)) },
TestCase { cpu: M68kType::MC68000, data: &[0x81FC, 0x0003], ins: Some(Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed)) }, TestCase { cpu: M68kType::MC68000, data: &[0x81FC, 0x0003], ins: Some(Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed)) },
TestCase { cpu: M68kType::MC68000, data: &[0xC1FC, 0x0276], ins: Some(Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed)) }, TestCase { cpu: M68kType::MC68000, data: &[0xC1FC, 0x0276], ins: Some(Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed)) },
TestCase { cpu: M68kType::MC68000, data: &[0xCDC5], ins: Some(Instruction::MULW(Target::DirectDReg(5), 6, Sign::Signed)) },
TestCase { cpu: M68kType::MC68000, data: &[0x0108, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::FromTarget)) }, TestCase { cpu: M68kType::MC68000, data: &[0x0108, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::FromTarget)) },
TestCase { cpu: M68kType::MC68000, data: &[0x0148, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::FromTarget)) }, TestCase { cpu: M68kType::MC68000, data: &[0x0148, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Long, Direction::FromTarget)) },
TestCase { cpu: M68kType::MC68000, data: &[0x0188, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::ToTarget)) }, TestCase { cpu: M68kType::MC68000, data: &[0x0188, 0x1234], ins: Some(Instruction::MOVEP(0, 0, 0x1234, Size::Word, Direction::ToTarget)) },