Reorganized state and decoding into their own structs
This commit is contained in:
transistor
parent
f453e6dde2
commit
38bcf0af3f
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@ -2,9 +2,9 @@
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use crate::error::Error;
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use crate::memory::{Address, AddressSpace};
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use super::execute::MC68010;
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use super::execute::ERR_ILLEGAL_INSTRUCTION;
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const OPCG_BIT_OPS: u8 = 0x0;
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const OPCG_MOVE_BYTE: u8 = 0x1;
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const OPCG_MOVE_LONG: u8 = 0x2;
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@ -179,19 +179,25 @@ pub enum Instruction {
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}
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impl MC68010 {
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fn read_instruction_word(&mut self, space: &mut AddressSpace) -> Result<u16, Error> {
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let word = space.read_beu16(self.pc as Address)?;
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//debug!("{:#010x} {:#06x?}", self.pc, word);
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self.pc += 2;
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Ok(word)
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pub struct M68kDecoder {
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pub start: u32,
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pub end: u32,
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pub instruction: Instruction,
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}
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impl M68kDecoder {
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pub fn new(start: u32) -> M68kDecoder {
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M68kDecoder {
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start: start,
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end: start,
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instruction: Instruction::NOP,
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}
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}
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fn read_instruction_long(&mut self, space: &mut AddressSpace) -> Result<u32, Error> {
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let word = space.read_beu32(self.pc as Address)?;
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//debug!("{:#010x} {:#010x}", self.pc, word);
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self.pc += 4;
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Ok(word)
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pub fn decode_at(space: &mut AddressSpace, start: u32) -> Result<M68kDecoder, Error> {
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let mut decoder = M68kDecoder::new(start);
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decoder.instruction = decoder.decode_one(space)?;
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Ok(decoder)
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}
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pub fn decode_one(&mut self, space: &mut AddressSpace) -> Result<Instruction, Error> {
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@ -584,6 +590,20 @@ impl MC68010 {
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}
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}
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fn read_instruction_word(&mut self, space: &mut AddressSpace) -> Result<u16, Error> {
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let word = space.read_beu16(self.end as Address)?;
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//debug!("{:#010x} {:#06x?}", self.end, word);
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self.end += 2;
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Ok(word)
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}
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fn read_instruction_long(&mut self, space: &mut AddressSpace) -> Result<u32, Error> {
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let word = space.read_beu32(self.end as Address)?;
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//debug!("{:#010x} {:#010x}", self.end, word);
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self.end += 4;
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Ok(word)
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}
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fn decode_lower_effective_address(&mut self, space: &mut AddressSpace, ins: u16, size: Option<Size>) -> Result<Target, Error> {
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let reg = get_low_reg(ins);
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let mode = get_low_mode(ins);
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@ -2,7 +2,18 @@
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use crate::error::Error;
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use crate::memory::{Address, AddressSpace};
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use super::decode::{Instruction, Target, Size, Direction, Condition, ShiftDirection, ControlRegister, RegisterType, sign_extend_to_long};
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use super::decode::{
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M68kDecoder,
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Instruction,
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Target,
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Size,
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Direction,
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Condition,
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ShiftDirection,
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ControlRegister,
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RegisterType,
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sign_extend_to_long
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};
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/*
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pub trait Processor {
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@ -27,14 +38,14 @@ pub const ERR_ILLEGAL_INSTRUCTION: u32 = 4;
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum State {
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pub enum Status {
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Init,
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Running,
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Halted,
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Stopped,
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}
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pub struct MC68010 {
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pub state: State,
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pub struct MC68010State {
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pub status: Status,
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pub pc: u32,
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pub sr: u16,
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@ -44,18 +55,12 @@ pub struct MC68010 {
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pub usp: u32,
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pub vbr: u32,
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pub current_instruction_addr: u32,
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pub current_instruction: Instruction,
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pub breakpoints: Vec<u32>,
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pub use_tracing: bool,
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pub use_debugger: bool,
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}
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impl MC68010 {
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pub fn new() -> MC68010 {
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MC68010 {
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state: State::Init,
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impl MC68010State {
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pub fn new() -> MC68010State {
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MC68010State {
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status: Status::Init,
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pc: 0,
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sr: FLAGS_ON_RESET,
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@ -65,9 +70,27 @@ impl MC68010 {
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usp: 0,
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vbr: 0,
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}
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}
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}
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pub struct MC68010 {
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pub state: MC68010State,
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pub decoder: M68kDecoder,
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pub breakpoints: Vec<u32>,
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pub use_tracing: bool,
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pub use_debugger: bool,
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}
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impl MC68010 {
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pub fn new() -> MC68010 {
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MC68010 {
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state: MC68010State::new(),
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decoder: M68kDecoder::new(0),
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current_instruction_addr: 0,
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current_instruction: Instruction::NOP,
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breakpoints: vec![],
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use_tracing: false,
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use_debugger: false,
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@ -75,46 +98,55 @@ impl MC68010 {
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}
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pub fn reset(&mut self) {
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self.state = State::Init;
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self.pc = 0;
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self.sr = FLAGS_ON_RESET;
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self.d_reg = [0; 8];
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self.a_reg = [0; 7];
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self.msp = 0;
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self.usp = 0;
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self.state = MC68010State::new();
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self.vbr = 0;
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self.decoder = M68kDecoder::new(0);
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self.current_instruction_addr = 0;
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self.current_instruction = Instruction::NOP;
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self.breakpoints = vec![];
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self.use_tracing = false;
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self.use_debugger = false;
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}
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pub fn is_running(&self) -> bool {
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self.state != State::Halted
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self.state.status != Status::Stopped
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}
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pub fn init(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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println!("Initializing CPU");
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self.msp = space.read_beu32(0)?;
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self.pc = space.read_beu32(4)?;
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self.state = State::Running;
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self.state.msp = space.read_beu32(0)?;
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self.state.pc = space.read_beu32(4)?;
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self.state.status = Status::Running;
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Ok(())
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}
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pub fn dump_state(&self, space: &mut AddressSpace) {
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println!("Status: {:?}", self.state.status);
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println!("PC: {:#010x}", self.state.pc);
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println!("SR: {:#06x}", self.state.sr);
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for i in 0..7 {
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println!("D{}: {:#010x} A{}: {:#010x}", i, self.state.d_reg[i as usize], i, self.state.a_reg[i as usize]);
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}
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println!("D7: {:#010x}", self.state.d_reg[7]);
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println!("MSP: {:#010x}", self.state.msp);
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println!("USP: {:#010x}", self.state.usp);
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println!("Current Instruction: {:#010x} {:?}", self.decoder.start, self.decoder.instruction);
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println!("");
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space.dump_memory(self.state.msp as Address, 0x40);
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println!("");
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}
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pub fn add_breakpoint(&mut self, addr: Address) {
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self.breakpoints.push(addr as u32);
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}
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pub fn step(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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match self.state {
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State::Init => self.init(space),
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State::Halted => Err(Error::new("CPU halted")),
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State::Running => {
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match self.state.status {
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Status::Init => self.init(space),
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Status::Stopped => Err(Error::new("CPU stopped")),
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Status::Running => {
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self.decode_next(space)?;
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self.execute_current(space)?;
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Ok(())
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@ -122,48 +154,12 @@ impl MC68010 {
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}
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}
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pub fn dump_state(&self, space: &mut AddressSpace) {
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println!("State: {:?}", self.state);
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println!("PC: {:#010x}", self.pc);
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println!("SR: {:#06x}", self.sr);
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for i in 0..7 {
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println!("D{}: {:#010x} A{}: {:#010x}", i, self.d_reg[i as usize], i, self.a_reg[i as usize]);
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}
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println!("D7: {:#010x}", self.d_reg[7]);
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println!("MSP: {:#010x}", self.msp);
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println!("USP: {:#010x}", self.usp);
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println!("Current Instruction: {:#010x} {:?}", self.current_instruction_addr, self.current_instruction);
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println!("");
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space.dump_memory(self.msp as Address, 0x40);
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println!("");
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}
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fn is_supervisor(&self) -> bool {
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self.sr & FLAGS_SUPERVISOR != 0
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}
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fn push_long(&mut self, space: &mut AddressSpace, value: u32) -> Result<(), Error> {
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let reg = self.get_stack_pointer_mut();
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*reg -= 4;
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//println!("PUSHING {:08x} at {:08x}", value, *reg);
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space.write_beu32(*reg as Address, value)
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}
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fn pop_long(&mut self, space: &mut AddressSpace) -> Result<u32, Error> {
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let reg = self.get_stack_pointer_mut();
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let value = space.read_beu32(*reg as Address)?;
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//println!("POPPING {:08x} at {:08x}", value, *reg);
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*reg += 4;
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Ok(value)
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}
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pub(crate) fn decode_next(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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self.current_instruction_addr = self.pc;
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self.current_instruction = self.decode_one(space)?;
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self.decoder = M68kDecoder::decode_at(space, self.state.pc)?;
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self.state.pc = self.decoder.end;
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for breakpoint in &self.breakpoints {
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if *breakpoint == self.current_instruction_addr {
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if *breakpoint == self.decoder.start {
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self.use_tracing = true;
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self.use_debugger = true;
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break;
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@ -173,10 +169,10 @@ impl MC68010 {
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if self.use_tracing {
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// Print instruction bytes for debugging
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let ins_data: Result<String, Error> =
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(0..((self.pc - self.current_instruction_addr) / 2)).map(|offset|
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Ok(format!("{:04x} ", space.read_beu16((self.current_instruction_addr + (offset * 2)) as Address)?))
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(0..((self.state.pc - self.decoder.start) / 2)).map(|offset|
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Ok(format!("{:04x} ", space.read_beu16((self.decoder.start + (offset * 2)) as Address)?))
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).collect();
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debug!("{:#010x}: {}\n\t{:?}\n", self.current_instruction_addr, ins_data?, self.current_instruction);
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debug!("{:#010x}: {}\n\t{:?}\n", self.decoder.start, ins_data?, self.decoder.instruction);
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}
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if self.use_debugger {
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@ -192,7 +188,7 @@ impl MC68010 {
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loop {
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std::io::stdin().read_line(&mut buffer).unwrap();
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match buffer.as_ref() {
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"dump\n" => space.dump_memory(self.msp as Address, (0x200000 - self.msp) as Address),
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"dump\n" => space.dump_memory(self.state.msp as Address, (0x200000 - self.state.msp) as Address),
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"continue\n" => {
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self.use_debugger = false;
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return;
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@ -203,7 +199,7 @@ impl MC68010 {
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}
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pub(crate) fn execute_current(&mut self, space: &mut AddressSpace) -> Result<(), Error> {
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match self.current_instruction {
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match self.decoder.instruction {
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Instruction::ADD(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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let existing = self.get_target_value(space, dest, size)?;
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@ -228,25 +224,25 @@ impl MC68010 {
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self.set_logic_flags(value, size);
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},
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Instruction::ANDtoCCR(value) => {
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self.sr = self.sr | value as u16;
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self.state.sr = self.state.sr | value as u16;
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},
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Instruction::ANDtoSR(value) => {
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self.sr = self.sr | value;
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self.state.sr = self.state.sr | value;
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},
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//Instruction::ASd(Target, Target, Size, ShiftDirection) => {
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//},
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Instruction::Bcc(cond, offset) => {
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let should_branch = self.get_current_condition(cond);
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if should_branch {
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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self.state.pc = self.decoder.start.wrapping_add(offset as u32) + 2;
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}
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},
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Instruction::BRA(offset) => {
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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self.state.pc = self.decoder.start.wrapping_add(offset as u32) + 2;
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},
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Instruction::BSR(offset) => {
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self.push_long(space, self.pc)?;
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self.pc = self.current_instruction_addr.wrapping_add(offset as u32) + 2;
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self.push_long(space, self.state.pc)?;
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self.state.pc = self.decoder.start.wrapping_add(offset as u32) + 2;
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},
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Instruction::BTST(bitnum, target, size) => {
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let bitnum = self.get_target_value(space, bitnum, Size::Byte)?;
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@ -277,7 +273,7 @@ impl MC68010 {
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Instruction::CLR(target, size) => {
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self.set_target_value(space, target, 0, size)?;
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// Clear flags except Zero flag
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self.sr = (self.sr & 0xFFF0) | 0x0004;
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self.state.sr = (self.state.sr & 0xFFF0) | 0x0004;
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},
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Instruction::CMP(src, dest, size) => {
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let value = self.get_target_value(space, src, size)?;
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@ -300,30 +296,30 @@ impl MC68010 {
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self.set_logic_flags(value, size);
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},
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Instruction::EORtoCCR(value) => {
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self.sr = self.sr ^ value as u16;
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self.state.sr = self.state.sr ^ value as u16;
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},
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Instruction::EORtoSR(value) => {
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self.sr = self.sr ^ value;
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self.state.sr = self.state.sr ^ value;
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},
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//Instruction::EXG(Target, Target) => {
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//},
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Instruction::EXT(reg, size) => {
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let byte = (self.d_reg[reg as usize] as u8) as i8;
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let byte = (self.state.d_reg[reg as usize] as u8) as i8;
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let result = match size {
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Size::Byte => (byte as u8) as u32,
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Size::Word => ((byte as i16) as u16) as u32,
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Size::Long => (byte as i32) as u32,
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};
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self.d_reg[reg as usize] = result;
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self.state.d_reg[reg as usize] = result;
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},
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//Instruction::ILLEGAL => {
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//},
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Instruction::JMP(target) => {
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self.pc = self.get_target_address(target)? - 2;
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self.state.pc = self.get_target_address(target)? - 2;
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},
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Instruction::JSR(target) => {
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self.push_long(space, self.pc)?;
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self.pc = self.get_target_address(target)? - 2;
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self.push_long(space, self.state.pc)?;
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self.state.pc = self.get_target_address(target)? - 2;
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},
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Instruction::LEA(target, reg) => {
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let value = self.get_target_address(target)?;
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@ -340,7 +336,7 @@ impl MC68010 {
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}
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self.set_compare_flags(pair.0, size, false);
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if pair.1 {
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self.sr |= FLAGS_EXTEND | FLAGS_CARRY;
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self.state.sr |= FLAGS_EXTEND | FLAGS_CARRY;
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}
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self.set_target_value(space, target, pair.0, size)?;
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},
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@ -355,14 +351,14 @@ impl MC68010 {
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*addr = sign_extend_to_long(value, size) as u32;
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},
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Instruction::MOVEfromSR(target) => {
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self.set_target_value(space, target, self.sr as u32, Size::Word)?;
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self.set_target_value(space, target, self.state.sr as u32, Size::Word)?;
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},
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Instruction::MOVEtoSR(target) => {
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self.sr = self.get_target_value(space, target, Size::Word)? as u16;
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self.state.sr = self.get_target_value(space, target, Size::Word)? as u16;
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},
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Instruction::MOVEtoCCR(target) => {
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let value = self.get_target_value(space, target, Size::Word)? as u16;
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self.sr = (self.sr & 0xFF00) | (value & 0x00FF);
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self.state.sr = (self.state.sr & 0xFF00) | (value & 0x00FF);
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},
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Instruction::MOVEC(target, control_reg, dir) => {
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match dir {
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@ -395,7 +391,7 @@ impl MC68010 {
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}
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for i in (0..8).rev() {
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if (mask & 0x01) != 0 {
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self.set_target_value(space, target, self.d_reg[i], size)?;
|
||||
self.set_target_value(space, target, self.state.d_reg[i], size)?;
|
||||
}
|
||||
mask >>= 1;
|
||||
}
|
||||
|
|
@ -403,7 +399,7 @@ impl MC68010 {
|
|||
let mut mask = mask;
|
||||
for i in 0..8 {
|
||||
if (mask & 0x01) != 0 {
|
||||
self.d_reg[i] = self.get_target_value(space, target, size)?;
|
||||
self.state.d_reg[i] = self.get_target_value(space, target, size)?;
|
||||
}
|
||||
mask >>= 1;
|
||||
}
|
||||
|
|
@ -419,7 +415,7 @@ impl MC68010 {
|
|||
},
|
||||
Instruction::MOVEQ(data, reg) => {
|
||||
let value = sign_extend_to_long(data as u32, Size::Byte) as u32;
|
||||
self.d_reg[reg as usize] = value;
|
||||
self.state.d_reg[reg as usize] = value;
|
||||
self.set_compare_flags(value, Size::Long, false);
|
||||
},
|
||||
//Instruction::MUL(Target, Target, Size, Sign) => {
|
||||
|
|
@ -440,10 +436,10 @@ impl MC68010 {
|
|||
self.set_logic_flags(value, size);
|
||||
},
|
||||
Instruction::ORtoCCR(value) => {
|
||||
self.sr = self.sr | value as u16;
|
||||
self.state.sr = self.state.sr | value as u16;
|
||||
},
|
||||
Instruction::ORtoSR(value) => {
|
||||
self.sr = self.sr | value;
|
||||
self.state.sr = self.state.sr | value;
|
||||
},
|
||||
Instruction::PEA(target) => {
|
||||
let value = self.get_target_address(target)?;
|
||||
|
|
@ -460,7 +456,7 @@ impl MC68010 {
|
|||
//Instruction::RTR => {
|
||||
//},
|
||||
Instruction::RTS => {
|
||||
self.pc = self.pop_long(space)?;
|
||||
self.state.pc = self.pop_long(space)?;
|
||||
},
|
||||
//Instruction::STOP(u16) => {
|
||||
//},
|
||||
|
|
@ -471,8 +467,8 @@ impl MC68010 {
|
|||
self.set_target_value(space, dest, result, size)?;
|
||||
},
|
||||
Instruction::SWAP(reg) => {
|
||||
let value = self.d_reg[reg as usize];
|
||||
self.d_reg[reg as usize] = ((value & 0x0000FFFF) << 16) | ((value & 0xFFFF0000) >> 16);
|
||||
let value = self.state.d_reg[reg as usize];
|
||||
self.state.d_reg[reg as usize] = ((value & 0x0000FFFF) << 16) | ((value & 0xFFFF0000) >> 16);
|
||||
},
|
||||
//Instruction::TAS(Target) => {
|
||||
//},
|
||||
|
|
@ -492,10 +488,25 @@ impl MC68010 {
|
|||
Ok(())
|
||||
}
|
||||
|
||||
fn push_long(&mut self, space: &mut AddressSpace, value: u32) -> Result<(), Error> {
|
||||
let reg = self.get_stack_pointer_mut();
|
||||
*reg -= 4;
|
||||
//println!("PUSHING {:08x} at {:08x}", value, *reg);
|
||||
space.write_beu32(*reg as Address, value)
|
||||
}
|
||||
|
||||
fn pop_long(&mut self, space: &mut AddressSpace) -> Result<u32, Error> {
|
||||
let reg = self.get_stack_pointer_mut();
|
||||
let value = space.read_beu32(*reg as Address)?;
|
||||
//println!("POPPING {:08x} at {:08x}", value, *reg);
|
||||
*reg += 4;
|
||||
Ok(value)
|
||||
}
|
||||
|
||||
fn get_target_value(&mut self, space: &mut AddressSpace, target: Target, size: Size) -> Result<u32, Error> {
|
||||
match target {
|
||||
Target::Immediate(value) => Ok(value),
|
||||
Target::DirectDReg(reg) => Ok(get_value_sized(self.d_reg[reg as usize], size)),
|
||||
Target::DirectDReg(reg) => Ok(get_value_sized(self.state.d_reg[reg as usize], size)),
|
||||
Target::DirectAReg(reg) => Ok(get_value_sized(*self.get_a_reg_mut(reg), size)),
|
||||
Target::IndirectAReg(reg) => get_address_sized(space, *self.get_a_reg_mut(reg) as Address, size),
|
||||
Target::IndirectARegInc(reg) => {
|
||||
|
|
@ -522,11 +533,11 @@ impl MC68010 {
|
|||
get_address_sized(space, addr as Address, size)
|
||||
},
|
||||
Target::IndirectPCOffset(offset) => {
|
||||
get_address_sized(space, self.pc.wrapping_add(offset as u32) as Address, size)
|
||||
get_address_sized(space, self.state.pc.wrapping_add(offset as u32) as Address, size)
|
||||
},
|
||||
Target::IndirectPCXRegOffset(rtype, xreg, offset, target_size) => {
|
||||
let reg_offset = sign_extend_to_long(self.get_x_reg_value(rtype, xreg), target_size);
|
||||
get_address_sized(space, self.pc.wrapping_add(reg_offset as u32).wrapping_add(offset as u32) as Address, size)
|
||||
get_address_sized(space, self.state.pc.wrapping_add(reg_offset as u32).wrapping_add(offset as u32) as Address, size)
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -534,7 +545,7 @@ impl MC68010 {
|
|||
fn set_target_value(&mut self, space: &mut AddressSpace, target: Target, value: u32, size: Size) -> Result<(), Error> {
|
||||
match target {
|
||||
Target::DirectDReg(reg) => {
|
||||
set_value_sized(&mut self.d_reg[reg as usize], value, size);
|
||||
set_value_sized(&mut self.state.d_reg[reg as usize], value, size);
|
||||
},
|
||||
Target::DirectAReg(reg) => {
|
||||
set_value_sized(self.get_a_reg_mut(reg), value, size);
|
||||
|
|
@ -585,11 +596,11 @@ impl MC68010 {
|
|||
addr
|
||||
},
|
||||
Target::IndirectPCOffset(offset) => {
|
||||
self.pc.wrapping_add(offset as u32)
|
||||
self.state.pc.wrapping_add(offset as u32)
|
||||
},
|
||||
Target::IndirectPCXRegOffset(rtype, xreg, offset, target_size) => {
|
||||
let reg_offset = sign_extend_to_long(self.get_x_reg_value(rtype, xreg), target_size);
|
||||
self.pc.wrapping_add(reg_offset as u32).wrapping_add(offset as u32)
|
||||
self.state.pc.wrapping_add(reg_offset as u32).wrapping_add(offset as u32)
|
||||
},
|
||||
_ => return Err(Error::new(&format!("Invalid addressing target: {:?}", target))),
|
||||
};
|
||||
|
|
@ -614,33 +625,37 @@ impl MC68010 {
|
|||
|
||||
fn get_control_reg_mut(&mut self, control_reg: ControlRegister) -> &mut u32 {
|
||||
match control_reg {
|
||||
ControlRegister::VBR => &mut self.vbr,
|
||||
ControlRegister::VBR => &mut self.state.vbr,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_stack_pointer_mut(&mut self) -> &mut u32 {
|
||||
if self.is_supervisor() { &mut self.msp } else { &mut self.usp }
|
||||
if self.is_supervisor() { &mut self.state.msp } else { &mut self.state.usp }
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn get_a_reg_mut(&mut self, reg: u8) -> &mut u32 {
|
||||
if reg == 7 {
|
||||
if self.is_supervisor() { &mut self.msp } else { &mut self.usp }
|
||||
if self.is_supervisor() { &mut self.state.msp } else { &mut self.state.usp }
|
||||
} else {
|
||||
&mut self.a_reg[reg as usize]
|
||||
&mut self.state.a_reg[reg as usize]
|
||||
}
|
||||
}
|
||||
|
||||
fn get_x_reg_value(&self, rtype: RegisterType, reg: u8) -> u32 {
|
||||
match rtype {
|
||||
RegisterType::Data => self.d_reg[reg as usize],
|
||||
RegisterType::Address => self.d_reg[reg as usize],
|
||||
RegisterType::Data => self.state.d_reg[reg as usize],
|
||||
RegisterType::Address => self.state.d_reg[reg as usize],
|
||||
}
|
||||
}
|
||||
|
||||
fn is_supervisor(&self) -> bool {
|
||||
self.state.sr & FLAGS_SUPERVISOR != 0
|
||||
}
|
||||
|
||||
fn get_flag(&self, flag: u16) -> bool {
|
||||
if (self.sr & flag) == 0 {
|
||||
if (self.state.sr & flag) == 0 {
|
||||
false
|
||||
} else {
|
||||
true
|
||||
|
|
@ -660,7 +675,7 @@ impl MC68010 {
|
|||
if carry {
|
||||
flags |= FLAGS_CARRY | FLAGS_OVERFLOW;
|
||||
}
|
||||
self.sr = (self.sr & 0xFFF0) | flags;
|
||||
self.state.sr = (self.state.sr & 0xFFF0) | flags;
|
||||
}
|
||||
|
||||
fn set_logic_flags(&mut self, value: u32, size: Size) {
|
||||
|
|
@ -671,13 +686,13 @@ impl MC68010 {
|
|||
if value == 0 {
|
||||
flags |= FLAGS_ZERO
|
||||
}
|
||||
self.sr |= (self.sr & 0xFFF0) | flags;
|
||||
self.state.sr |= (self.state.sr & 0xFFF0) | flags;
|
||||
}
|
||||
|
||||
fn set_bit_test_flags(&mut self, value: u32, bitnum: u32, size: Size) -> u32 {
|
||||
let mask = 0x1 << (bitnum % size.in_bits());
|
||||
let zeroflag = if (value & mask) == 0 { FLAGS_ZERO } else { 0 };
|
||||
self.sr = (self.sr & !FLAGS_ZERO) | zeroflag;
|
||||
self.state.sr = (self.state.sr & !FLAGS_ZERO) | zeroflag;
|
||||
mask
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,9 @@ fn init_test() -> (MC68010, AddressSpace) {
|
|||
|
||||
let mut cpu = MC68010::new();
|
||||
cpu.step(&mut space).unwrap();
|
||||
assert_eq!(cpu.pc, INIT_ADDR as u32);
|
||||
assert_eq!(cpu.msp, INIT_STACK as u32);
|
||||
assert_eq!(cpu.current_instruction, Instruction::NOP);
|
||||
assert_eq!(cpu.state.pc, INIT_ADDR as u32);
|
||||
assert_eq!(cpu.state.msp, INIT_STACK as u32);
|
||||
assert_eq!(cpu.decoder.instruction, Instruction::NOP);
|
||||
(cpu, space)
|
||||
}
|
||||
|
||||
|
|
@ -36,7 +36,7 @@ mod tests {
|
|||
|
||||
space.write_beu16(INIT_ADDR, 0x4e71).unwrap();
|
||||
cpu.decode_next(&mut space).unwrap();
|
||||
assert_eq!(cpu.current_instruction, Instruction::NOP);
|
||||
assert_eq!(cpu.decoder.instruction, Instruction::NOP);
|
||||
cpu.execute_current(&mut space).unwrap();
|
||||
// TODO you need a way to easily check the entire state (you maybe need to make a special struct for the state)
|
||||
}
|
||||
|
|
@ -49,9 +49,9 @@ mod tests {
|
|||
space.write_beu16(INIT_ADDR, 0x0008).unwrap();
|
||||
space.write_beu16(INIT_ADDR + 2, 0x00FF).unwrap();
|
||||
cpu.decode_next(&mut space).unwrap();
|
||||
assert_eq!(cpu.current_instruction, Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte));
|
||||
assert_eq!(cpu.decoder.instruction, Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte));
|
||||
cpu.execute_current(&mut space).unwrap();
|
||||
assert_eq!(cpu.a_reg[0], 0x000000FF);
|
||||
assert_eq!(cpu.state.a_reg[0], 0x000000FF);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ fn main() {
|
|||
//cpu.add_breakpoint(0x07f8);
|
||||
//cpu.add_breakpoint(0x0836);
|
||||
//cpu.add_breakpoint(0x0838);
|
||||
//cpu.add_breakpoint(0x0ea0);
|
||||
|
||||
cpu.use_tracing = true;
|
||||
while cpu.is_running() {
|
||||
|
|
@ -44,7 +45,7 @@ fn main() {
|
|||
|
||||
// TODO I need to add a way to decode and dump the assembly for a section of code, in debugger
|
||||
/*
|
||||
cpu.pc = 0x07f8;
|
||||
cpu.state.pc = 0x07f8;
|
||||
while cpu.is_running() {
|
||||
cpu.decode_next(&mut space).unwrap();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue