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Fixed bug in DIVW instruction

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This commit is contained in:
transistor 2021-10-22 13:02:48 -07:00
parent f9e018742b
commit 447b3727ed
2 changed files with 11 additions and 1 deletions
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2
src/cpus/m68k/decode.rs
View File

@ -399,7 +399,7 @@ impl M68kDecoder {
if size.is_none() {
let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
let effective_addr = self.decode_lower_effective_address(memory, ins, size)?;
let effective_addr = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?;
Ok(Instruction::DIVW(effective_addr, get_high_reg(ins), sign))
} else if (ins & 0x1F0) == 0x100 {
let regx = get_high_reg(ins);

10
src/cpus/m68k/tests.rs
View File

@ -373,6 +373,16 @@ mod decode_tests {
assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
}
#[test]
fn instruction_divs() {
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
system.get_bus().write_beu16(INIT_ADDR, 0x81FC).unwrap();
system.get_bus().write_beu16(INIT_ADDR + 2, 0x0003).unwrap();
cpu.decode_next(&system).unwrap();
assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
}
#[test]
fn instruction_mulsl() {
let (mut cpu, system) = init_decode_test(M68kType::MC68030);