From 492027fa7aeb9d20956e2d178934081f21f6b457 Mon Sep 17 00:00:00 2001 From: transistor Date: Mon, 18 Oct 2021 21:41:42 -0700 Subject: [PATCH] Fixed a bug in bit field instruction decode We were trying to decode the effective address before fetching the second instruction word for bitfield instructions, which was causing it to use the wrong word for the offset:width information, which was preventing the shell from printing to the screen after boot --- src/cpus/m68k/decode.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpus/m68k/decode.rs b/src/cpus/m68k/decode.rs index 99b3b7b..ba341a0 100644 --- a/src/cpus/m68k/decode.rs +++ b/src/cpus/m68k/decode.rs @@ -547,10 +547,9 @@ impl M68kDecoder { } }, None => { - let target = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?; - - let count = Target::Immediate(1); if (ins & 0x800) == 0 { + let target = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?; + let count = Target::Immediate(1); match (ins & 0x0600) >> 9 { 0b00 => Ok(Instruction::ASd(count, target, Size::Word, dir)), 0b01 => Ok(Instruction::LSd(count, target, Size::Word, dir)), @@ -573,6 +572,7 @@ impl M68kDecoder { false => RegOrImmediate::DReg((ext & 0x0007) as u8), }; + let target = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?; match (ins & 0x0700) >> 8 { 0b010 => Ok(Instruction::BFCHG(target, offset, width)), 0b100 => Ok(Instruction::BFCLR(target, offset, width)),