mirror of
https://github.com/transistorfet/moa.git
synced 2024-11-21 19:30:52 +00:00
Fixed the basic IN/OUT instructions on Z80, and basic RETI/RETN
This commit is contained in:
transistor
parent
c97b3b8aca
commit
57f9f93cc9
@ -21,6 +21,7 @@ pub struct System {
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pub debugger: RefCell<Debugger>,
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pub bus: Rc<RefCell<Bus>>,
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pub buses: HashMap<String, Rc<RefCell<Bus>>>,
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pub interrupt_controller: RefCell<InterruptController>,
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pub break_signal: Option<EdgeSignal>,
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@ -37,6 +38,7 @@ impl Default for System {
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debugger: RefCell::new(Debugger::default()),
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bus: Rc::new(RefCell::new(Bus::default())),
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buses: HashMap::new(),
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interrupt_controller: RefCell::new(InterruptController::default()),
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break_signal: None,
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@ -280,12 +280,24 @@ impl Z80 {
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//},
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//Instruction::INIR => {
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//},
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//Instruction::INic(reg) => {
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//},
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Instruction::INic(reg) => {
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let b = self.get_register_value(Register::B);
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let c = self.get_register_value(Register::C);
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let value = self.get_ioport_value(b, c)?;
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self.set_register_value(reg, value);
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self.set_numeric_flags(value as u16, Size::Byte);
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self.set_parity_flags(value);
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self.set_flag(Flags::HalfCarry, false);
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self.set_flag(Flags::AddSubtract, false);
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},
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//Instruction::INicz => {
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//},
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//Instruction::INx(u8) => {
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//},
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Instruction::INx(n) => {
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let a = self.get_register_value(Register::A);
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let value = self.get_ioport_value(a, n)?;
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self.set_register_value(Register::A, value);
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},
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Instruction::JP(addr) => {
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self.state.pc = addr;
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},
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@ -368,13 +380,18 @@ impl Z80 {
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//},
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//Instruction::OUTI => {
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//},
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//Instruction::OUTic(reg) => {
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//},
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Instruction::OUTic(reg) => {
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let b = self.get_register_value(Register::B);
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let c = self.get_register_value(Register::C);
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let value = self.get_register_value(reg);
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self.set_ioport_value(b, c, value)?;
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},
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//Instruction::OUTicz => {
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//},
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Instruction::OUTx(_port) => {
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// TODO this needs to be fixed
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//println!("OUT ({:x}), {:x} {}", port, self.state.reg[Register::A as usize], self.state.reg[Register::A as usize] as char);
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Instruction::OUTx(n) => {
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let a = self.get_register_value(Register::A);
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let value = self.get_register_value(Register::A);
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self.set_ioport_value(a, n, value)?;
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},
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Instruction::POP(regpair) => {
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let value = self.pop_word()?;
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@ -395,10 +412,12 @@ impl Z80 {
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Instruction::RET => {
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self.state.pc = self.pop_word()?;
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},
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//Instruction::RETI => {
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//},
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//Instruction::RETN => {
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//},
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Instruction::RETI => {
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self.state.pc = self.pop_word()?;
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},
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Instruction::RETN => {
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self.state.pc = self.pop_word()?;
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},
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Instruction::RETcc(cond) => {
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if self.get_current_condition(cond) {
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self.state.pc = self.pop_word()?;
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@ -728,6 +747,23 @@ impl Z80 {
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Ok(())
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}
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fn get_ioport_value(&mut self, upper: u8, lower: u8) -> Result<u8, Error> {
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let addr = ((upper as Address) << 8) | (lower as Address);
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if let Some(io) = self.ioport.as_mut() {
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Ok(io.read_u8(self.current_clock, addr)?)
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} else {
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Ok(0)
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}
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}
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fn set_ioport_value(&mut self, upper: u8, lower: u8, value: u8) -> Result<(), Error> {
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let addr = ((upper as Address) << 8) | (lower as Address);
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if let Some(io) = self.ioport.as_mut() {
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io.write_u8(self.current_clock, addr, value)?
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}
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Ok(())
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}
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fn get_register_value(&mut self, reg: Register) -> u8 {
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self.state.reg[reg as usize]
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@ -112,13 +112,14 @@ pub struct Z80 {
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pub decoder: Z80Decoder,
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pub debugger: Z80Debugger,
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pub port: BusPort,
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pub ioport: Option<BusPort>,
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pub reset: Signal<bool>,
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pub bus_request: Signal<bool>,
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pub current_clock: ClockTime,
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}
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impl Z80 {
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pub fn new(cputype: Z80Type, frequency: Frequency, port: BusPort) -> Self {
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pub fn new(cputype: Z80Type, frequency: Frequency, port: BusPort, ioport: Option<BusPort>) -> Self {
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Self {
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cputype,
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frequency,
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@ -126,6 +127,7 @@ impl Z80 {
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decoder: Z80Decoder::default(),
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debugger: Z80Debugger::default(),
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port,
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ioport,
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reset: Signal::new(false),
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bus_request: Signal::new(false),
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current_clock: ClockTime::START,
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@ -14,7 +14,7 @@ fn init_decode_test() -> (Z80, System) {
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system.add_addressable_device(0x0000, wrap_transmutable(mem)).unwrap();
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// Initialize the CPU and make sure it's in the expected state
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4), BusPort::new(0, 16, 8, system.bus.clone()));
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4), BusPort::new(0, 16, 8, system.bus.clone()), None);
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cpu.init().unwrap();
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(cpu, system)
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@ -489,7 +489,7 @@ fn init_execute_test() -> (Z80, System) {
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system.add_addressable_device(0x0000, wrap_transmutable(mem)).unwrap();
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// Initialize the CPU and make sure it's in the expected state
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4), BusPort::new(0, 16, 8, system.bus.clone()));
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let mut cpu = Z80::new(Z80Type::Z80, Frequency::from_mhz(4), BusPort::new(0, 16, 8, system.bus.clone()), None);
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cpu.init().unwrap();
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(cpu, system)
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@ -82,7 +82,7 @@ pub fn build_genesis<H: Host>(host: &mut H, mut options: SegaGenesisOptions) ->
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coproc_bus.borrow_mut().insert(0x6000, coproc_register.clone());
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coproc_bus.borrow_mut().insert(0x7f11, coproc_sn_sound.clone());
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coproc_bus.borrow_mut().insert(0x8000, coproc_area);
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let mut coproc = Z80::new(Z80Type::Z80, Frequency::from_hz(3_579_545), BusPort::new(0, 16, 8, coproc_bus));
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let mut coproc = Z80::new(Z80Type::Z80, Frequency::from_hz(3_579_545), BusPort::new(0, 16, 8, coproc_bus), None);
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coproc.set_debugging(true);
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let mut reset = coproc.reset.clone();
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let mut bus_request = coproc.bus_request.clone();
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@ -42,7 +42,8 @@ pub fn build_trs80<H: Host>(host: &mut H, options: Trs80Options) -> Result<Syste
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let video = Model1Video::new(host)?;
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system.add_addressable_device(0x37E0 + 0x420, wrap_transmutable(video)).unwrap();
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let cpu = Z80::new(Z80Type::Z80, options.frequency, BusPort::new(0, 16, 8, system.bus.clone()));
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// TODO the ioport needs to be hooked up
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let cpu = Z80::new(Z80Type::Z80, options.frequency, BusPort::new(0, 16, 8, system.bus.clone()), None);
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//cpu.add_breakpoint(0x0);
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//cpu.add_breakpoint(0xb55);
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//cpu.add_breakpoint(0xb76);
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@ -1,4 +1,4 @@
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Last run on 2023-05-13 at commit cf4e31454b417b361b70fcbf82edf6a1daf62eb8
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Last run on 2023-05-13 at commit c97b3b8aca39518b1a88a19ba236ac19c1717b25
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||||
|
||||
passed: 566963, failed: 83037, total 87%
|
||||
completed in 0m 33s
|
||||
@ -1,6 +1,8 @@
|
||||
|
||||
const DEFAULT_RAD_TESTS: &str = "tests/jsmoo/misc/tests/GeneratedTests/z80/v1/";
|
||||
|
||||
use std::rc::Rc;
|
||||
use std::cell::RefCell;
|
||||
use std::io::prelude::*;
|
||||
use std::fmt::{Debug, UpperHex};
|
||||
use std::path::PathBuf;
|
||||
@ -11,7 +13,7 @@ use clap::{Parser, ArgEnum};
|
||||
use flate2::read::GzDecoder;
|
||||
use serde_derive::Deserialize;
|
||||
|
||||
use moa_core::{System, Error, MemoryBlock, BusPort, Frequency, Address, Addressable, Steppable, wrap_transmutable};
|
||||
use moa_core::{System, Error, MemoryBlock, Bus, BusPort, Frequency, Address, Addressable, Steppable, wrap_transmutable};
|
||||
|
||||
use moa_z80::{Z80, Z80Type};
|
||||
use moa_z80::state::Flags;
|
||||
@ -87,6 +89,13 @@ struct TestState {
|
||||
ram: Vec<(u16, u8)>,
|
||||
}
|
||||
|
||||
#[derive(Debug, Deserialize)]
|
||||
struct TestPort {
|
||||
addr: u16,
|
||||
value: u8,
|
||||
atype: String,
|
||||
}
|
||||
|
||||
#[derive(Debug, Deserialize)]
|
||||
struct TestCase {
|
||||
name: String,
|
||||
@ -94,6 +103,8 @@ struct TestCase {
|
||||
initial_state: TestState,
|
||||
#[serde(rename(deserialize = "final"))]
|
||||
final_state: TestState,
|
||||
#[serde(default)]
|
||||
ports: Vec<TestPort>,
|
||||
}
|
||||
|
||||
impl TestState {
|
||||
@ -123,25 +134,36 @@ impl TestCase {
|
||||
self.initial_state.dump();
|
||||
println!("final:");
|
||||
self.final_state.dump();
|
||||
|
||||
println!("ports: ");
|
||||
for port in self.ports.iter() {
|
||||
println!("{:04x} {:02x} {}", port.addr, port.value, port.atype);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
fn init_execute_test(cputype: Z80Type, state: &TestState) -> Result<(Z80, System), Error> {
|
||||
fn init_execute_test(cputype: Z80Type, state: &TestState, ports: &[TestPort]) -> Result<(Z80, System, Rc<RefCell<Bus>>), Error> {
|
||||
let mut system = System::default();
|
||||
|
||||
// Insert basic initialization
|
||||
let data = vec![0; 0x01000000];
|
||||
let mem = MemoryBlock::new(data);
|
||||
let mem = MemoryBlock::new(vec![0; 0x1_0000]);
|
||||
system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap();
|
||||
|
||||
// Set up IOREQ as memory space
|
||||
let io_ram = wrap_transmutable(MemoryBlock::new(vec![0; 0x10000]));
|
||||
let io_bus = Rc::new(RefCell::new(Bus::default()));
|
||||
io_bus.borrow_mut().set_ignore_unmapped(true);
|
||||
io_bus.borrow_mut().insert(0x0000, io_ram.clone());
|
||||
|
||||
let port = BusPort::new(0, 16, 8, system.bus.clone());
|
||||
let mut cpu = Z80::new(cputype, Frequency::from_mhz(10), port);
|
||||
let ioport = BusPort::new(0, 16, 8, io_bus.clone());
|
||||
let mut cpu = Z80::new(cputype, Frequency::from_mhz(10), port, Some(ioport));
|
||||
cpu.state.status = Status::Running;
|
||||
|
||||
load_state(&mut cpu, &mut system, state)?;
|
||||
load_state(&mut cpu, &mut system, io_bus.clone(), state, ports)?;
|
||||
|
||||
Ok((cpu, system))
|
||||
Ok((cpu, system, io_bus))
|
||||
}
|
||||
|
||||
fn assert_value<T>(actual: T, expected: T, message: &str) -> Result<(), Error>
|
||||
@ -155,7 +177,7 @@ where
|
||||
}
|
||||
}
|
||||
|
||||
fn load_state(cpu: &mut Z80, system: &mut System, initial: &TestState) -> Result<(), Error> {
|
||||
fn load_state(cpu: &mut Z80, system: &mut System, io_bus: Rc<RefCell<Bus>>, initial: &TestState, ports: &[TestPort]) -> Result<(), Error> {
|
||||
cpu.state.reg[0] = initial.b;
|
||||
cpu.state.reg[1] = initial.c;
|
||||
cpu.state.reg[2] = initial.d;
|
||||
@ -183,12 +205,17 @@ fn load_state(cpu: &mut Z80, system: &mut System, initial: &TestState) -> Result
|
||||
system.get_bus().write_u8(system.clock, *addr as u64, *byte)?;
|
||||
}
|
||||
|
||||
// Load data bytes into io space
|
||||
for port in ports.iter() {
|
||||
io_bus.borrow_mut().write_u8(system.clock, port.addr as u64, port.value)?;
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
const IGNORE_FLAG_MASK: u8 = Flags::F3 as u8 | Flags::F5 as u8;
|
||||
|
||||
fn assert_state(cpu: &Z80, system: &System, expected: &TestState, check_extra_flags: bool) -> Result<(), Error> {
|
||||
fn assert_state(cpu: &Z80, system: &System, io_bus: Rc<RefCell<Bus>>, expected: &TestState, check_extra_flags: bool, ports: &[TestPort]) -> Result<(), Error> {
|
||||
assert_value(cpu.state.reg[0], expected.b, "b")?;
|
||||
assert_value(cpu.state.reg[1], expected.c, "c")?;
|
||||
assert_value(cpu.state.reg[2], expected.d, "d")?;
|
||||
@ -223,22 +250,30 @@ fn assert_state(cpu: &Z80, system: &System, expected: &TestState, check_extra_fl
|
||||
assert_value(actual, *byte, &format!("ram at {:x}", addr))?;
|
||||
}
|
||||
|
||||
// Load data bytes into io space
|
||||
for port in ports.iter() {
|
||||
if port.atype == "w" {
|
||||
let actual = io_bus.borrow_mut().read_u8(system.clock, port.addr as u64)?;
|
||||
assert_value(actual, port.value, &format!("port value at {:x}", port.addr))?;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn step_cpu_and_assert(cpu: &mut Z80, system: &System, case: &TestCase, check_extra_flags: bool) -> Result<(), Error> {
|
||||
fn step_cpu_and_assert(cpu: &mut Z80, system: &System, io_bus: Rc<RefCell<Bus>>, case: &TestCase, check_extra_flags: bool) -> Result<(), Error> {
|
||||
let _clock_elapsed = cpu.step(&system)?;
|
||||
|
||||
assert_state(&cpu, &system, &case.final_state, check_extra_flags)?;
|
||||
assert_state(&cpu, &system, io_bus, &case.final_state, check_extra_flags, &case.ports)?;
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn run_test(case: &TestCase, args: &Args) -> Result<(), Error> {
|
||||
let (mut cpu, system) = init_execute_test(Z80Type::Z80, &case.initial_state).unwrap();
|
||||
let (mut cpu, system, io_bus) = init_execute_test(Z80Type::Z80, &case.initial_state, &case.ports).unwrap();
|
||||
let mut initial_cpu = cpu.clone();
|
||||
|
||||
let result = step_cpu_and_assert(&mut cpu, &system, case, args.check_extra_flags);
|
||||
let result = step_cpu_and_assert(&mut cpu, &system, io_bus, case, args.check_extra_flags);
|
||||
|
||||
match result {
|
||||
Ok(()) => Ok(()),
|
||||
|
||||
7
todo.txt
7
todo.txt
@ -1,4 +1,11 @@
|
||||
|
||||
* I like making address adapters like this (below)
|
||||
* you could have busport take a closure or something which translates the address, and returns an error that will be passed up if it occurs
|
||||
in order to implement the correct behaviour for address exceptions in 68k, transparently
|
||||
|
||||
* should you make a means of storing different kinds of buses?
|
||||
* should you make buses hide their RcRefCell?
|
||||
|
||||
* address repeater on ym2612 doesn't seem to work the same, when it's on the 68000 device. The Z80 device doesn't have an affect, but maybe it's not being used
|
||||
* sound doesn't work on a lot of games... is it a problem with the Z80 accessing the YM2612, or the lack of YM timers? or something else?
|
||||
* make the ym generate audio in sync so the DAC timings can be more accurate
|
||||
|
||||
Loading…
Reference in New Issue
Block a user