diff --git a/src/cpus/m68k/decode.rs b/src/cpus/m68k/decode.rs
index e2544e3..afee24e 100644
--- a/src/cpus/m68k/decode.rs
+++ b/src/cpus/m68k/decode.rs
@@ -238,9 +238,9 @@ impl M68kDecoder {
                         _ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
                     }
                 } else if ins_0f00 == 0x800 || ins_0f00 == 0x900 {
-                    let subselect = (ins & 0x01C0) >> 6;
+                    let opmode = (ins & 0x01C0) >> 6;
                     let mode = get_low_mode(ins);
-                    match (subselect, mode) {
+                    match (opmode, mode) {
                         (0b000, 0b001) if self.cputype >= M68kType::MC68020 => {
                             let data = self.read_instruction_long(memory)? as i32;
                             Ok(Instruction::LINK(get_low_reg(ins), data))
diff --git a/src/cpus/m68k/execute.rs b/src/cpus/m68k/execute.rs
index afd4a2a..342506d 100644
--- a/src/cpus/m68k/execute.rs
+++ b/src/cpus/m68k/execute.rs
@@ -381,8 +381,8 @@ impl M68k {
                 let existing = get_value_sized(self.state.d_reg[dest as usize], Size::Long);
                 let (remainder, quotient) = match sign {
                     Sign::Signed => {
-                        let value = sign_extend_to_long(value, Size::Word) as u32;
-                        (existing % value, existing / value)
+                        let value = sign_extend_to_long(value, Size::Word) as i32;
+                        ((existing as i32 % value) as u32, (existing as i32 / value) as u32)
                     },
                     Sign::Unsigned => (existing % value, existing / value),
                 };
diff --git a/src/cpus/m68k/instructions.rs b/src/cpus/m68k/instructions.rs
index e53793d..149571a 100644
--- a/src/cpus/m68k/instructions.rs
+++ b/src/cpus/m68k/instructions.rs
@@ -439,7 +439,7 @@ impl fmt::Display for Instruction {
             Instruction::EORtoCCR(value) => write!(f, "eorb\t{:02x}, %ccr", value),
             Instruction::EORtoSR(value) => write!(f, "eorw\t{:04x}, %sr", value),
             Instruction::EXG(src, dest) => write!(f, "exg\t{}, {}", src, dest),
-            Instruction::EXT(reg, from_size, to_size) => write!(f, "ext{}{}\t%d{}", from_size, to_size, reg),
+            Instruction::EXT(reg, from_size, to_size) => write!(f, "ext{}{}\t%d{}", if *from_size == Size::Byte && *to_size == Size::Long { "b" } else { "" }, to_size, reg),
 
             Instruction::ILLEGAL => write!(f, "illegal"),
 
diff --git a/src/cpus/m68k/tests.rs b/src/cpus/m68k/tests.rs
index 09a25f7..3e9a54c 100644
--- a/src/cpus/m68k/tests.rs
+++ b/src/cpus/m68k/tests.rs
@@ -753,6 +753,14 @@ mod execute_tests {
             init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00040000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
             fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x007101C3, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
         },
+        TestCase {
+            name: "divs",
+            ins: Instruction::DIVW(Target::Immediate(48), 0, Sign::Signed),
+            data: &[ 0x81FC, 0x0030 ],
+            cputype: M68kType::MC68010,
+            init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFEB00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
+            fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF90, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
+        },
         TestCase {
             name: "eori",
             ins: Instruction::EOR(Target::DirectDReg(1), Target::DirectDReg(0), Size::Long),