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Added Z80 timings, and enabled check in rad tests

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This commit is contained in:
transistor 2023-05-15 21:13:52 -07:00
parent f205e231b6
commit 64b18662d5
10 changed files with 1650 additions and 28 deletions
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7
emulator/cpus/z80/src/decode.rs
View File

@ -9,7 +9,6 @@ pub struct Z80Decoder {
pub start: u16, pub start: u16,
pub end: u16, pub end: u16,
pub instruction: Instruction, pub instruction: Instruction,
pub execution_time: u16,
} }
impl Default for Z80Decoder { impl Default for Z80Decoder {
@ -19,7 +18,6 @@ impl Default for Z80Decoder {
start: 0, start: 0,
end: 0, end: 0,
instruction: Instruction::NOP, instruction: Instruction::NOP,
execution_time: 0,
} }
} }
} }
@ -29,7 +27,6 @@ impl Z80Decoder {
self.clock = clock; self.clock = clock;
self.start = start; self.start = start;
self.end = start; self.end = start;
self.execution_time = 0;
self.instruction = self.decode_one(memory)?; self.instruction = self.decode_one(memory)?;
Ok(()) Ok(())
} }
@ -509,20 +506,18 @@ impl Z80Decoder {
fn read_instruction_byte(&mut self, device: &mut dyn Addressable) -> Result<u8, Error> { fn read_instruction_byte(&mut self, device: &mut dyn Addressable) -> Result<u8, Error> {
let byte = device.read_u8(self.clock, self.end as Address)?; let byte = device.read_u8(self.clock, self.end as Address)?;
self.end = self.end.wrapping_add(1); self.end = self.end.wrapping_add(1);
self.execution_time += 4;
Ok(byte) Ok(byte)
} }
fn read_instruction_word(&mut self, device: &mut dyn Addressable) -> Result<u16, Error> { fn read_instruction_word(&mut self, device: &mut dyn Addressable) -> Result<u16, Error> {
let word = device.read_leu16(self.clock, self.end as Address)?; let word = device.read_leu16(self.clock, self.end as Address)?;
self.end = self.end.wrapping_add(2); self.end = self.end.wrapping_add(2);
self.execution_time += 8;
Ok(word) Ok(word)
} }
pub fn format_instruction_bytes(&mut self, memory: &mut dyn Addressable) -> String { pub fn format_instruction_bytes(&mut self, memory: &mut dyn Addressable) -> String {
let ins_data: String = let ins_data: String =
(0..(self.end - self.start)).map(|offset| (0..self.end.saturating_sub(self.start)).map(|offset|
format!("{:02x} ", memory.read_u8(self.clock, (self.start + offset) as Address).unwrap()) format!("{:02x} ", memory.read_u8(self.clock, (self.start + offset) as Address).unwrap())
).collect(); ).collect();
ins_data ins_data

45
emulator/cpus/z80/src/execute.rs
View File

@ -1,8 +1,9 @@
use moa_core::{System, Error, ErrorType, ClockDuration, Address, Steppable, Addressable, Interruptable, Debuggable, Transmutable, read_beu16, write_beu16}; use moa_core::{System, Error, ErrorType, ClockTime, ClockDuration, Address, Steppable, Addressable, Interruptable, Debuggable, Transmutable, read_beu16, write_beu16};
use crate::instructions::{Condition, Instruction, LoadTarget, Target, Register, InterruptMode, RegisterPair, IndexRegister, SpecialRegister, IndexRegisterHalf, Size, Direction, UndocumentedCopy}; use crate::instructions::{Condition, Instruction, LoadTarget, Target, Register, InterruptMode, RegisterPair, IndexRegister, SpecialRegister, IndexRegisterHalf, Size, Direction, UndocumentedCopy};
use crate::state::{Z80, Status, Flags}; use crate::state::{Z80, Status, Flags};
use crate::timing::Z80InstructionCycles;
const DEV_NAME: &str = "z80-cpu"; const DEV_NAME: &str = "z80-cpu";
@ -53,9 +54,24 @@ impl Transmutable for Z80 {
} }
#[derive(Clone)]
pub struct Z80Executor {
pub current_clock: ClockTime,
pub took_branch: bool,
}
impl Z80Executor {
pub fn at_time(current_clock: ClockTime) -> Self {
Self {
current_clock,
took_branch: false,
}
}
}
impl Z80 { impl Z80 {
pub fn step_internal(&mut self, system: &System) -> Result<u16, Error> { pub fn step_internal(&mut self, system: &System) -> Result<u16, Error> {
self.current_clock = system.clock; self.executor = Z80Executor::at_time(system.clock);
match self.state.status { match self.state.status {
Status::Init => self.init(), Status::Init => self.init(),
Status::Halted => Err(Error::new("CPU stopped")), Status::Halted => Err(Error::new("CPU stopped")),
@ -63,7 +79,6 @@ impl Z80 {
match self.cycle_one(system) { match self.cycle_one(system) {
Ok(clocks) => Ok(clocks), Ok(clocks) => Ok(clocks),
Err(Error { err: ErrorType::Processor, .. }) => { Err(Error { err: ErrorType::Processor, .. }) => {
//self.exception(system, native as u8, false)?;
Ok(4) Ok(4)
}, },
Err(err) => Err(err), Err(err) => Err(err),
@ -86,13 +101,13 @@ impl Z80 {
pub fn cycle_one(&mut self, system: &System) -> Result<u16, Error> { pub fn cycle_one(&mut self, system: &System) -> Result<u16, Error> {
self.decode_next()?; self.decode_next()?;
self.execute_current()?; self.execute_current()?;
//self.check_pending_interrupts(system)?;
self.check_breakpoints(system); self.check_breakpoints(system);
Ok(self.decoder.execution_time) Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction)?
.calculate_cycles(self.executor.took_branch))
} }
pub fn decode_next(&mut self) -> Result<(), Error> { pub fn decode_next(&mut self) -> Result<(), Error> {
self.decoder.decode_at(&mut self.port, self.current_clock, self.state.pc)?; self.decoder.decode_at(&mut self.port, self.executor.current_clock, self.state.pc)?;
self.increment_refresh(self.decoder.end.saturating_sub(self.decoder.start) as u8); self.increment_refresh(self.decoder.end.saturating_sub(self.decoder.start) as u8);
self.state.pc = self.decoder.end; self.state.pc = self.decoder.end;
Ok(()) Ok(())
@ -279,6 +294,7 @@ impl Z80 {
fn execute_callcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> { fn execute_callcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> {
if self.get_current_condition(cond) { if self.get_current_condition(cond) {
self.executor.took_branch = true;
self.push_word(self.decoder.end)?; self.push_word(self.decoder.end)?;
self.state.pc = addr; self.state.pc = addr;
} }
@ -395,6 +411,7 @@ impl Z80 {
self.set_register_value(Register::B, result); self.set_register_value(Register::B, result);
if result != 0 { if result != 0 {
self.executor.took_branch = true;
self.state.pc = self.state.pc.wrapping_add_signed(offset as i16); self.state.pc = self.state.pc.wrapping_add_signed(offset as i16);
} }
Ok(()) Ok(())
@ -528,6 +545,7 @@ impl Z80 {
fn execute_jpcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> { fn execute_jpcc(&mut self, cond: Condition, addr: u16) -> Result<(), Error> {
if self.get_current_condition(cond) { if self.get_current_condition(cond) {
self.executor.took_branch = true;
self.state.pc = addr; self.state.pc = addr;
} }
Ok(()) Ok(())
@ -540,6 +558,7 @@ impl Z80 {
fn execute_jrcc(&mut self, cond: Condition, offset: i8) -> Result<(), Error> { fn execute_jrcc(&mut self, cond: Condition, offset: i8) -> Result<(), Error> {
if self.get_current_condition(cond) { if self.get_current_condition(cond) {
self.executor.took_branch = true;
self.state.pc = self.state.pc.wrapping_add_signed(offset as i16); self.state.pc = self.state.pc.wrapping_add_signed(offset as i16);
} }
Ok(()) Ok(())
@ -593,6 +612,7 @@ impl Z80 {
if (self.decoder.instruction == Instruction::LDIR || self.decoder.instruction == Instruction::LDDR) if (self.decoder.instruction == Instruction::LDIR || self.decoder.instruction == Instruction::LDDR)
&& count != 0 && count != 0
{ {
self.executor.took_branch = true;
self.state.pc -= 2; self.state.pc -= 2;
} }
Ok(()) Ok(())
@ -685,6 +705,7 @@ impl Z80 {
fn execute_retcc(&mut self, cond: Condition) -> Result<(), Error> { fn execute_retcc(&mut self, cond: Condition) -> Result<(), Error> {
if self.get_current_condition(cond) { if self.get_current_condition(cond) {
self.executor.took_branch = true;
self.state.pc = self.pop_word()?; self.state.pc = self.pop_word()?;
} }
Ok(()) Ok(())
@ -1083,28 +1104,28 @@ impl Z80 {
fn read_port_u8(&mut self, addr: u16) -> Result<u8, Error> { fn read_port_u8(&mut self, addr: u16) -> Result<u8, Error> {
self.increment_refresh(1); self.increment_refresh(1);
self.port.read_u8(self.current_clock, addr as Address) self.port.read_u8(self.executor.current_clock, addr as Address)
} }
fn write_port_u8(&mut self, addr: u16, value: u8) -> Result<(), Error> { fn write_port_u8(&mut self, addr: u16, value: u8) -> Result<(), Error> {
self.increment_refresh(1); self.increment_refresh(1);
self.port.write_u8(self.current_clock, addr as Address, value) self.port.write_u8(self.executor.current_clock, addr as Address, value)
} }
fn read_port_u16(&mut self, addr: u16) -> Result<u16, Error> { fn read_port_u16(&mut self, addr: u16) -> Result<u16, Error> {
self.increment_refresh(2); self.increment_refresh(2);
self.port.read_leu16(self.current_clock, addr as Address) self.port.read_leu16(self.executor.current_clock, addr as Address)
} }
fn write_port_u16(&mut self, addr: u16, value: u16) -> Result<(), Error> { fn write_port_u16(&mut self, addr: u16, value: u16) -> Result<(), Error> {
self.increment_refresh(2); self.increment_refresh(2);
self.port.write_leu16(self.current_clock, addr as Address, value) self.port.write_leu16(self.executor.current_clock, addr as Address, value)
} }
fn read_ioport_value(&mut self, upper: u8, lower: u8) -> Result<u8, Error> { fn read_ioport_value(&mut self, upper: u8, lower: u8) -> Result<u8, Error> {
let addr = ((upper as Address) << 8) | (lower as Address); let addr = ((upper as Address) << 8) | (lower as Address);
if let Some(io) = self.ioport.as_mut() { if let Some(io) = self.ioport.as_mut() {
Ok(io.read_u8(self.current_clock, addr)?) Ok(io.read_u8(self.executor.current_clock, addr)?)
} else { } else {
Ok(0) Ok(0)
} }
@ -1113,7 +1134,7 @@ impl Z80 {
fn write_ioport_value(&mut self, upper: u8, lower: u8, value: u8) -> Result<(), Error> { fn write_ioport_value(&mut self, upper: u8, lower: u8, value: u8) -> Result<(), Error> {
let addr = ((upper as Address) << 8) | (lower as Address); let addr = ((upper as Address) << 8) | (lower as Address);
if let Some(io) = self.ioport.as_mut() { if let Some(io) = self.ioport.as_mut() {
io.write_u8(self.current_clock, addr, value)? io.write_u8(self.executor.current_clock, addr, value)?
} }
Ok(()) Ok(())
} }

10
emulator/cpus/z80/src/instructions.rs
View File

@ -201,4 +201,14 @@ impl From<u8> for InterruptMode {
} }
} }
impl RegisterPair {
pub(crate) fn is_index_reg(&self) -> bool {
match self {
RegisterPair::IX |
RegisterPair::IY => true,
_ => false,
}
}
}

5
emulator/cpus/z80/src/lib.rs
View File

@ -1,9 +1,10 @@
pub mod state; pub mod debugger;
pub mod decode; pub mod decode;
pub mod execute; pub mod execute;
pub mod debugger;
pub mod instructions; pub mod instructions;
pub mod state;
pub mod timing;
pub use self::state::{Z80, Z80Type}; pub use self::state::{Z80, Z80Type};

6
emulator/cpus/z80/src/state.rs
View File

@ -3,6 +3,7 @@ use moa_core::{ClockTime, Address, BusPort, Signal, Frequency};
use crate::decode::Z80Decoder; use crate::decode::Z80Decoder;
use crate::debugger::Z80Debugger; use crate::debugger::Z80Debugger;
use crate::execute::Z80Executor;
use crate::instructions::{Register, InterruptMode}; use crate::instructions::{Register, InterruptMode};
@ -93,11 +94,11 @@ pub struct Z80 {
pub state: Z80State, pub state: Z80State,
pub decoder: Z80Decoder, pub decoder: Z80Decoder,
pub debugger: Z80Debugger, pub debugger: Z80Debugger,
pub executor: Z80Executor,
pub port: BusPort, pub port: BusPort,
pub ioport: Option<BusPort>, pub ioport: Option<BusPort>,
pub reset: Signal<bool>, pub reset: Signal<bool>,
pub bus_request: Signal<bool>, pub bus_request: Signal<bool>,
pub current_clock: ClockTime,
} }
impl Z80 { impl Z80 {
@ -108,11 +109,11 @@ impl Z80 {
state: Z80State::default(), state: Z80State::default(),
decoder: Z80Decoder::default(), decoder: Z80Decoder::default(),
debugger: Z80Debugger::default(), debugger: Z80Debugger::default(),
executor: Z80Executor::at_time(ClockTime::START),
port, port,
ioport, ioport,
reset: Signal::new(false), reset: Signal::new(false),
bus_request: Signal::new(false), bus_request: Signal::new(false),
current_clock: ClockTime::START,
} }
} }
@ -121,6 +122,7 @@ impl Z80 {
self.state = Z80State::default(); self.state = Z80State::default();
self.decoder = Z80Decoder::default(); self.decoder = Z80Decoder::default();
self.debugger = Z80Debugger::default(); self.debugger = Z80Debugger::default();
self.executor = Z80Executor::at_time(ClockTime::START);
} }
pub fn dump_state(&mut self, clock: ClockTime) { pub fn dump_state(&mut self, clock: ClockTime) {

299
emulator/cpus/z80/src/timing.rs Normal file
View File

@ -0,0 +1,299 @@
use moa_core::Error;
use crate::instructions::{Instruction, Target, LoadTarget, RegisterPair};
pub enum Z80InstructionCycles {
Single(u16),
Branch {
taken: u16,
not_taken: u16
},
Repeating {
repeating: u16,
terminating: u16,
},
}
impl Z80InstructionCycles {
pub fn calculate_cycles(&self, took_branch: bool) -> u16 {
match self {
Z80InstructionCycles::Single(cycles) => *cycles,
Z80InstructionCycles::Branch { taken, not_taken } => if took_branch { *taken } else { *not_taken },
Z80InstructionCycles::Repeating { repeating, terminating } => if took_branch { *repeating } else { *terminating },
}
}
pub fn from_instruction(instruction: &Instruction) -> Result<Z80InstructionCycles, Error> {
let cycles = match instruction {
Instruction::ADCa(target) |
Instruction::ADDa(target) |
Instruction::AND(target) |
Instruction::CP(target) |
Instruction::SBCa(target) |
Instruction::SUB(target) |
Instruction::OR(target) |
Instruction::XOR(target) => {
match target {
// TODO the undocumented DD version of this instruction is actually 8 cycles
Target::DirectReg(_) => 4,
Target::IndirectReg(_) => 7,
Target::Immediate(_) => 7,
Target::IndirectOffset(_, _) => 19,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::ADC16(_, _) |
Instruction::SBC16(_, _) => 15,
Instruction::ADD16(dest_pair, _) => {
if !dest_pair.is_index_reg() {
11
} else {
15
}
},
Instruction::BIT(_, target) => {
match target {
Target::DirectReg(_) => 8,
Target::IndirectReg(_) => 12,
Target::IndirectOffset(_, _) => 20,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::CALL(_) => 17,
Instruction::CALLcc(_, _) => {
return Ok(Z80InstructionCycles::Branch {
taken: 17,
not_taken: 10,
});
},
Instruction::CCF => 4,
Instruction::CPD |
Instruction::CPI |
Instruction::IND |
Instruction::INI |
Instruction::LDD |
Instruction::LDI |
Instruction::OUTD |
Instruction::OUTI => 16,
Instruction::CPDR |
Instruction::CPIR |
Instruction::INDR |
Instruction::INIR |
Instruction::LDDR |
Instruction::LDIR |
Instruction::OTDR |
Instruction::OTIR => {
return Ok(Z80InstructionCycles::Repeating {
repeating: 21,
terminating: 16,
})
},
Instruction::CPL => 4,
Instruction::DAA => 4,
Instruction::DEC8(target) |
Instruction::INC8(target) => {
// TODO the undocumented DD version of this instruction is actually 8 cycles
match target {
Target::DirectReg(_) => 4,
Target::IndirectReg(_) => 11,
Target::IndirectOffset(_, _) => 23,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::DEC16(regpair) |
Instruction::INC16(regpair) => {
if !regpair.is_index_reg() {
6
} else {
10
}
},
Instruction::DI |
Instruction::EI => 4,
Instruction::DJNZ(_) => {
return Ok(Z80InstructionCycles::Branch {
taken: 13,
not_taken: 8,
});
},
Instruction::EXX => 4,
Instruction::EXafaf => 4,
Instruction::EXhlde => 4,
Instruction::EXsp(regpair) => {
if !regpair.is_index_reg() {
19
} else {
23
}
},
Instruction::HALT => 4,
Instruction::IM(_) => 8,
Instruction::INic(_) |
Instruction::INicz |
Instruction::OUTic(_) |
Instruction::OUTicz => 12,
Instruction::INx(_) |
Instruction::OUTx(_) => 11,
Instruction::JP(_) => 10,
Instruction::JR(_) => 12,
Instruction::JPIndirect(regpair) => {
if !regpair.is_index_reg() {
4
} else {
8
}
},
Instruction::JPcc(_, _) => 10,
Instruction::JRcc(_, _) => {
return Ok(Z80InstructionCycles::Branch {
taken: 12,
not_taken: 7,
});
},
Instruction::LD(dest, src) => {
// TODO the undocumented DD version of this instruction is actually 8 cycles
match (dest, src) {
// 8-Bit Operations
(LoadTarget::DirectRegByte(_), LoadTarget::DirectRegByte(_)) => 4,
(LoadTarget::DirectRegByte(_), LoadTarget::ImmediateByte(_)) => 7,
(LoadTarget::IndirectRegByte(_), LoadTarget::ImmediateByte(_)) => 10,
(LoadTarget::IndirectOffsetByte(_, _), _) |
(_, LoadTarget::IndirectOffsetByte(_, _)) => 19,
(_, LoadTarget::IndirectRegByte(_)) |
(LoadTarget::IndirectRegByte(_), _) => 7,
(_, LoadTarget::IndirectByte(_)) |
(LoadTarget::IndirectByte(_), _) => 13,
// 16-Bit Operations
(LoadTarget::DirectRegWord(regpair), LoadTarget::ImmediateWord(_)) |
(LoadTarget::ImmediateWord(_), LoadTarget::DirectRegWord(regpair)) => {
if !regpair.is_index_reg() {
10
} else {
14
}
},
(LoadTarget::DirectRegWord(_), LoadTarget::DirectRegWord(regpair)) => {
if !regpair.is_index_reg() {
6
} else {
10
}
},
(LoadTarget::IndirectWord(_), LoadTarget::DirectRegWord(RegisterPair::HL)) |
(LoadTarget::DirectRegWord(RegisterPair::HL), LoadTarget::IndirectWord(_)) => 16,
(LoadTarget::IndirectWord(_), _) |
(_, LoadTarget::IndirectWord(_)) => 20,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::LDsr(_, _) => 9,
Instruction::NEG => 8,
Instruction::NOP => 4,
Instruction::POP(regpair) => {
if !regpair.is_index_reg() {
10
} else {
14
}
},
Instruction::PUSH(regpair) => {
if !regpair.is_index_reg() {
11
} else {
15
}
},
Instruction::RES(_, target, _) |
Instruction::SET(_, target, _) => {
match target {
Target::DirectReg(_) => 8,
Target::IndirectReg(_) => 15,
Target::IndirectOffset(_, _) => 23,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::RET => 10,
Instruction::RETI => 14,
Instruction::RETN => 14,
Instruction::RETcc(_) => {
return Ok(Z80InstructionCycles::Branch {
taken: 11,
not_taken: 5,
});
},
Instruction::RL(target, _) |
Instruction::RLC(target, _) |
Instruction::RR(target, _) |
Instruction::RRC(target, _) |
Instruction::SLA(target, _) |
Instruction::SLL(target, _) |
Instruction::SRA(target, _) |
Instruction::SRL(target, _) => {
match target {
Target::DirectReg(_) => 8,
Target::IndirectReg(_) => 15,
Target::IndirectOffset(_, _) => 23,
_ => return Err(Error::new(format!("unexpected instruction: {:?}", instruction))),
}
},
Instruction::RLA |
Instruction::RLCA |
Instruction::RRA |
Instruction::RRCA => 4,
Instruction::RLD => 18,
Instruction::RRD => 18,
Instruction::RST(_) => 11,
Instruction::SCF => 4,
};
Ok(Z80InstructionCycles::Single(cycles))
}
}

10
tests/rad_tests/latest.txt
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@ -1,4 +1,4 @@
Last run on 2023-05-14 at commit aaa7952dd0cf0ab6e33946ce0ae1aa91920e5405 Last run on 2023-05-15 at commit f205e231b62d62c72186c1d9f5277e2bce693380
00.json completed, all passed! 00.json completed, all passed!
01.json completed, all passed! 01.json completed, all passed!
@ -568,7 +568,7 @@ ed 73.json completed, all passed!
ed 74.json completed, all passed! ed 74.json completed, all passed!
ed 75.json completed, all passed! ed 75.json completed, all passed!
ed 76.json completed, all passed! ed 76.json completed, all passed!
ed 77.json completed, all passed! ed 77.json completed: 0 passed, 1000 FAILED
ed 78.json completed, all passed! ed 78.json completed, all passed!
ed 79.json completed, all passed! ed 79.json completed, all passed!
ed 7a.json completed, all passed! ed 7a.json completed, all passed!
@ -576,7 +576,7 @@ ed 7b.json completed, all passed!
ed 7c.json completed, all passed! ed 7c.json completed, all passed!
ed 7d.json completed, all passed! ed 7d.json completed, all passed!
ed 7e.json completed, all passed! ed 7e.json completed, all passed!
ed 7f.json completed, all passed! ed 7f.json completed: 0 passed, 1000 FAILED
ed a0.json completed, all passed! ed a0.json completed, all passed!
ed a1.json completed: 0 passed, 1000 FAILED ed a1.json completed: 0 passed, 1000 FAILED
ed a2.json completed: 13 passed, 987 FAILED ed a2.json completed: 13 passed, 987 FAILED
@ -643,5 +643,5 @@ fd f9.json completed, all passed!
fe.json completed, all passed! fe.json completed, all passed!
ff.json completed, all passed! ff.json completed, all passed!
passed: 629560, failed: 12440, total 98% passed: 627560, failed: 14440, total 98%
completed in 0m 32s completed in 0m 35s

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tests/rad_tests/progress/2023-05-13-7-without-undoc-fixed-refresh-sim.txt Normal file
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@ -0,0 +1,647 @@
Last run on 2023-05-13 at commit f3d1fd0ae2410a164c92150cc3caa0f525cbb4b7
00.json completed, all passed!
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passed: 626998, failed: 15002, total 98%
completed in 0m 32s

647
tests/rad_tests/progress/2023-05-14-without-undoc-fixed-memory-wrapping.txt Normal file
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@ -0,0 +1,647 @@
Last run on 2023-05-14 at commit aaa7952dd0cf0ab6e33946ce0ae1aa91920e5405
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passed: 629560, failed: 12440, total 98%
completed in 0m 32s

2
tests/rad_tests/run_all.sh
View File

@ -7,5 +7,5 @@ RESULTS=latest.txt
cd $LOCATION cd $LOCATION
echo "Last run on $DATE at commit $COMMIT" | tee $RESULTS echo "Last run on $DATE at commit $COMMIT" | tee $RESULTS
echo "" | tee -a $RESULTS echo "" | tee -a $RESULTS
cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" | tee -a $RESULTS cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" --check-timings | tee -a $RESULTS
} }