From 6e7e315808228e03eaf8ad2e8152c087710f1d28 Mon Sep 17 00:00:00 2001 From: transistor fet Date: Fri, 22 Mar 2024 18:51:17 -0700 Subject: [PATCH] Modified for Instant as associated type in emulator-hal (#6) * Modified for Instant as associated type in emulator-hal * Updated emulator-hal to latest --- emulator/core/src/memory.rs | 5 +++-- emulator/cpus/m68k/src/debugger.rs | 10 +++++----- emulator/cpus/m68k/src/decode.rs | 10 +++++----- emulator/cpus/m68k/src/execute.rs | 12 ++++++------ emulator/cpus/m68k/src/memory.rs | 18 +++++++++--------- emulator/cpus/m68k/src/moa.rs | 4 ++-- emulator/cpus/m68k/tests/decode_tests.rs | 4 ++-- emulator/cpus/m68k/tests/execute_tests.rs | 2 +- .../cpus/m68k/tests/musashi_timing_tests.rs | 2 +- emulator/cpus/m68k/tests/timing_tests.rs | 2 +- emulator/libraries/emulator-hal | 2 +- 11 files changed, 36 insertions(+), 35 deletions(-) diff --git a/emulator/core/src/memory.rs b/emulator/core/src/memory.rs index 1d841e2..b5e545b 100644 --- a/emulator/core/src/memory.rs +++ b/emulator/core/src/memory.rs @@ -388,7 +388,7 @@ pub fn dump_slice(data: &[u8], mut count: usize) { pub fn dump_memory(bus: &mut Bus, clock: Instant, addr: Address, count: Address) where - Bus: BusAccess, + Bus: BusAccess, Address: From + Into + Copy, Instant: Copy, { @@ -416,7 +416,8 @@ use emulator_hal::bus::{self, BusAccess}; impl bus::Error for Error {} -impl BusAccess for &mut dyn Addressable { +impl BusAccess for &mut dyn Addressable { + type Instant = Instant; type Error = Error; fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result { diff --git a/emulator/cpus/m68k/src/debugger.rs b/emulator/cpus/m68k/src/debugger.rs index d018421..d438944 100644 --- a/emulator/cpus/m68k/src/debugger.rs +++ b/emulator/cpus/m68k/src/debugger.rs @@ -28,9 +28,9 @@ pub enum M68kInfo { State, } -impl Inspect for M68k +impl Inspect for M68k where - Bus: BusAccess, + Bus: BusAccess, BusError: bus::Error, Writer: fmt::Write, { @@ -57,9 +57,9 @@ where } /// Control the execution of a CPU device for debugging purposes -impl Debug for M68k +impl Debug for M68k where - Bus: BusAccess, + Bus: BusAccess, BusError: bus::Error, Instant: time::Instant, Writer: fmt::Write, @@ -103,7 +103,7 @@ pub struct M68kDebugger { impl<'a, Bus, BusError, Instant> M68kCycleExecutor<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, Instant: Copy, { pub fn check_breakpoints(&mut self) -> Result<(), M68kError> { diff --git a/emulator/cpus/m68k/src/decode.rs b/emulator/cpus/m68k/src/decode.rs index 29cc270..fd2c891 100644 --- a/emulator/cpus/m68k/src/decode.rs +++ b/emulator/cpus/m68k/src/decode.rs @@ -41,7 +41,7 @@ pub struct M68kDecoder { pub struct InstructionDecoding<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, { pub(crate) bus: &'a mut Bus, pub(crate) memory: &'a mut M68kBusPort, @@ -81,7 +81,7 @@ where start: u32, ) -> Result<(), M68kError> where - Bus: BusAccess, + Bus: BusAccess, { self.init(is_supervisor, start); let mut decoding = InstructionDecoding { @@ -95,7 +95,7 @@ where pub fn dump_disassembly(&mut self, bus: &mut Bus, memory: &mut M68kBusPort, start: u32, length: u32) where - Bus: BusAccess, + Bus: BusAccess, { let mut next = start; while next < (start + length) { @@ -117,7 +117,7 @@ where pub fn dump_decoded(&mut self, clock: Instant, bus: &mut Bus) where - Bus: BusAccess, + Bus: BusAccess, { let ins_data: Result> = (0..((self.end - self.start) / 2)) .map(|offset| Ok(format!("{:04x} ", bus.read_beu16(clock, self.start + (offset * 2)).unwrap()))) @@ -128,7 +128,7 @@ where impl<'a, Bus, Instant> InstructionDecoding<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, Instant: Copy, { #[inline] diff --git a/emulator/cpus/m68k/src/execute.rs b/emulator/cpus/m68k/src/execute.rs index 6b75424..e2fadb7 100644 --- a/emulator/cpus/m68k/src/execute.rs +++ b/emulator/cpus/m68k/src/execute.rs @@ -61,7 +61,7 @@ where #[inline] pub fn begin(self, cpu: &mut M68k, bus: Bus) -> M68kCycleExecutor<'_, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, { cpu.stats.cycle_number = cpu.stats.cycle_number.wrapping_add(1); @@ -74,9 +74,9 @@ where } } -impl Step for M68k +impl Step for M68k where - Bus: BusAccess, + Bus: BusAccess, BusError: bus::Error, Instant: time::Instant, { @@ -110,7 +110,7 @@ where pub struct M68kCycleExecutor<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, { pub state: &'a mut M68kState, pub bus: Bus, @@ -120,7 +120,7 @@ where impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, Instant: Copy, { pub fn end(self) -> M68kCycle { @@ -130,7 +130,7 @@ where impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant> where - Bus: BusAccess, + Bus: BusAccess, Instant: Copy, { #[inline] diff --git a/emulator/cpus/m68k/src/memory.rs b/emulator/cpus/m68k/src/memory.rs index 41e0004..f95f194 100644 --- a/emulator/cpus/m68k/src/memory.rs +++ b/emulator/cpus/m68k/src/memory.rs @@ -173,7 +173,7 @@ where data: &mut [u8], ) -> Result<(), M68kError> where - Bus: BusAccess, + Bus: BusAccess, { let addr = addr & self.address_mask; for i in (0..data.len()).step_by(self.data_bytewidth) { @@ -193,7 +193,7 @@ where data: &[u8], ) -> Result<(), M68kError> where - Bus: BusAccess, + Bus: BusAccess, { let addr = addr & self.address_mask; for i in (0..data.len()).step_by(self.data_bytewidth) { @@ -207,7 +207,7 @@ where fn read_sized(&mut self, bus: &mut Bus, addr: M68kAddress, size: Size) -> Result> where - Bus: BusAccess, + Bus: BusAccess, { let mut data = [0; 4]; match size { @@ -226,7 +226,7 @@ where value: u32, ) -> Result<(), M68kError> where - Bus: BusAccess, + Bus: BusAccess, { let data = value.to_be_bytes(); match size { @@ -244,7 +244,7 @@ where size: Size, ) -> Result> where - Bus: BusAccess, + Bus: BusAccess, { self.start_request(is_supervisor, addr, size, MemAccess::Read, MemType::Data, false)?; self.read_sized(bus, addr, size) @@ -259,7 +259,7 @@ where value: u32, ) -> Result<(), M68kError> where - Bus: BusAccess, + Bus: BusAccess, { self.start_request(is_supervisor, addr, size, MemAccess::Write, MemType::Data, false)?; self.write_sized(bus, addr, size, value) @@ -272,7 +272,7 @@ where addr: u32, ) -> Result> where - Bus: BusAccess, + Bus: BusAccess, { self.request.instruction(is_supervisor, addr)?; Ok(self.read_sized(bus, addr, Size::Word)? as u16) @@ -285,7 +285,7 @@ where addr: u32, ) -> Result> where - Bus: BusAccess, + Bus: BusAccess, { self.request.instruction(is_supervisor, addr)?; self.read_sized(bus, addr, Size::Long) @@ -327,7 +327,7 @@ fn validate_address(addr: u32) -> Result> { pub fn dump_memory(bus: &mut Bus, clock: Instant, addr: Address, count: Address) where - Bus: BusAccess, + Bus: BusAccess, Address: From + Into + Copy, Instant: Copy, { diff --git a/emulator/cpus/m68k/src/moa.rs b/emulator/cpus/m68k/src/moa.rs index 8b3d091..7ab9703 100644 --- a/emulator/cpus/m68k/src/moa.rs +++ b/emulator/cpus/m68k/src/moa.rs @@ -10,7 +10,7 @@ impl Steppable for M68k { let cycle = M68kCycle::new(self, system.clock); let mut bus = system.bus.borrow_mut(); - let mut adapter: bus::BusAdapter = + let mut adapter: bus::BusAdapter = bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err); let mut executor = cycle.begin(self, &mut adapter); @@ -99,7 +99,7 @@ impl Debuggable for M68k { let mut memory = M68kBusPort::from_info(&self.info, system.clock); let mut bus = system.bus.borrow_mut(); - let mut adapter: bus::BusAdapter = + let mut adapter: bus::BusAdapter = bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err); decoder.dump_disassembly(&mut adapter, &mut memory, addr as u32, count as u32); diff --git a/emulator/cpus/m68k/tests/decode_tests.rs b/emulator/cpus/m68k/tests/decode_tests.rs index e586e84..b0843b9 100644 --- a/emulator/cpus/m68k/tests/decode_tests.rs +++ b/emulator/cpus/m68k/tests/decode_tests.rs @@ -81,10 +81,10 @@ fn init_decode_test(cputype: M68kType) -> (M68k, M68kCycle, Me (cpu, cycle, memory) } -fn load_memory>(memory: &mut Bus, data: &[u16]) { +fn load_memory>(memory: &mut Bus, data: &[u16]) { let mut addr = INIT_ADDR; for word in data { - memory.write_beu16(Instant::START, addr, *word).unwrap(); + memory.write_beu16(Bus::Instant::START, addr, *word).unwrap(); addr += 2; } } diff --git a/emulator/cpus/m68k/tests/execute_tests.rs b/emulator/cpus/m68k/tests/execute_tests.rs index 3b0a4d3..a26e221 100644 --- a/emulator/cpus/m68k/tests/execute_tests.rs +++ b/emulator/cpus/m68k/tests/execute_tests.rs @@ -76,7 +76,7 @@ fn build_state(state: &TestState) -> M68kState { new_state } -fn load_memory>(bus: &mut Bus, data: &[u16]) { +fn load_memory>(bus: &mut Bus, data: &[u16]) { for i in 0..data.len() { bus.write_beu16(Instant::START, (i << 1) as u32, data[i]).unwrap(); } diff --git a/emulator/cpus/m68k/tests/musashi_timing_tests.rs b/emulator/cpus/m68k/tests/musashi_timing_tests.rs index 7eb8e4a..696915f 100644 --- a/emulator/cpus/m68k/tests/musashi_timing_tests.rs +++ b/emulator/cpus/m68k/tests/musashi_timing_tests.rs @@ -29,7 +29,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k, M68kCycle, Me (cpu, cycle, memory) } -fn load_memory>(bus: &mut Bus, data: &[u16]) { +fn load_memory>(bus: &mut Bus, data: &[u16]) { let mut addr = INIT_ADDR; for word in data { bus.write_beu16(Instant::START, addr, *word).unwrap(); diff --git a/emulator/cpus/m68k/tests/timing_tests.rs b/emulator/cpus/m68k/tests/timing_tests.rs index d80d911..8e00d8a 100644 --- a/emulator/cpus/m68k/tests/timing_tests.rs +++ b/emulator/cpus/m68k/tests/timing_tests.rs @@ -43,7 +43,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k, M68kCycle, Me (cpu, cycle, memory) } -fn load_memory>(bus: &mut Bus, data: &[u16]) { +fn load_memory>(bus: &mut Bus, data: &[u16]) { let mut addr = INIT_ADDR; for word in data { bus.write_beu16(Instant::START, addr, *word).unwrap(); diff --git a/emulator/libraries/emulator-hal b/emulator/libraries/emulator-hal index 1000066..2391a32 160000 --- a/emulator/libraries/emulator-hal +++ b/emulator/libraries/emulator-hal @@ -1 +1 @@ -Subproject commit 10000669524747dce101947e60f230551b26f6f8 +Subproject commit 2391a324376bdd9fa1ae9801bbe3d12f2e69fa62