mirror of
https://github.com/transistorfet/moa.git
synced 2025-04-07 18:38:42 +00:00
Added MC68020+ addressing modes
This commit is contained in:
transistor
parent
3fc76335d0
commit
731c89845e
@ -10,6 +10,8 @@ use super::instructions::{
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Direction,
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ShiftDirection,
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XRegister,
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BaseRegister,
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IndexRegister,
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RegOrImmediate,
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ControlRegister,
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Condition,
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@ -108,7 +110,7 @@ impl M68kDecoder {
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let dir = if (ins & 0x0800) == 0 { Direction::FromTarget } else { Direction::ToTarget };
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let size = if (ins & 0x0040) == 0 { Size::Word } else { Size::Long };
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let offset = sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word);
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Ok(Instruction::MOVEP(dreg, Target::IndirectARegOffset(areg, offset), size, dir))
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Ok(Instruction::MOVEP(dreg, Target::IndirectRegOffset(BaseRegister::AReg(areg), None, offset), size, dir))
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} else if (ins & 0x0100) == 0x0100 || (ins & 0x0F00) == 0x0800 {
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let bitnum = if (ins & 0x0100) == 0x0100 {
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Target::DirectDReg(get_high_reg(ins))
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@ -606,25 +608,53 @@ impl M68kDecoder {
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self.get_mode_as_target(memory, mode, reg, size)
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}
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fn get_extension_displacement(&mut self, memory: &mut dyn Addressable, select: u16) -> Result<i32, Error> {
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let result = match select {
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0b00 | 0b01 => 0,
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0b10 => sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word),
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0b11 => self.read_instruction_long(memory)? as i32,
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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};
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Ok(result)
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}
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fn decode_extension_word(&mut self, memory: &mut dyn Addressable, areg: Option<u8>) -> Result<Target, Error> {
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let brief_extension = self.read_instruction_word(memory)?;
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let use_full = (brief_extension & 0x0100) != 0;
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// Decode Index Register
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let xreg_num = ((brief_extension & 0x7000) >> 12) as u8;
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let xreg = if (brief_extension & 0x8000) == 0 { XRegister::Data(xreg_num) } else { XRegister::Address(xreg_num) };
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let xreg = if (brief_extension & 0x8000) == 0 { XRegister::DReg(xreg_num) } else { XRegister::AReg(xreg_num) };
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let size = if (brief_extension & 0x0800) == 0 { Size::Word } else { Size::Long };
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let scale = ((brief_extension & 0x0600) >> 9) as u8;
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let use_full = (brief_extension & 0x0100) != 0;
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let index_reg = IndexRegister { xreg, scale, size };
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if !use_full {
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let displacement = sign_extend_to_long((brief_extension & 0x00FF) as u32, Size::Byte);
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match areg {
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Some(areg) => Ok(Target::IndirectARegXRegOffset(areg, xreg, displacement, scale, size)),
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None => Ok(Target::IndirectPCXRegOffset(xreg, displacement, scale, size)),
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Some(areg) => Ok(Target::IndirectRegOffset(BaseRegister::AReg(areg), Some(index_reg), displacement)),
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None => Ok(Target::IndirectRegOffset(BaseRegister::PC, Some(index_reg), displacement)),
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}
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} else if self.cputype >= M68kType::MC68020 {
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let use_base = (brief_extension & 0x0080) == 0;
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let use_base_reg = (brief_extension & 0x0080) == 0;
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let use_index = (brief_extension & 0x0040) == 0;
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let use_sub_indirect = (brief_extension & 0x0007) != 0;
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let pre_not_post = (brief_extension & 0x0004) == 0;
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panic!("Not Implemented");
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let opt_base_reg = match (use_base_reg, areg) {
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(false, _) => BaseRegister::None,
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(true, None) => BaseRegister::PC,
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(true, Some(areg)) => BaseRegister::AReg(areg),
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};
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let opt_index_reg = if use_index { Some(index_reg) } else { None };
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let base_disp = self.get_extension_displacement(memory, (brief_extension & 0x0030) >> 4)?;
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let outer_disp = self.get_extension_displacement(memory, brief_extension & 0x0003)?;
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match (use_sub_indirect, pre_not_post) {
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(false, _) => Ok(Target::IndirectRegOffset(opt_base_reg, opt_index_reg, base_disp)),
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(true, true) => Ok(Target::IndirectMemoryPreindexed(opt_base_reg, opt_index_reg, base_disp, outer_disp)),
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(true, false) => Ok(Target::IndirectMemoryPostindexed(opt_base_reg, opt_index_reg, base_disp, outer_disp)),
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}
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} else {
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Err(Error::processor(Exceptions::IllegalInstruction as u32))
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}
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@ -638,8 +668,8 @@ impl M68kDecoder {
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0b011 => Target::IndirectARegInc(reg),
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0b100 => Target::IndirectARegDec(reg),
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0b101 => {
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let data = sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word);
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Target::IndirectARegOffset(reg, data)
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let displacement = sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word);
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Target::IndirectRegOffset(BaseRegister::AReg(reg), None, displacement)
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},
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0b110 => {
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self.decode_extension_word(memory, Some(reg))?
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@ -655,8 +685,8 @@ impl M68kDecoder {
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Target::IndirectMemory(value)
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},
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0b010 => {
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let data = sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word);
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Target::IndirectPCOffset(data)
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let displacement = sign_extend_to_long(self.read_instruction_word(memory)? as u32, Size::Word);
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Target::IndirectRegOffset(BaseRegister::PC, None, displacement)
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},
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0b011 => {
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self.decode_extension_word(memory, None)?
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@ -10,6 +10,8 @@ use super::instructions::{
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Direction,
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ShiftDirection,
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XRegister,
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BaseRegister,
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IndexRegister,
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RegOrImmediate,
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ControlRegister,
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Condition,
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@ -389,16 +391,16 @@ impl M68k {
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//Instruction::ILLEGAL => {
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//},
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Instruction::JMP(target) => {
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self.state.pc = self.get_target_address(target)?;
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self.state.pc = self.get_target_address(system, target)?;
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},
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Instruction::JSR(target) => {
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self.push_long(system, self.state.pc)?;
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let sp = *self.get_stack_pointer_mut();
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self.debugger.stack_tracer.push_return(sp);
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self.state.pc = self.get_target_address(target)?;
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self.state.pc = self.get_target_address(system, target)?;
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},
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Instruction::LEA(target, reg) => {
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let value = self.get_target_address(target)?;
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let value = self.get_target_address(system, target)?;
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let addr = self.get_a_reg_mut(reg);
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*addr = value;
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},
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@ -472,7 +474,7 @@ impl M68k {
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// TODO moving words requires a sign extension to 32 bits
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if size != Size::Long { return Err(Error::new("Unsupported size in MOVEM instruction")); }
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let mut addr = self.get_target_address(target)?;
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let mut addr = self.get_target_address(system, target)?;
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if dir == Direction::ToTarget {
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let mut mask = mask;
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for i in (0..8).rev() {
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@ -567,7 +569,7 @@ impl M68k {
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self.state.sr = self.state.sr | value;
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},
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Instruction::PEA(target) => {
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let value = self.get_target_address(target)?;
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let value = self.get_target_address(system, target)?;
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self.push_long(system, value)?;
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},
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//Instruction::RESET => {
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@ -697,25 +699,29 @@ impl M68k {
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*addr -= size.in_bytes();
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get_address_sized(system, *addr as Address, size)
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},
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Target::IndirectARegOffset(reg, offset) => {
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let addr = self.get_a_reg_mut(reg);
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get_address_sized(system, (*addr).wrapping_add(offset as u32) as Address, size)
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Target::IndirectRegOffset(base_reg, index_reg, displacement) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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get_address_sized(system, base_value.wrapping_add(displacement as u32).wrapping_add(index_value as u32) as Address, size)
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},
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Target::IndirectARegXRegOffset(reg, xreg, offset, scale, target_size) => {
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let index = sign_extend_to_long(self.get_x_reg_value(xreg), target_size) << scale;
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let addr = self.get_a_reg_mut(reg);
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get_address_sized(system, (*addr).wrapping_add(offset as u32).wrapping_add(index as u32) as Address, size)
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Target::IndirectMemoryPreindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32).wrapping_add(index_value as u32) as Address, Size::Long)?;
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get_address_sized(system, intermediate.wrapping_add(outer_disp as u32) as Address, size)
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},
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Target::IndirectMemoryPostindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32) as Address, Size::Long)?;
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get_address_sized(system, intermediate.wrapping_add(index_value as u32).wrapping_add(outer_disp as u32) as Address, size)
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},
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Target::IndirectMemory(addr) => {
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get_address_sized(system, addr as Address, size)
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},
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Target::IndirectPCOffset(offset) => {
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get_address_sized(system, (self.decoder.start + 2).wrapping_add(offset as u32) as Address, size)
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},
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Target::IndirectPCXRegOffset(xreg, offset, scale, target_size) => {
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let index = sign_extend_to_long(self.get_x_reg_value(xreg), target_size) << scale;
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get_address_sized(system, (self.decoder.start + 2).wrapping_add(offset as u32).wrapping_add(index as u32) as Address, size)
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},
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_ => return Err(Error::new(&format!("Unimplemented addressing target: {:?}", target))),
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}
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}
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@ -740,14 +746,22 @@ impl M68k {
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*addr -= size.in_bytes();
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set_address_sized(system, *addr as Address, value, size)?;
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},
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Target::IndirectARegOffset(reg, offset) => {
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let addr = self.get_a_reg_mut(reg);
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set_address_sized(system, (*addr).wrapping_add(offset as u32) as Address, value, size)?;
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Target::IndirectRegOffset(base_reg, index_reg, displacement) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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set_address_sized(system, base_value.wrapping_add(displacement as u32).wrapping_add(index_value as u32) as Address, value, size)?;
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},
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Target::IndirectARegXRegOffset(reg, xreg, offset, scale, target_size) => {
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let index = sign_extend_to_long(self.get_x_reg_value(xreg), target_size) << scale;
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let addr = self.get_a_reg_mut(reg);
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set_address_sized(system, (*addr).wrapping_add(offset as u32).wrapping_add(index as u32) as Address, value, size)?;
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Target::IndirectMemoryPreindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32).wrapping_add(index_value as u32) as Address, Size::Long)?;
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set_address_sized(system, intermediate.wrapping_add(outer_disp as u32) as Address, value, size);
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},
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Target::IndirectMemoryPostindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32) as Address, Size::Long)?;
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set_address_sized(system, intermediate.wrapping_add(index_value as u32).wrapping_add(outer_disp as u32) as Address, value, size);
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},
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Target::IndirectMemory(addr) => {
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set_address_sized(system, addr as Address, value, size)?;
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@ -757,28 +771,29 @@ impl M68k {
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Ok(())
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}
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pub fn get_target_address(&mut self, target: Target) -> Result<u32, Error> {
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pub fn get_target_address(&mut self, system: &System, target: Target) -> Result<u32, Error> {
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let addr = match target {
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Target::IndirectAReg(reg) | Target::IndirectARegInc(reg) | Target::IndirectARegDec(reg) => *self.get_a_reg_mut(reg),
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Target::IndirectARegOffset(reg, offset) => {
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let addr = self.get_a_reg_mut(reg);
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(*addr).wrapping_add(offset as u32)
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Target::IndirectRegOffset(base_reg, index_reg, displacement) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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base_value.wrapping_add(displacement as u32).wrapping_add(index_value as u32)
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},
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Target::IndirectARegXRegOffset(reg, xreg, offset, scale, target_size) => {
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let index = sign_extend_to_long(self.get_x_reg_value(xreg), target_size) << scale;
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let addr = self.get_a_reg_mut(reg);
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(*addr).wrapping_add(offset as u32).wrapping_add(index as u32)
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Target::IndirectMemoryPreindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32).wrapping_add(index_value as u32) as Address, Size::Long)?;
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intermediate.wrapping_add(outer_disp as u32)
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},
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Target::IndirectMemoryPostindexed(base_reg, index_reg, base_disp, outer_disp) => {
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let base_value = self.get_base_reg_value(base_reg);
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let index_value = self.get_index_reg_value(&index_reg);
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let intermediate = get_address_sized(system, base_value.wrapping_add(base_disp as u32) as Address, Size::Long)?;
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intermediate.wrapping_add(index_value as u32).wrapping_add(outer_disp as u32)
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},
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Target::IndirectMemory(addr) => {
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addr
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},
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Target::IndirectPCOffset(offset) => {
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(self.decoder.start + 2).wrapping_add(offset as u32)
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},
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Target::IndirectPCXRegOffset(xreg, offset, scale, target_size) => {
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let index = sign_extend_to_long(self.get_x_reg_value(xreg), target_size) << scale;
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(self.decoder.start + 2).wrapping_add(offset as u32).wrapping_add(index as u32)
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},
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_ => return Err(Error::new(&format!("Invalid addressing target: {:?}", target))),
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};
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Ok(addr)
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@ -800,6 +815,31 @@ impl M68k {
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}
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}
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fn get_x_reg_value(&self, xreg: XRegister) -> u32 {
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match xreg {
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XRegister::DReg(reg) => self.state.d_reg[reg as usize],
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XRegister::AReg(reg) => self.state.a_reg[reg as usize],
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}
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}
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fn get_base_reg_value(&self, base_reg: BaseRegister) -> u32 {
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match base_reg {
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BaseRegister::None => 0,
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BaseRegister::PC => self.decoder.start + 2,
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BaseRegister::AReg(reg) if reg == 7 => if self.is_supervisor() { self.state.msp } else { self.state.usp },
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BaseRegister::AReg(reg) => self.state.a_reg[reg as usize],
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}
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}
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fn get_index_reg_value(&self, index_reg: &Option<IndexRegister>) -> i32 {
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match index_reg {
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None => 0,
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Some(IndexRegister { xreg, scale, size }) => {
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sign_extend_to_long(self.get_x_reg_value(*xreg), *size) << scale
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}
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}
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}
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fn get_control_reg_mut(&mut self, control_reg: ControlRegister) -> &mut u32 {
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match control_reg {
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ControlRegister::VBR => &mut self.state.vbr,
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@ -820,13 +860,6 @@ impl M68k {
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}
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}
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fn get_x_reg_value(&self, xreg: XRegister) -> u32 {
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match xreg {
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XRegister::Data(reg) => self.state.d_reg[reg as usize],
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XRegister::Address(reg) => self.state.a_reg[reg as usize],
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}
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}
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#[inline(always)]
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fn is_supervisor(&self) -> bool {
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self.state.sr & (Flags:: Supervisor as u16) != 0
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@ -31,8 +31,22 @@ pub enum ShiftDirection {
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum XRegister {
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Data(u8),
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Address(u8),
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DReg(u8),
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AReg(u8),
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum BaseRegister {
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None,
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PC,
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AReg(u8),
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub struct IndexRegister {
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pub xreg: XRegister,
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pub scale: u8,
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pub size: Size,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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@ -41,11 +55,11 @@ pub enum RegOrImmediate {
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Immediate(u8),
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum ControlRegister {
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VBR,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Condition {
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True,
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@ -74,11 +88,10 @@ pub enum Target {
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IndirectAReg(Register),
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IndirectARegInc(Register),
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IndirectARegDec(Register),
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IndirectARegOffset(Register, i32),
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IndirectARegXRegOffset(Register, XRegister, i32, u8, Size),
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IndirectRegOffset(BaseRegister, Option<IndexRegister>, i32),
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IndirectMemoryPreindexed(BaseRegister, Option<IndexRegister>, i32, i32),
|
||||
IndirectMemoryPostindexed(BaseRegister, Option<IndexRegister>, i32, i32),
|
||||
IndirectMemory(u32),
|
||||
IndirectPCOffset(i32),
|
||||
IndirectPCXRegOffset(XRegister, i32, u8, Size),
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
@ -267,12 +280,36 @@ impl fmt::Display for ControlRegister {
|
||||
impl fmt::Display for XRegister {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
match self {
|
||||
XRegister::Data(reg) => write!(f, "d{}", reg),
|
||||
XRegister::Address(reg) => write!(f, "a{}", reg),
|
||||
XRegister::DReg(reg) => write!(f, "d{}", reg),
|
||||
XRegister::AReg(reg) => write!(f, "a{}", reg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl fmt::Display for BaseRegister {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
match self {
|
||||
BaseRegister::None => Ok(()),
|
||||
BaseRegister::PC => write!(f, "%pc + "),
|
||||
BaseRegister::AReg(reg) => write!(f, "%a{} + ", reg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn fmt_index_disp(index: &Option<IndexRegister>) -> String {
|
||||
match index {
|
||||
Some(index) => {
|
||||
let mut result = format!("%{}", index.xreg);
|
||||
if index.scale != 0 {
|
||||
result += &format!("<< {}", index.scale);
|
||||
}
|
||||
result += " + ";
|
||||
result
|
||||
},
|
||||
None => "".to_string(),
|
||||
}
|
||||
}
|
||||
|
||||
impl fmt::Display for Target {
|
||||
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
||||
match self {
|
||||
@ -282,17 +319,19 @@ impl fmt::Display for Target {
|
||||
Target::IndirectAReg(reg) => write!(f, "(%a{})", reg),
|
||||
Target::IndirectARegInc(reg) => write!(f, "(%a{})+", reg),
|
||||
Target::IndirectARegDec(reg) => write!(f, "-(%a{})", reg),
|
||||
Target::IndirectARegOffset(reg, offset) => write!(f, "(%a{} + #{:04x})", reg, offset),
|
||||
Target::IndirectARegXRegOffset(reg, xreg, offset, scale, _) => {
|
||||
let scale_str = if *scale != 0 { format!("<< {}", scale) } else { "".to_string() };
|
||||
write!(f, "(%a{} + %{} + #{:04x}{})", reg, xreg, offset, scale_str)
|
||||
Target::IndirectRegOffset(base_reg, index_reg, offset) => {
|
||||
let index_str = fmt_index_disp(index_reg);
|
||||
write!(f, "({}{}#{:04x})", base_reg, index_str, offset)
|
||||
},
|
||||
Target::IndirectMemoryPreindexed(base_reg, index_reg, base_disp, outer_disp) => {
|
||||
let index_str = fmt_index_disp(index_reg);
|
||||
write!(f, "([{}{}#{:08x}] + #{:08x})", base_reg, index_str, base_disp, outer_disp)
|
||||
},
|
||||
Target::IndirectMemoryPostindexed(base_reg, index_reg, base_disp, outer_disp) => {
|
||||
let index_str = fmt_index_disp(index_reg);
|
||||
write!(f, "([{}#{:08x}]{} + #{:08x})", base_reg, base_disp, index_str, outer_disp)
|
||||
},
|
||||
Target::IndirectMemory(value) => write!(f, "(#{:08x})", value),
|
||||
Target::IndirectPCOffset(offset) => write!(f, "(%pc + #{:04x})", offset),
|
||||
Target::IndirectPCXRegOffset(xreg, offset, scale, _) => {
|
||||
let scale_str = if *scale != 0 { format!("<< {}", scale) } else { "".to_string() };
|
||||
write!(f, "(%pc + %{} + #{:04x}{})", xreg, offset, scale_str)
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
3
todo.txt
3
todo.txt
@ -1,4 +1,7 @@
|
||||
|
||||
* rearrange the order of Target::IndirectARegXReg...
|
||||
* should you make a new type for the index, c/w proper Display formatter
|
||||
|
||||
* can you eventually make the system connections all configurable via a config file?
|
||||
* test using mpsc to pass messages with the tty IO thread, and test if it's slower than what you have now
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user