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Once again modified how the memory addressing works

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This commit is contained in:
transistor 2021-10-16 10:58:27 -07:00
parent 24e050a840
commit 853626584e
3 changed files with 18 additions and 11 deletions
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15
src/memory.rs
View File

@ -6,12 +6,14 @@ use crate::system::System;
use crate::devices::{Clock, Steppable, AddressableDeviceBox};
pub const MAX_READ: usize = 4;
pub type Address = u64;
/// A device that can be addressed to read data from or write data to the device.
pub trait Addressable {
fn len(&self) -> usize;
fn read(&mut self, addr: Address, count: usize) -> Result<Vec<u8>, Error>;
fn read(&mut self, addr: Address, count: usize) -> Result<[u8; MAX_READ], Error>;
fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error>;
fn read_u8(&mut self, addr: Address) -> Result<u8, Error> {
@ -80,8 +82,13 @@ impl Addressable for MemoryBlock {
self.contents.len()
}
fn read(&mut self, addr: Address, count: usize) -> Result<Vec<u8>, Error> {
Ok(self.contents[(addr as usize) .. (addr as usize + count)].to_vec())
fn read(&mut self, addr: Address, count: usize) -> Result<[u8; MAX_READ], Error> {
let mut data = [0; MAX_READ];
//self.contents[(addr as usize) .. (addr as usize + 4)].clone_from_slice(&data);
for i in 0..std::cmp::min(count, MAX_READ) {
data[i] = self.contents[(addr as usize) + i];
}
Ok(data)
}
fn write(&mut self, mut addr: Address, data: &[u8]) -> Result<(), Error> {
@ -168,7 +175,7 @@ impl Addressable for Bus {
(block.base as usize) + block.length
}
fn read(&mut self, addr: Address, count: usize) -> Result<Vec<u8>, Error> {
fn read(&mut self, addr: Address, count: usize) -> Result<[u8; MAX_READ], Error> {
let (dev, relative_addr) = self.get_device_at(addr, count)?;
let result = dev.borrow_mut().read(relative_addr, count);
result

8
src/peripherals/ata.rs
View File

@ -3,7 +3,7 @@ use std::fs;
use crate::error::Error;
use crate::system::System;
use crate::memory::{Address, Addressable};
use crate::memory::{Address, Addressable, MAX_READ};
use crate::devices::{Clock, Steppable};
@ -69,13 +69,13 @@ impl Addressable for AtaDevice {
0x30
}
fn read(&mut self, addr: Address, count: usize) -> Result<Vec<u8>, Error> {
let mut data = vec![0; count];
fn read(&mut self, addr: Address, count: usize) -> Result<[u8; MAX_READ], Error> {
let mut data = [0; MAX_READ];
match addr {
ATA_REG_DATA_WORD => {
self.selected_count -= 2;
let offset = ((self.selected_sector * ATA_SECTOR_SIZE) + (ATA_SECTOR_SIZE -1 - self.selected_count)) as usize;
let offset = ((self.selected_sector * ATA_SECTOR_SIZE) + (ATA_SECTOR_SIZE - 1 - self.selected_count)) as usize;
data[0] = self.contents[offset];
data[1] = self.contents[offset + 1];
if self.selected_count == 0 {

6
src/peripherals/mc68681.rs
View File

@ -9,7 +9,7 @@ use nix::fcntl::{fcntl, FcntlArg};
use crate::error::Error;
use crate::system::System;
use crate::devices::{Clock, Steppable};
use crate::memory::{Address, Addressable};
use crate::memory::{Address, Addressable, MAX_READ};
const REG_MR1A_MR2A: Address = 0x01;
@ -275,8 +275,8 @@ impl Addressable for MC68681 {
0x30
}
fn read(&mut self, addr: Address, count: usize) -> Result<Vec<u8>, Error> {
let mut data = vec![0; count];
fn read(&mut self, addr: Address, count: usize) -> Result<[u8; MAX_READ], Error> {
let mut data = [0; MAX_READ];
match addr {
REG_SRA_RD => {