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https://github.com/transistorfet/moa.git
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More clippy fixes after updating rustc
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7bdd63bc76
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@ -153,9 +153,8 @@ impl System {
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pub fn exit_error(&mut self) {
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pub fn exit_error(&mut self) {
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for (_, dev) in self.devices.iter() {
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for (_, dev) in self.devices.iter() {
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match dev.borrow_mut().as_steppable() {
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if let Some(dev) = dev.borrow_mut().as_steppable() {
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Some(dev) => dev.on_error(self),
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dev.on_error(self);
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None => { },
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}
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}
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}
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}
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}
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}
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@ -385,7 +385,7 @@ impl M68kAssembler {
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[AssemblyOperand::Register(_), AssemblyOperand::Register(_)] => {
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[AssemblyOperand::Register(_), AssemblyOperand::Register(_)] => {
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let bit_reg = expect_data_register(lineno, &args[0])?;
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let bit_reg = expect_data_register(lineno, &args[0])?;
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let reg = expect_data_register(lineno, &args[1])?;
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let reg = expect_data_register(lineno, &args[1])?;
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self.output.push(opcode | ((bit_reg as u16) << 9) | direction | encode_size(operation_size) | (0b1 << 5) | reg);
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self.output.push(opcode | (bit_reg << 9) | direction | encode_size(operation_size) | (0b1 << 5) | reg);
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},
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},
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//[_] => {
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//[_] => {
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// let (effective_address, additional_words) = convert_target(lineno, &args[0], Size::Word, Disallow::NoRegsImmediateOrPC)?;
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// let (effective_address, additional_words) = convert_target(lineno, &args[0], Size::Word, Disallow::NoRegsImmediateOrPC)?;
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@ -129,7 +129,7 @@ impl M68kDecoder {
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} else {
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} else {
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let size = get_size(ins);
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let size = get_size(ins);
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let data = match size {
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let data = match size {
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Some(Size::Byte) => (self.read_instruction_word(memory)? as u32 & 0xFF),
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Some(Size::Byte) => self.read_instruction_word(memory)? as u32 & 0xFF,
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Some(Size::Word) => self.read_instruction_word(memory)? as u32,
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Some(Size::Word) => self.read_instruction_word(memory)? as u32,
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Some(Size::Long) => self.read_instruction_long(memory)?,
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Some(Size::Long) => self.read_instruction_long(memory)?,
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None => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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None => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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@ -433,8 +433,8 @@ impl M68k {
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//Instruction::BKPT(u8) => {
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//Instruction::BKPT(u8) => {
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//},
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//},
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Instruction::CHK(target, reg, size) => {
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Instruction::CHK(target, reg, size) => {
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let upper_bound = sign_extend_to_long(self.get_target_value(target, size, Used::Once)?, size) as i32;
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let upper_bound = sign_extend_to_long(self.get_target_value(target, size, Used::Once)?, size);
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let dreg = sign_extend_to_long(self.state.d_reg[reg as usize], size) as i32;
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let dreg = sign_extend_to_long(self.state.d_reg[reg as usize], size);
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self.set_sr(self.state.sr & 0xFFF0);
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self.set_sr(self.state.sr & 0xFFF0);
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if dreg < 0 || dreg > upper_bound {
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if dreg < 0 || dreg > upper_bound {
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@ -494,7 +494,7 @@ impl M68k {
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let (remainder, quotient, overflow) = match sign {
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let (remainder, quotient, overflow) = match sign {
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Sign::Signed => {
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Sign::Signed => {
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let dest_val = dest_val as i32;
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let dest_val = dest_val as i32;
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let src_val = sign_extend_to_long(src_val, Size::Word) as i32;
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let src_val = sign_extend_to_long(src_val, Size::Word);
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let quotient = dest_val / src_val;
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let quotient = dest_val / src_val;
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(
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(
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(dest_val % src_val) as u32,
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(dest_val % src_val) as u32,
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@ -514,7 +514,7 @@ impl M68k {
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// Only update the register if the quotient was large than a 16-bit number
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// Only update the register if the quotient was large than a 16-bit number
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if !overflow {
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if !overflow {
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self.set_compare_flags(quotient as u32, Size::Word, false, false);
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self.set_compare_flags(quotient, Size::Word, false, false);
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self.state.d_reg[dest as usize] = (remainder << 16) | (0xFFFF & quotient);
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self.state.d_reg[dest as usize] = (remainder << 16) | (0xFFFF & quotient);
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} else {
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} else {
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self.set_flag(Flags::Carry, false);
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self.set_flag(Flags::Carry, false);
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@ -617,7 +617,7 @@ impl M68k {
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let value = *self.get_a_reg_mut(reg);
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let value = *self.get_a_reg_mut(reg);
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self.set_address_sized(sp as Address, value, Size::Long)?;
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self.set_address_sized(sp as Address, value, Size::Long)?;
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*self.get_a_reg_mut(reg) = sp;
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*self.get_a_reg_mut(reg) = sp;
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*self.get_stack_pointer_mut() = (sp as i32).wrapping_add(offset as i32) as u32;
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*self.get_stack_pointer_mut() = (sp as i32).wrapping_add(offset) as u32;
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},
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},
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Instruction::LSd(count, target, size, shift_dir) => {
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Instruction::LSd(count, target, size, shift_dir) => {
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let count = self.get_target_value(count, size, Used::Once)? % 64;
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let count = self.get_target_value(count, size, Used::Once)? % 64;
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@ -1540,7 +1540,7 @@ fn shift_operation(value: u32, size: Size, dir: ShiftDirection, arithmetic: bool
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match size {
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match size {
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Size::Byte => (((value as u8) << 1) as u32, bit),
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Size::Byte => (((value as u8) << 1) as u32, bit),
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Size::Word => (((value as u16) << 1) as u32, bit),
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Size::Word => (((value as u16) << 1) as u32, bit),
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Size::Long => ((value << 1) as u32, bit),
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Size::Long => (value << 1, bit),
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}
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}
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},
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},
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ShiftDirection::Right => {
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ShiftDirection::Right => {
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@ -1558,7 +1558,7 @@ fn rotate_operation(value: u32, size: Size, dir: ShiftDirection, use_extend: Opt
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match size {
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match size {
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Size::Byte => (mask | ((value as u8) << 1) as u32, bit),
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Size::Byte => (mask | ((value as u8) << 1) as u32, bit),
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Size::Word => (mask | ((value as u16) << 1) as u32, bit),
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Size::Word => (mask | ((value as u16) << 1) as u32, bit),
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Size::Long => (mask | (value << 1) as u32, bit),
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Size::Long => (mask | value << 1, bit),
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}
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}
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},
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},
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ShiftDirection::Right => {
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ShiftDirection::Right => {
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@ -433,7 +433,7 @@ impl fmt::Display for Instruction {
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Instruction::DBcc(cond, reg, offset) => write!(f, "db{}\t%d{}, {}", cond, reg, offset),
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Instruction::DBcc(cond, reg, offset) => write!(f, "db{}\t%d{}, {}", cond, reg, offset),
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Instruction::DIVW(src, dest, sign) => write!(f, "div{}w\t{}, %d{}", sign, src, dest),
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Instruction::DIVW(src, dest, sign) => write!(f, "div{}w\t{}, %d{}", sign, src, dest),
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Instruction::DIVL(src, desth, destl, sign) => {
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Instruction::DIVL(src, desth, destl, sign) => {
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let opt_reg = desth.map(|reg| format!("%d{}:", reg)).unwrap_or_else(|| "".to_string());
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let opt_reg = desth.map(|reg| format!("%d{}:", reg)).unwrap_or_default();
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write!(f, "div{}l\t{}, {}%d{}", sign, src, opt_reg, destl)
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write!(f, "div{}l\t{}, {}%d{}", sign, src, opt_reg, destl)
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},
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},
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@ -478,7 +478,7 @@ impl fmt::Display for Instruction {
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},
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},
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Instruction::MULW(src, dest, sign) => write!(f, "mul{}w\t{}, %d{}", sign, src, dest),
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Instruction::MULW(src, dest, sign) => write!(f, "mul{}w\t{}, %d{}", sign, src, dest),
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Instruction::MULL(src, desth, destl, sign) => {
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Instruction::MULL(src, desth, destl, sign) => {
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let opt_reg = desth.map(|reg| format!("%d{}:", reg)).unwrap_or_else(|| "".to_string());
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let opt_reg = desth.map(|reg| format!("%d{}:", reg)).unwrap_or_default();
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write!(f, "mul{}l\t{}, {}%d{}", sign, src, opt_reg, destl)
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write!(f, "mul{}l\t{}, {}%d{}", sign, src, opt_reg, destl)
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},
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},
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@ -73,7 +73,7 @@ pub fn run_threaded<I>(matches: ArgMatches, init: I) where I: FnOnce(&mut MiniFr
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{
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{
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let frontend = frontend.clone();
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let frontend = frontend.clone();
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thread::spawn(move || {
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thread::spawn(move || {
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let mut system = init(&mut *(frontend.lock().unwrap())).unwrap();
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let mut system = init(&mut frontend.lock().unwrap()).unwrap();
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frontend.lock().unwrap().finalize();
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frontend.lock().unwrap().finalize();
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system.run_loop();
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system.run_loop();
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});
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});
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@ -109,13 +109,10 @@ impl MC68681Port {
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if self.rx_enabled && (self.status & SR_RX_READY) == 0 && self.tty.is_some() {
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if self.rx_enabled && (self.status & SR_RX_READY) == 0 && self.tty.is_some() {
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let tty = self.tty.as_mut().unwrap();
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let tty = self.tty.as_mut().unwrap();
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let result = tty.read();
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let result = tty.read();
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match result {
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if let Some(input) = result {
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Some(input) => {
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self.input = input;
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self.input = input;
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self.set_rx_status(true);
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self.set_rx_status(true);
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return Ok(true);
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return Ok(true);
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},
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None => { },
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}
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}
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}
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}
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Ok(false)
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Ok(false)
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@ -316,9 +313,8 @@ impl Addressable for MC68681 {
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self.set_interrupt_flag(ISR_CH_A_TX_READY, false);
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self.set_interrupt_flag(ISR_CH_A_TX_READY, false);
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},
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},
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REG_CRA_WR => {
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REG_CRA_WR => {
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match self.port_a.handle_command(data[0]) {
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if let Some(value) = self.port_a.handle_command(data[0]) {
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Some(value) => self.set_interrupt_flag(ISR_CH_A_TX_READY, value),
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self.set_interrupt_flag(ISR_CH_A_TX_READY, value);
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None => { },
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}
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}
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},
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},
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REG_TBB_WR => {
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REG_TBB_WR => {
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@ -327,9 +323,8 @@ impl Addressable for MC68681 {
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self.set_interrupt_flag(ISR_CH_B_TX_READY, false);
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self.set_interrupt_flag(ISR_CH_B_TX_READY, false);
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},
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},
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REG_CRB_WR => {
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REG_CRB_WR => {
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match self.port_b.handle_command(data[0]) {
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if let Some(value) = self.port_b.handle_command(data[0]) {
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Some(value) => self.set_interrupt_flag(ISR_CH_B_TX_READY, value),
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self.set_interrupt_flag(ISR_CH_B_TX_READY, value);
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None => { },
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}
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}
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},
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},
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REG_CTUR_WR => {
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REG_CTUR_WR => {
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@ -431,7 +431,7 @@ impl Ym7101State {
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#[inline(always)]
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#[inline(always)]
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fn get_pattern_addr(&self, cell_table: usize, cell_x: usize, cell_y: usize) -> usize {
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fn get_pattern_addr(&self, cell_table: usize, cell_x: usize, cell_y: usize) -> usize {
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cell_table + ((cell_x + (cell_y * self.scroll_size.0 as usize)) << 1)
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cell_table + ((cell_x + (cell_y * self.scroll_size.0)) << 1)
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}
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}
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fn build_sprites_lists(&mut self) {
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fn build_sprites_lists(&mut self) {
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