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Updated readme
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README.md
14
README.md
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@ -7,10 +7,16 @@ Moa
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An emulator for m68k CPUs and devices. I originally started this project to
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distract myself while recovering from a bout of sickness. The idea was to
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emulate the computer I had built as part of the
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[computie project](https://github.com/transistorfet/computie).
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[computie project](https://transistorfet.github.io/projects/computie).
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Currently it can run the monitor program and load the kernel across serial
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(or the kernel can be loaded directly into memory), and it can boot the kernel,
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but an error occurs as soon as the kernel runs. It doesn't yet have interrupt
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support, but that will be the next thing added.
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(or the kernel can be loaded directly into memory), and it can boot the kernel.
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It opens two PTYs: one for the serial terminal, and one for the SLIP connection,
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and launches both `pyserial-miniterm` automatically connected to the console PTY,
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and launches `slattach` with the associated setup commands to create the SLIP
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device on the host, and set up routing.
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There are currently peripheral emulators for the MC68681 dual serial port
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controller, and the ATA device, which loads the compact flash image on startup,
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which the OS can read.
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@ -53,7 +53,8 @@ fn main() {
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Ok(()) => { },
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Err(err) => {
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system.exit_error();
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panic!("{:?}", err);
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println!("{:?}", err);
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break;
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},
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}
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}
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16
todo.txt
16
todo.txt
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@ -1,22 +1,10 @@
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* add a Signal struct which records its val and prev val, and can be used for state change things like interrupts
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the int controller coild have multiple for different prioritis, and could maybe be activated by multiple sources
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* the remaining issue with the shell is that putchar_buffered requires the TX interrupt and TX enable/disable commands to work in order to trigger a write
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* how will you add the cpu, which is not addressable, but is steppable, and also interruptable... what else?
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* how can you add 68030 support? Should it be all one module that checks maybe during decode if the instruction is supported? Should it 'inherit' from the MC68010 object
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* how can you have multple CPUs
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* should you simulate bus arbitration?
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* if the bus had an Rc<RefCell<Box<dyn AddressableDevice>>>, then it could be like AddressSpace used to be, with it's own Addressable, and then you could
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access one of multiple busses to do an op on it, rather than a single bus per machine
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* can you get rid of the duplicate read/write functions in System?
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* how do you pass in a mutable system to a mutable device? At the very least, I need the AddressSpace, but that needs access to the devices/memory segments.
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I could make System contain refcells for submutability
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* check all instructions in the docs
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* make tests for each instruction
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