From b8906fdbb13a3d5ab093153de907dfbd0c9c30cb Mon Sep 17 00:00:00 2001 From: transistor Date: Thu, 6 Jan 2022 23:40:22 -0800 Subject: [PATCH] Minor fixes --- src/host/gfx.rs | 5 +++++ src/peripherals/genesis/coprocessor.rs | 12 ++---------- src/peripherals/genesis/ym7101.rs | 6 +++--- 3 files changed, 10 insertions(+), 13 deletions(-) diff --git a/src/host/gfx.rs b/src/host/gfx.rs index 022d595..97e09b8 100644 --- a/src/host/gfx.rs +++ b/src/host/gfx.rs @@ -108,6 +108,11 @@ impl FrameSwapper { pub fn swap(&mut self) { std::mem::swap(&mut self.current.lock().unwrap().bitmap, &mut self.previous.lock().unwrap().bitmap); } + + pub fn set_size(&mut self, width: u32, height: u32) { + self.previous.lock().unwrap().set_size(width, height); + self.current.lock().unwrap().set_size(width, height); + } } impl WindowUpdater for FrameSwapper { diff --git a/src/peripherals/genesis/coprocessor.rs b/src/peripherals/genesis/coprocessor.rs index 1feabcf..211b48d 100644 --- a/src/peripherals/genesis/coprocessor.rs +++ b/src/peripherals/genesis/coprocessor.rs @@ -46,18 +46,10 @@ impl Addressable for CoprocessorCoordinator { match addr { 0x000 => { /* ROM vs DRAM mode */ }, 0x100 => { - if data[0] != 0 { - self.bus_request.set(true); - } else { - self.bus_request.set(false); - } + self.bus_request.set(data[0] != 0); }, 0x200 => { - if data[0] == 0 { - self.reset.set(true); - } else { - self.reset.set(false); - } + self.reset.set(data[0] == 0); }, _ => { warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr); }, } diff --git a/src/peripherals/genesis/ym7101.rs b/src/peripherals/genesis/ym7101.rs index 0bc4ebc..6805157 100644 --- a/src/peripherals/genesis/ym7101.rs +++ b/src/peripherals/genesis/ym7101.rs @@ -150,10 +150,10 @@ impl Ym7101Memory { } } - pub fn setup_transfer(&mut self, upper: u16, lower: u16) { + pub fn setup_transfer(&mut self, first: u16, second: u16) { self.ctrl_port_buffer = None; - self.transfer_type = ((((upper & 0xC000) >> 14) | ((lower & 0x00F0) >> 2))) as u8; - self.transfer_dest_addr = ((upper & 0x3FFF) | ((lower & 0x0003) << 14)) as u32; + self.transfer_type = ((((first & 0xC000) >> 14) | ((second & 0x00F0) >> 2))) as u8; + self.transfer_dest_addr = ((first & 0x3FFF) | ((second & 0x0003) << 14)) as u32; self.transfer_target = match self.transfer_type & 0x0E { 0 => Memory::Vram, 4 => Memory::Vsram,