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Fixed bug in ADDA/SUBA instructions

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This commit is contained in:
transistor 2021-11-03 15:30:38 -07:00
parent dc25a9f171
commit bd5a798fa1
3 changed files with 19 additions and 10 deletions
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4
src/cpus/m68k/decode.rs
View File

@ -437,7 +437,7 @@ impl M68kDecoder {
None => {
let size = if dir == 0 { Size::Word } else { Size::Long };
let target = self.decode_lower_effective_address(memory, ins, Some(size))?;
Ok(Instruction::SUB(target, Target::DirectAReg(reg), size))
Ok(Instruction::SUBA(target, reg, size))
},
}
},
@ -522,7 +522,7 @@ impl M68kDecoder {
None => {
let size = if dir == 0 { Size::Word } else { Size::Long };
let target = self.decode_lower_effective_address(memory, ins, Some(size))?;
Ok(Instruction::ADD(target, Target::DirectAReg(reg), size))
Ok(Instruction::ADDA(target, reg, size))
},
}
},

23
src/cpus/m68k/execute.rs
View File

@ -145,6 +145,7 @@ impl M68k {
}
self.state.pc = self.port.read_beu32((self.state.vbr + offset as u32) as Address)?;
Ok(())
}
@ -170,12 +171,15 @@ impl M68k {
let value = self.get_target_value(system, src, size)?;
let existing = self.get_target_value(system, dest, size)?;
let (result, carry) = overflowing_add_sized(existing, value, size);
match dest {
Target::DirectAReg(_) => { },
_ => self.set_compare_flags(result, size, carry, get_overflow(existing, value, result, size)),
}
self.set_compare_flags(result, size, carry, get_overflow(existing, value, result, size));
self.set_target_value(system, dest, result, size)?;
},
Instruction::ADDA(src, dest, size) => {
let value = self.get_target_value(system, src, size)?;
let existing = *self.get_a_reg_mut(dest);
let (result, carry) = overflowing_add_sized(existing, value, Size::Long);
*self.get_a_reg_mut(dest) = result;
},
Instruction::AND(src, dest, size) => {
let value = self.get_target_value(system, src, size)?;
let existing = self.get_target_value(system, dest, size)?;
@ -624,12 +628,15 @@ impl M68k {
let value = self.get_target_value(system, src, size)?;
let existing = self.get_target_value(system, dest, size)?;
let (result, carry) = overflowing_sub_sized(existing, value, size);
match dest {
Target::DirectAReg(_) => { },
_ => self.set_compare_flags(result, size, carry, get_overflow(existing, value, result, size)),
}
self.set_compare_flags(result, size, carry, get_overflow(existing, value, result, size));
self.set_target_value(system, dest, result, size)?;
},
Instruction::SUBA(src, dest, size) => {
let value = self.get_target_value(system, src, size)?;
let existing = *self.get_a_reg_mut(dest);
let (result, carry) = overflowing_sub_sized(existing, value, size);
*self.get_a_reg_mut(dest) = result;
},
Instruction::SWAP(reg) => {
let value = self.state.d_reg[reg as usize];
self.state.d_reg[reg as usize] = ((value & 0x0000FFFF) << 16) | ((value & 0xFFFF0000) >> 16);

2
src/cpus/m68k/instructions.rs
View File

@ -98,6 +98,7 @@ pub enum Target {
pub enum Instruction {
ABCD(Target, Target),
ADD(Target, Target, Size),
ADDA(Target, Register, Size),
ADDX(Target, Target, Size),
AND(Target, Target, Size),
ANDtoCCR(u8),
@ -184,6 +185,7 @@ pub enum Instruction {
Scc(Condition, Target),
STOP(u16),
SUB(Target, Target, Size),
SUBA(Target, Register, Size),
SUBX(Target, Target, Size),
SWAP(Register),