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Fixed final major bug with hscroll, where I needed to multiply by 32 instead of 16

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transistor 2021-12-26 21:29:01 -08:00
parent ac9ec8840c
commit bf938855e1
2 changed files with 16 additions and 3 deletions
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10
docs/log.txt
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@ -223,6 +223,16 @@ before 2021-10-25
has to be looked up for ever column, so swapping the vscroll and hscroll between the inner and has to be looked up for ever column, so swapping the vscroll and hscroll between the inner and
outer loops fixed the issue perfectly. Kind of odd that it wasn't more broken when inverted outer loops fixed the issue perfectly. Kind of odd that it wasn't more broken when inverted
- now I've noticed there's a scroll problem in Ren & Stimpy. Every other cell's hscroll is 0
- looks like address 0x264 is the start of the transfer to the hscroll table in vram
0x83e2 is the function that calls 0x244. 244 sets up the transfer and 83e2 sends the data
- the auto-increment is set to 0x20 which leaves that 0 in between, but after thinking about it more,
I realized that's correct, and that it's actually 32 bytes (16 words) between each scroll value,
The bug was in the hscroll function which I didn't actually fix properly. I modified it to
multiply the line by 4 instead of 2, but I also needed to shift to the hcell value by 5 instead
of 4 (multiply by 32 instead of 16) to get the proper base scroll
Now, Ren & Stimpy works, and Sonic 2's Scroll B actually looks right

9
src/peripherals/genesis/ym7101.rs
View File

@ -324,8 +324,8 @@ impl Ym7101State {
pub fn get_hscroll(&self, hcell: usize, line: usize) -> (u32, u32) { pub fn get_hscroll(&self, hcell: usize, line: usize) -> (u32, u32) {
let base_addr = match self.mode_3 & MODE3_BF_H_SCROLL_MODE { let base_addr = match self.mode_3 & MODE3_BF_H_SCROLL_MODE {
0 => self.hscroll_addr, 0 => self.hscroll_addr,
2 => self.hscroll_addr + (hcell << 4), 2 => self.hscroll_addr + (hcell << 5),
3 => self.hscroll_addr + (hcell << 4), 3 => self.hscroll_addr + (hcell << 5),
_ => panic!("Unsupported horizontal scroll mode"), _ => panic!("Unsupported horizontal scroll mode"),
}; };
@ -456,7 +456,9 @@ impl Ym7101State {
for cell_y in 0..cells_v { for cell_y in 0..cells_v {
for cell_x in 0..cells_h { for cell_x in 0..cells_h {
let pattern_w = read_beu16(&self.vram[self.get_pattern_addr(cell_table, cell_x as usize, cell_y as usize)..]); let pattern_w = read_beu16(&self.vram[self.get_pattern_addr(cell_table, cell_x as usize, cell_y as usize)..]);
self.draw_pattern(frame, pattern_w, (cell_x << 3) as u32, (cell_y << 3) as u32); if pattern_w != 0 {
self.draw_pattern(frame, pattern_w, (cell_x << 3) as u32, (cell_y << 3) as u32);
}
} }
} }
} }
@ -837,6 +839,7 @@ impl Ym7101State {
println!("DMA Source: {:#06x}", self.transfer_src_addr); println!("DMA Source: {:#06x}", self.transfer_src_addr);
println!("DMA Dest : {:#06x}", self.transfer_dest_addr); println!("DMA Dest : {:#06x}", self.transfer_dest_addr);
println!("DMA Count : {:#06x}", self.transfer_count); println!("DMA Count : {:#06x}", self.transfer_count);
println!("Auto-Inc : {:#06x}", self.transfer_auto_inc);
} }
pub fn dump_vram(&self) { pub fn dump_vram(&self) {